JP3057751B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] A semiconductor memory, in particular, a read circuit of a pre-charge type ROM, is intended to reduce power consumption by eliminating unnecessary pre-charge, and to form a block of memory cells. Selecting a precharge transistor inserted between each cell block and a precharge power supply to be turned on when the cell block is selected and turned off when the cell block is not selected in a semiconductor memory performing a precharge type readout It is configured to provide a circuit.

[Industrial applications]

The present invention relates to a semiconductor memory, and more particularly to a read circuit of a precharge type ROM.

The one-chip microcomputer has a pre-charge type memory (ROM), and the capacity of the built-in memory is increasing, and the power consumption is increasing accordingly. However, one-chip microcomputers are required to have low power consumption, such as being usable with batteries.

[Conventional technology]

The ROM also tends to block the memory cell group as the capacity increases, and 1A to 1E in FIG. 6 are the memory cell blocks. Block select gates 3A to 3E are inserted in the read data circuit of each block, and the gates (transistors) are turned on / off by the decode signal BDS of the block select decoder. In reading, the bit line circuit is precharged and stored in the selected memory cell (on / off).
, And the subsequent bit line potential is taken out via the sense amplifier SA. 2A to 2E are precharge gates, and PCS is a precharge signal for turning on / off this gate (transistor).

[Problems to be solved by the invention]

As shown in FIG. 6, in the conventional precharge type ROM,
The precharge circuit is common, and when the precharge signal PCS is input, the transistors 2A to 2E are turned on, and the cell block 1A
11E are simultaneously precharged by the power supply V _CC .

The memory cell to be read is one cell block, for example.
Only one gate in this example, 3C, is in 1C and is therefore turned on by the decode signal BDS, and the other gates are off. As described above, in the conventional method, cell blocks that do not contribute to reading are precharged, and there is wasteful power consumption.

An object of the present invention is to improve this point and reduce power consumption by eliminating unnecessary precharge.

[Means for solving the problem]

As shown in FIG. 1, in the present invention, cell blocks 1A to 1E
And providing the selection circuit 5 to turn on / off individually the inserted precharging transistor 2A~2E between the precharge power source V _CC.

The selection circuit 5 is specifically a decoder, receives an address for selecting a cell block, and turns on the transistor when the cell block is selected.

[Action]

In this configuration, when a cell block, for example, 1A is selected (read), only the transistor 2A is turned on and the remaining transistors 2B to 2E are off, so that only the cell block 1A is precharged and the remaining Cells 1B to 1E are not precharged. Therefore, non-selected cell blocks other than the selected cell block are also precharged, so that power is not wasted.

The transistors 2A to 2E are also provided in the conventional circuit of FIG. 4, and the present invention utilizes them.

〔Example〕

FIG. 2 shows an embodiment of the present invention. The cell array 1A includes memory cells 9a,..., 9d,... And discharge cells (transistors) 9g, 9h. Memory cells 9a, 9d,
The gate of the ... word lines l _1, connected to the ...., cell 9 g, the gate of 9h for discharge is connected to a line l ₅ for receiving the discharge signal DCS. Cell 9a and not shown 9b,
...... it is connected in series with the cell 9g The cells 9d and not shown 9e,, ...... are connected in series with the cell 9h, and these series connection is connected in parallel to the bit line l _6. Two cells 9a and 9d, 9b and 9e connected to the same word line,
Are alternately turned on, for example, 9a, 9e,... Are always turned on by depletion, and 9d, 9b,.
This is a true memory cell that is turned off.

Such cell group located plurality in the cell array 1A, each bit line l ₆ to l ₉ is connected to a common bus l ₁₀ via the column gate 10 a to 10 d. The same applies to the cell arrays 1B and 1C. These cell array, the pre-charge transistor 2A~2C is inserted between the common bus and the power supply V _CC of the l ₁₀ equivalent.

The common bus l ₁₀ connects latch composed of inverters I _1, I _2, inverter I _3, through a block selection transistor 3A to the common bus l _11. The same applies to the other blocks 1B and 1C. This bus l ₁₁ is also connected via a precharging transistor 4 to the power supply V _CC. Furthermore, it is connected to the power supply V _CC via the holding transistor 7 and to the processor CPU via the sense amplifier SA composed of inverters I ₄ and I ₅ .

3 and 4 show time charts of the signals BPS, BDS,..., And FIG. 5 shows a circuit for generating these signals. A ₀
To A ₁₁ in each bit of the address, the A ₀ to A ₂ is BDS, A ₃ is
PCS, A ₄ ~A ₇ is CDS, A ₈ ~A ₁₁ are for WDS occur.

When the memory (ROM) is read, assuming that the memory cell to be read is 9d, each signal BPS, PCS,... Is output as shown at point t in FIG. As a result, the transistor 4 is turned on by the precharge signal BPS, the transistor 3A is turned on by the decode signal BDS, the transistor 2A is turned on by the precharge selection signal PCS, and the decode signal C
DS turns on transistor 10a, discharge signal D
Transistor 9g by CS, 9h is off, the bit line l ₆ of the cell array 1A, the bus l _10, to precharge a bus l ₁₁ by the power supply V _CC. The transistors 2B (not shown), 2C, etc. of the cell arrays 1B, 1C are off, so that the buses and bit lines of these cell arrays are not precharged. As a result, power consumption can be reduced.

In a ROM of a type in which a plurality of memory cells are connected in series, when a word line is not selected, the memory cell is on, and when the word line is selected, the memory cell is on or off according to storage data. At the time of the precharge, the memory cell is on because the word line is not selected, and cannot be precharged as it is, but is turned off by the transistors 9g and 9h discharge signals DCS, so that bit line precharge is possible.

Next, in the word line example, l _{1 is set} to the selection level. The discharge signal DCS returns to the H level, and the transistor 9g,
Turn on 9h. The transistors 2A and 4 are turned off at the end of the precharge. If cell 9d is on, bit line l ₆
Is discharged to the L level, and if the cell 9d is turned off, the bit line ₁₆ remains at the H level before precharging.

The potential of the bit line ₁₆ is held by the latches I ₁ and I ₂ . For example l ₆ Therefore l ₁₀ is H if the output of the inverter I ₁ is L, the output of the inverter I ₂ In response to this H, therefore l _10,
Also l ₆ is in a floating above H, the L level is held. This also applies when l ₆ is at the L level.

Read output latch I ₁ potential thus cell array 1A bus l _10, I _2, inverter I _3, transistors 3A, buses l _11, are taken out to the outside through the sense amplifier S _A. For example, the output of the bus l ₁₀ is latched I ₁ If H is L, the output of the inverter I _2, I ₃ is H, which enters into the bus l ₁₁ through transistor 3A, l ₁₁
To H (for details, leave the precharge). If the bus l ₁₀ is L level, the output of the latch I ₁ is H, the output of the inverter I _2, I ₃ is L, H-level bus l ₁₁ precharge therefore becomes L level to discharge through the transistor 3A.

Output bus l ₁₁ is H if the inverter I ₄ is L, the output of the inverter I ₅ is H, the transistor 7 is on, H level l ₁₁ is held by the power supply V _CC. The output of the l ₁₁ is L if the inverter I ₄ is H, the output of the inverter I ₅ is L, the transistor 7 is off, l ₁₁ is at L level orゝ.

The provision of the latch / hold circuit can further reduce the precharge power. That is, when the bus l ₁₀ in cell readout is to become H level, which if held by the latch I _1, I _2, precharge current when pre-charging the cell array 1A on the next read does not flow almost, Power savings. Hold circuit by the inverter I ₄ and the transistor 7 and the like are also the same.

The selection circuit 5 in FIG. 1 corresponds to an output section of the precharge selection signal PCS of the decoder 6 in FIG.

The BDS and BPS in FIG. 3 are the same as those in FIG. 4, but FIG. 3 (3) shows the conventional SA output, and FIG. 3 (4) shows the SA output of the present invention. The SA output is changed every time since it is not held in the conventional method, but is held in the present invention, so that the SA output is unchanged if the next read data is the same H / L as the previous read data.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the precharge power of a precharge type memory in which a cell array is divided into blocks, and it is possible to obtain an advantage that the circuit is not increased.

[Brief description of the drawings]

1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIGS. 3 and 4 are waveform diagrams for explaining the operation, and FIG. 5 is an example of a circuit for generating various signals. FIG. 6 is an explanatory diagram of a conventional example. In FIG. 1, 1A,... Are cell blocks, 2A,... Are precharge transistors, and 3A,.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-229596 (JP, A) JP-A-2-71500 (JP, A) JP-A-60-239997 (JP, A) JP-A-60-229 76094 (JP, A)

Claims (3)

(57) [Claims] A word decode signal (WD) for selecting a word line is commonly provided to a plurality of cell blocks.
S) and a column decode signal (CDS) for selecting a bit line are input, and each cell block receives one word decode signal (WDS) and one column decode signal (CDS).
A bit line of one cell block selected by a block decode signal (BDS) for cell block selection, wherein the bit lines are simultaneously selected, and the word decode is performed in each of the cell blocks. A bus (l ₁₀ ) to which a bit line selected by a signal (WDS) and a column decode signal (CDS) is connected, and a bus provided between the bus (l ₁₀ ) and a precharge power supply for each of the cell blocks. .., And an address decode signal (PCS) for selecting a precharge transistor of a selected cell block among the precharge transistors (2A,...) Of each of the cell blocks. To turn on and turn off the precharge transistors of other unselected cell blocks. And a selector circuit. 2. A bus (l ₁₀ ) to which a bit line selected in each cell block is connected is provided with a latch (I ₁ , I ₂ ) for holding a high / low potential of the bus. The semiconductor memory according to claim 1, wherein: Wherein the bus the bus (l ₁₀₎ to a selected bit line in each cell block is connected is connected through a block selection transistor _{(3A, ......) (l 11} )
3. The semiconductor memory according to claim 1, further comprising a circuit (7, SA) for holding a high / low potential of the bus.