JP3059589B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Contents] Industrial application field Conventional technology (FIG. 78) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 12) Action Embodiment (1) First Embodiment (FIGS. 13 to 15) (2) Description of the second embodiment (FIG. 16) (3) Description of the third embodiment (FIGS. 17 to 33) (4) Description of the fourth embodiment (FIG. 34-53) (5) Description of the fifth embodiment (FIG. 54 (a)) (6) Description of the sixth embodiment (FIG. 54 (b)) (7) Description of the seventh embodiment (FIG. 54) 55 (a)) (8) Description of the eighth embodiment (FIG. 55 (b)) (9) Description of the ninth embodiment (FIG. 56) (10) Description of the tenth embodiment (FIG. 57) (11) Description of the eleventh embodiment (FIGS. 58 to 67) (12) Description of the twelfth embodiment (FIGS. 68 to 77)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an improvement in a circuit configuration of a basic cell of a programmable gate array (hereinafter referred to as an FPGA).

In recent years, with the demand for higher integration, higher density, and higher functionality of semiconductor integrated circuit (hereinafter referred to as LSI) devices, FPGAs (Field Programmable Gate Arrays) have attracted attention as ASICs that can be programmed by the user. Have been. The FPGA can be provided to the user at an early stage, and is mainly used as a chip for a new development or a prototype of an electronic product.

For example, in a FPGA, a PLD (Programmable Logic Device) for programming an AND-OR plane with a fuse (or an antifuse) is provided.
There is also a type in which a circuit block and a switch box are programmed by information stored in a memory.

[0005] Further, as in the conventional gate array, there is a type which comprises a circuit block row and a wiring area, and these are programmed by a fuse or an anti-fuse. According to this, a basic cell that allows only a specific logic circuit to be combined is applied, and that is the minimum unit. For this reason, the number of transistors constituting the basic cell increases.

Further, the transistor pair tile portion and R
In a basic cell having two types of minimum units, the AM logic tile portion, when the usage ratio of the number of macros provided in the chip is different, the circuit usage ratio is reduced.

Therefore, the number of transistors and the number of program points are reduced as much as necessary without depending on many transistors in relation to the circuit configuration of the basic cell.
There is a demand for an apparatus that can form various types of basic logic circuits by performing the combination and program processing.

[0008]

2. Description of the Related Art FIG. 78 is an explanatory diagram of a semiconductor integrated circuit device according to a conventional example, and shows a configuration diagram of a logic circuit included in a basic cell of an FPGA. For example, as an ASIC that can be programmed by a user, an FPGA (Field Pro
The basic cells that make up the grammable gate array have I
EEE JOURNAL OF SOLID-STATE CIRCUITS VOL 24.NO
3. Logic circuit as seen in JUNE 1989 (Logic mod)
ule schematic) is applicable.

In FIG. 78, according to the logic circuit, 6
AND-AND circuits (hereinafter simply referred to as first to sixth AND circuits) AND1 to AND6, and three inverter circuits (hereinafter simply referred to as first to third inverters) IN1 to IN3,3
Two two-input OR circuits (hereinafter simply referred to as first to third OR circuits) OR1 to OR3, one two-input NOR circuit NOR and 1
It consists of buffer circuits BUF.

Further, for example, a three-input logic circuit, a four-input logic circuit, a two-input exclusive-OR circuit, and a D-type latch circuit can be constituted by one unit function of the logic circuit. A D-type flip-flop circuit can be configured by a two-unit function combining two logic circuits.

Note that wiring areas are provided between the logic circuits, and program points are provided at horizontal and vertical intersections of the wiring leading to each circuit. Further, the plurality of program points are made of an antifuse or a fuse element, and a logic gate circuit can be arbitrarily assembled at the user's hand. When prototypes of electronics using these FPGAs are manufactured, their operation is verified, and then the chip gate array is re-created again, and the production is shifted to mass production.

[0012]

According to the logic circuit applied to the conventional basic cell, the first to sixth ANs
D circuits AND1 to AND6, first to third inverters IN1 to
IN3, first to third OR circuits OR1 to OR3, and a buffer circuit BUF.

Therefore, there is a first problem that the number of transistors constituting the basic cell increases. For example, if one two-input AND circuit is constituted by four transistors, the first to sixth AND circuits ND1
~ AND6 requires 24, and if it is configured with two transistors per one inverter circuit,
The first to third inverters IN1 to IN3 require six inverters.

Further, one two-input OR circuit or two-input NO
Assuming that each of the R circuits includes four transistors, the first to third OR circuits OR1 to OR3 require twelve, and the two-input NOR circuit requires four.
Further, if one buffer circuit BUF is composed of two transistors, a total of 48 transistors must be incorporated in the basic cell.

Thus, when there is a request to form a D-type flip-flop circuit, at least 96 transistors are required since the function of the logic circuit is required in two units.

The basic macro (logic circuit) as the minimum unit can be realized only by a specific combination circuit such as a three-input logic circuit, a four-input logic circuit, a two-input exclusive OR circuit, a D-type latch circuit, and the like. As a result, when a logic gate circuit having many small circuits such as an inverter circuit and a two-input NAND circuit is assembled, there is a second problem that the use efficiency (circuit utilization rate) is reduced.

As the other basic cells, there is a cell having two types of minimum units, that is, a transistor pair tile for realizing a combinational circuit and a RAM logic tile for realizing a flip-flop. However, since two types of basic macros are required at the time of programming, if the usage ratio of the number of macros provided in the chip is different, the circuit usage ratio is reduced.

In order to shorten the programming time of the FPGA, it is desirable that the number of program points for connecting the transistors constituting the basic cell and the wiring leading to the transistors be small. Furthermore, since the program points after the program processing have a contact resistance of about 50 to 500 [Ω], it is necessary to reduce the number of program points as much as possible in order to increase the speed of the transistor operation.

The present invention has been made in view of the above-mentioned problems of the prior art. The present invention is not limited to a large number of transistors and depends on the circuit configuration of the basic cell. Less
It is an object of the present invention to provide a semiconductor integrated circuit device capable of forming various types of basic logic circuits by performing the combination and the program processing.

[0020]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first source or drain extraction electrode (SD1); and a second drain or source. A first transistor (T1) including an extraction electrode (SD2); a second transistor including a third source or drain extraction electrode (SD3); and a second drain or source extraction electrode (SD2). Transistor (T2)
A third transistor (T3) including a fourth source or drain lead electrode (SD4) and a fifth drain or source lead electrode (SD5); and a sixth source or drain lead electrode (SD5). SD6) and a fourth transistor (T4) including the fifth drain or source extraction electrode (SD5), and a gate (G) of the first to fourth transistors (T1 to T4). The input wiring (Lin) connected to the first source or drain lead electrode (SD1) via a first high-potential-side program switch (PD1) and a second high-potential-side program switch ( PD2) via a first power supply line (VDD) connected to the second drain or source lead electrode (SD2) and a first low potential side program switch (PS1). A second power supply connected to the source or drain extraction electrode (SD4) and to the fifth drain or source extraction electrode (SD5) via the second low-potential side program switch (PS2). Line (VSS) and a second source or drain extraction electrode (S2) via a second program switch (P2).
D1), and the second drain or source extraction electrode (S3) is connected via a third program switch (P3).
D2), and via the fourth program switch (P4), the third source or drain extraction electrode (S
D3) and a fourth source or drain extraction electrode (SD4) via an eighth program switch (P8).
And the sixth source or drain extraction electrode (S) via a twelfth program switch (P12).
D6), a first output wiring (Lout 1) connected to
Connected to the fourth source or drain lead-out electrode (SD4) through the program switch (P1).
Connected to the third source or drain lead-out electrode (SD3) through the program switch (P5).
Connected to the fourth source or drain lead-out electrode (SD4) via the program switch (P9).
0 is connected to the fifth drain or source lead electrode (SD5) through a program switch (P10)
A second output wiring (Lout 2) connected to the sixth source or drain lead electrode (SD6) via an eleventh program switch (P11), and a first source or drain lead electrode ( A first high-potential side spare line (LP1) connected to the third source or drain lead electrode (SD3) via a sixth program switch (P6); A second high-potential-side spare line (LP2) connected to the first output line (Lout1) via a program switch (P7), and a connection to the fourth source or drain lead electrode (SD4). The first low-potential side spare line (LN1) connected to the sixth source or drain lead electrode (SD6) via the thirteenth program switch (P13), and the fourteenth program switch (P13) 4) through the second output wiring (second low-potential-side auxiliary wiring connected to the Lout 2) (LN2), and having a.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
As shown in FIG. 2, in the semiconductor integrated circuit device according to the first aspect of the present invention, the semiconductor integrated circuit device is provided between the first power supply line (VDD) and the third source or drain lead electrode (SD3). Third high potential side program switch (PD3)
And a third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). Semiconductor integrated circuit device.

A semiconductor integrated circuit device according to claim 3 is
As shown in FIG. 3, in the semiconductor integrated circuit device according to claim 1, the first source or drain lead electrode (SD1) is connected to the third source or drain lead electrode (SD3). A first bias program switch (PB1) provided therebetween, and a fourth source or drain lead electrode (SD6) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6). 2 bias program switches (PB2).

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
As shown in FIG. 4, in the semiconductor integrated circuit device according to claim 1, a third terminal provided between the first power supply line (VDD) and the third source or drain lead electrode (SD3). High-potential-side program switch (PD3), and a third low-potential-side program switch provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). (PS3) and a first source or drain extraction electrode (SD3) provided between the first source or drain extraction electrode (SD1) and the third source or drain extraction electrode (SD3).
Bias program switch (PB1) and the fourth
Source or drain extraction electrode (SD4) and the sixth
A second bias program switch (PB2) provided between the source and drain extraction electrodes (SD6)
It is characterized by having.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
5. The semiconductor integrated circuit device according to claim 1, wherein said first and second transistors (T1, T2) are p-type field-effect transistors, and said third and fourth transistors (T3, T4) are It is characterized by comprising an n-type field effect transistor.

A semiconductor integrated circuit device according to claim 6 is
5. The semiconductor integrated circuit device according to claim 1, wherein said program switches (PD1 to PD3, PS1 to PS3,
P1 to P14, PB1, PB2) are fuse elements, antifuse elements, or p-type or n-type field-effect transistors.

A semiconductor integrated circuit device according to claim 7 is
As shown in FIG. 5, a first transistor (T1) including a first source or drain extraction electrode (SD1) and a second drain or source extraction electrode (SD2), and a third source or drain. A second transistor (T2) including a drain extraction electrode (SD3) and the second drain or source extraction electrode (SD2); a fourth source or drain extraction electrode (SD4); A third transistor (T3) having a drain or source lead electrode (SD5), a sixth source or drain lead electrode (SD6) and the fifth drain or source lead electrode (SD5). A fourth transistor (T4), an input line (Lin) connected to the gates (G) of the first to fourth transistors (T1 to T4), and a first high-potential side program switch. (PD1) to the first source or drain lead electrode (SD1), and via the second high-potential side program switch (PD2), the second drain or source lead electrode (SD1). S
D2) connected to a first power supply line (VDD) connected to the fourth source or drain extraction electrode (SD4) via a first low-potential side program switch (PS1); 2 low side program switch (PS
2) a second power supply line (VSS) connected to the fifth drain or source extraction electrode (SD5) through the second power supply line (VSS);
Connected to the first source or drain extraction electrode (SD1) through the program switch (P2)
Connected to the second drain or source lead electrode (SD2) through the program switch (P3)
Connected to the third source or drain lead-out electrode (SD3) through the program switch (P4).
To the fourth source or drain lead electrode (SD4) via the program switch (P8), and to the sixth source or drain lead electrode (SD6) via the twelfth program switch (P12). Second connected
Is connected to the fourth source or drain lead electrode (SD4) via the first program switch (P1), and via the fifth program switch (P5). A tenth program switch connected to the third source or drain lead electrode (SD3) and connected to the fourth source or drain lead electrode (SD4) via a ninth program switch (P9); (P10) is connected to the fifth drain or source lead electrode (SD5), and is connected to the sixth source or drain lead electrode (SD6) via an eleventh program switch (P11). Connected to the second low-potential-side spare line (LN2) and the first source or drain lead electrode (SD1). And a first high-potential-side spare line (LP1) connected to the third source or drain lead electrode (SD3) and a second high-potential side via a fifteenth program switch (P15). Spare wiring (LP
2) is connected to the first output wiring (Lout 1) connected to the fourth source or drain lead electrode (SD4), and is connected to the sixth source or drain via the thirteenth program switch (P13). A first low-potential-side spare line (LN1) connected to the drain extraction electrode (SD6) and a second low-potential-side spare line (LN2) connected via a sixteenth program switch (P16). And a second output wiring (Lout 2).

The semiconductor integrated circuit device according to claim 8 is
As shown in FIG. 6, in the semiconductor integrated circuit device according to claim 7, a third terminal provided between the first power supply line (VDD) and the third source or drain lead electrode (SD3). High-potential side program switch (PD3),
A third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). .

According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
As shown in FIG. 7, in the semiconductor integrated circuit device according to claim 7, between the first source or drain extraction electrode (SD1) and the third source or drain extraction electrode (SD3). A first bias program switch (PB1) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6). And a bias program switch (PB2).

A semiconductor integrated circuit device according to a tenth aspect is the semiconductor integrated circuit device according to the seventh aspect, as shown in FIG. 8, wherein the first power supply line (VDD) and the third source or A third high-potential side program switch (PD3) provided between the drain extraction electrode (SD3)
A third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6); Alternatively, a first bias program switch (PB1) provided between the drain lead electrode (SD1) and the third source or drain lead electrode (SD3), and the fourth source or drain lead electrode (SD4) and a second bias program switch (PB) provided between the sixth source or drain lead electrode (SD6).
2), and

According to an eleventh aspect of the present invention, in the semiconductor integrated circuit device according to the seventh to tenth aspects, the first and second transistors (T1, T2) are formed from p-type field effect transistors. The third and fourth
Wherein the transistors (T3, T4) are n-type field effect transistors.

A semiconductor integrated circuit device according to a twelfth aspect is the semiconductor integrated circuit device according to the seventh to tenth aspects, wherein the program switches (PD1 to PD3, PS1 to PS3, P1 to P14, PB1, PB2) are different from each other. Fuse element,
It is characterized by comprising an anti-fuse element or a p-type or n-type field effect transistor.

The semiconductor integrated circuit device according to the thirteenth aspect includes, as shown in FIG. 9, a first source or drain lead electrode (SD1) and a second drain or source lead electrode (SD2). First transistor (T1)
A second transistor (T2) including a third source or drain lead electrode (SD3) and the second drain or source lead electrode (SD2); and a fourth source or drain lead electrode. A third transistor (T3) including (SD4) and a fifth drain or source extraction electrode (SD5); a sixth source or drain extraction electrode (SD6); and a fifth drain or source electrode. A fourth transistor (T4) having an extraction electrode (SD5)
A fifth transistor (T5) including a seventh source or drain lead electrode (SD7) and an eighth drain or source lead electrode (SD8); and a ninth source or drain lead electrode (SD7). A sixth transistor (T6) provided with SD9) and the eighth drain or source lead electrode (SD8); and a tenth source or drain lead electrode (SD10) and eleventh drain or source lead. Electrode (SD11) and a seventh transistor (T
7) and a twelfth source or drain extraction electrode (S
D12) and an eighth transistor (T8) comprising the eleventh drain or source lead electrode (SD11);
The first source or the input source (Lin) connected to the gates (G) of the first to eighth transistors (T1 to T8) and the first source or the source via a first high-potential side program switch (PD1); A second high-potential-side program switch (PD2) connected to the drain extraction electrode (SD1)
Connected to the second drain or source lead electrode (SD2) via a third high potential side program switch (PD3) to the fourth source or drain lead electrode (SD4). A first power supply line (VDD) connected to the fifth drain or source lead electrode (SD5) via a fourth high-potential side program switch (PD4); The drain or source of the eighth drain or source is connected to the seventh source or drain lead electrode (SD7) via the second program switch (PS1). Connected to the electrode (SD8), connected to the tenth source or drain extraction electrode (SD10) via a third low-potential side program switch (PS3), and connected to the fourth low-potential Use program switch (PS
4) a second power supply line (VSS) connected to the eleventh drain or source lead electrode (SD11) via
Connected to the first source or drain lead electrode (SD1) via a second program switch (P2);
Connected to the second drain or source lead electrode (SD2) via a third program switch (P3);
Connected to the third source or drain extraction electrode (SD3) via a fourth program switch (P4);
A fourth source or drain extraction electrode (SD4) is connected through an eighth program switch (P8),
Connected to the fifth drain or source lead-out electrode (SD5) through the program switch (P9).
Connected to the sixth source or drain lead electrode (SD6) through one program switch (P11);
The seventh source or drain extraction electrode (SD7) is connected via a twelfth program switch (P12), and the ninth source or drain extraction electrode (SD16) is connected via a sixteenth program switch (P16). SD9) and a tenth source or drain extraction electrode (SD10) via an eighteenth program switch (P18).
And the twenty-second program switch (P2
2) a first output wiring (Lout1) connected to the twelfth source or drain lead electrode (SD12) via
Connected to the first source or drain lead electrode (SD1) through a first program switch (P1), and pulled out of the third source or drain through a fifth program switch (P5). Connected to the electrode (SD3), connected to the fourth source or drain lead-out electrode (SD4) via a seventh program switch (P7), and connected to the sixth program switch (P11) via an eleventh program switch (P11). It is connected to the source or drain lead electrode (SD6), is connected to the seventh source or drain lead electrode (SD7) via the thirteenth program switch (P13), and is connected via the fourteenth program switch (P14). Connected to the extraction electrode (SD8) of the eighth drain or source, and connected to the ninth source or drain via the fifteenth program switch (P15). Connected to the extraction electrode (SD9) of the source and drain via the nineteenth program switch (P19), and connected to the extraction electrode (SD10) of the tenth source or drain via the twentieth program switch (P20). Drain or source extraction electrode (SD11)
And a twelfth source or drain extraction electrode (SD1) via a twelfth program switch (P21).
And 2) a second output wiring (Lout2) connected to (2).

As shown in FIG. 10, the semiconductor integrated circuit device according to claim 14 is the semiconductor integrated circuit device according to claim 13, wherein the first power supply line (VDD) and the third source or A fifth high-potential-side program switch (PD) provided between the drain lead electrode (SD3)
5) a sixth high-potential-side program switch (PD6) provided between the first power supply line (VDD) and the sixth source or drain extraction electrode (SD6); And a fifth low-potential-side program switch (PS5) provided between the power supply line (VSS) and the ninth source or drain extraction electrode (SD9);
SS) and a sixth low potential side program switch (PS6) provided between the twelfth source or drain lead electrode (SD12).

According to a fifteenth aspect of the present invention, as shown in FIG. 11, in the semiconductor integrated circuit device according to the thirteenth aspect, the first source or drain extraction electrode (SD1) is connected to the first source or drain extraction electrode (SD1). A third bias program switch (PB1) provided between the third source or drain lead electrode (SD3), the fourth source or drain lead electrode (SD4), and the sixth source or drain. A second bias program switch (PB2) provided between the second source / drain extraction electrode (SD6) and the ninth source / drain extraction electrode (SD9). ), A third bias program switch (PB3), the tenth source or drain lead electrode (SD10), and the twelfth source or drain. Extraction electrode (SD12)
And a fourth bias program switch (PB4) provided between them.

As shown in FIG. 12, the semiconductor integrated circuit device according to claim 16 is the semiconductor integrated circuit device according to claim 13, wherein the third source or drain extraction electrode (SD3) is connected to the third integrated circuit. And a fifth high-potential-side program switch (P
D5), a sixth high-potential-side program switch (PD6) provided between the sixth source or drain lead electrode (SD6) and the first power supply line (VDD), A fifth low-potential-side program switch (PS5) provided between the source or drain extraction electrode (SD9) of the ninth source and the second power supply line (VSS); A sixth low-potential-side program switch (PS6) provided between the extraction electrode (SD12) and the second power supply line (VSS); and a first source or drain extraction electrode (SD1). A first bias program switch (PB1) provided between the third source or drain lead electrode (SD3), the fourth source or drain lead electrode (SD4) and the sixth source Or drain extraction electrode ( D6) between the second bias program switch (PB2) and the seventh source or drain lead electrode (SD7) and the ninth source or drain lead electrode (SD9). Third bias program switch (PB3)
And the tenth source or drain extraction electrode (S
D10) and a fourth bias program switch (PB4) provided between the twelfth source or drain lead electrode (SD12).

The semiconductor integrated circuit device according to a seventeenth aspect is the semiconductor integrated circuit device according to the thirteenth to sixteenth aspects, wherein the first to fourth transistors (T1 to T
4) comprises a p-type field effect transistor,
The eighth to eighth transistors (T5 to T8) are n-type field effect transistors.

The semiconductor integrated circuit device according to claim 18 is the semiconductor integrated circuit device according to claims 13 to 16, wherein the program switches (PD1 to PD6, PS1 to PS6, P1 to P22, PB1 to PB4) are fuses. And a p-type or n-type field effect transistor.

A semiconductor integrated circuit device according to a nineteenth aspect is characterized in that a logic circuit is formed by combining two or more basic cells comprising the semiconductor integrated circuit devices according to the first to sixth aspects.

A semiconductor integrated circuit device according to a twentieth aspect is characterized in that a logic circuit is formed by combining two or more basic cells composed of the semiconductor integrated circuit devices according to the seventh to twelfth aspects.

A semiconductor integrated circuit device according to a twenty-first aspect is characterized in that a logic circuit is formed by combining two or more basic cells composed of the semiconductor integrated circuit devices according to the thirteenth to sixteenth aspects.

A semiconductor integrated circuit device according to a twenty-second aspect is characterized in that a logic circuit is formed by combining two or more basic cells comprising the semiconductor integrated circuit device according to any one of the nineteenth, twentieth and twenty-first aspects. I do.

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Next, each embodiment of the present invention will be described with reference to the drawings. 13 to 77 are diagrams illustrating a semiconductor integrated circuit device according to an embodiment of the present invention.

(1) Description of First Embodiment FIGS. 13A and 13B are configuration diagrams of a chip plane of an FPGA according to each embodiment of the present invention, and FIGS. FIG. 15 is an explanatory diagram of a basic cell according to the embodiment, and FIG.
(B) has shown the block diagram of the basic cell which concerns on the 1st Example of this invention, respectively.

For example, an FPGA (Field Programmable Gate Array) 100, which is an example of a semiconductor integrated circuit device, has a basic cell (basic cell) region 101,
I / O (input / output circuit element) cell region 102 and wiring region 10
Consists of three. The FPGA can be provided to the user at an early stage, and can be mainly used for developing a new LSI or for prototype of an electronic product. The FPGA is an ASIC that can be programmed arbitrarily by the user.

That is, the basic cells of the FPGA according to the first to eighth embodiments of the present invention are as shown in FIG.
A p-type field effect transistor TPi [i = 1, 2, 11, 12] which is an example of the first and second transistors T1 and T2.
And an n-type field effect transistor Tni [i = 1, 2, 11, 1, 1 as an example of the third and fourth transistors T3, T4.
2], and a source or drain extraction electrode SDi [i = 1 to 6] and a gate G are provided therein.

The basic cells of the FPGA according to the ninth to twelfth embodiments of the present invention are the same as those of the first to fourth transistors T1 to T4.
To T4, a p-type field-effect transistor TPi
[I = 1 to 4] and the fifth to eighth transistors T5 to T5
8, an n-type field effect transistor Tni [i =
1 to 4], on which a source or drain extraction electrode SDi [i = 1 to 12] and a gate G are provided.

FIG. 14B is a plan view showing a wiring region of the first to fourth transistors T1 to T4.
In FIG. 14B, the first to fourth transistors T1 to T1
Each gate G of T4 is a contact hole (bulk-AL1)
106, and is fixedly connected to the input wiring Lin with the first
The second output wiring Lout1 or Lout2 is a through hole (AL1-
AL2) 106 are fixedly connected to the first and second p-type spare wirings, which are examples of the first and second high-potential side spare wirings LP1 and LP2.

Further, the FPGA according to each embodiment of the present invention
The various program points are through holes (AL1-AL
2) The first and second power supply lines VDD and VSS with 105 interposed
(Hereinafter simply referred to as a power line VDD and a ground line GND) and first and second low-potential side spare lines LN1 and LN2.
It is programmed to the second spare wiring for n-type or the like. The details will be described later with reference to FIGS.

FIGS. 15A and 15B are diagrams showing the configuration of a basic cell according to the first embodiment of the present invention. FIG. 15A shows the transistor, its wiring, and various program points. FIG. 15B is a circuit diagram showing a program symbol diagram in which various program points are arranged.

In FIG. 15A, a first basic cell 1 of the present invention comprises first to fourth transistors TP1, TP2, TN1,
TN4 and 18 various program switches PD1, PD2,
PS1, PS2, P1 to P14.

For example, the first to fourth transistors TP1,
Each gate G of TP2, TN1, TN4 is connected to the input line Lin, and the first to fourth transistors TP1, TP2, TN1, TN2
Source or drain extraction electrodes SD1 to SD6
First and second p-type power supply program switches as examples of second high-potential side program switches PD1 and PD2, and n-type as example of first and second low-potential side program switches PS1 and PS2 Grounding program switch and 1st to 14th
Power supply line V through program switches P1 to P14 of
DD, ground line GND, first and second output lines Lout1, Lout
2, the first and second p-type spare wirings LP1 and LP2 or the first and second
The second n-type spare wirings LN1 and LN2 are connected.

That is to say, FIG.
In the program symbol diagram in which the transistor symbol is omitted as shown in (b), the source or drain lead electrode SD1 of the first transistor TP1 is connected to the power supply line VDD via the first p-type power supply program switch PD1. When,
The second output wiring Lout2 with the first program switch P1 interposed, the first output wiring Lout1 with the second program switch P2 interposed, and the first p-type spare wiring L
Connected to P1.

Further, the first and second transistors TP1, Tp
The source or drain extraction electrode SD2 of P2 is connected to the second p
Power supply line V with the power supply program switch PD2 for
DD and the first program switch P3
Is connected to the output wiring Lout1. The source or drain lead electrode SD3 of the second transistor TP2 is connected to the first output line L via a fourth program switch P4.
out1, the second output wiring Lout2 with the fifth program switch P5 interposed, and the sixth program switch P6
Are connected to the first p-type spare wiring LP1.

Further, the source or drain lead electrode SD4 of the third transistor TN1 is connected to the ground line GND with the first n-type ground program switch PS1.
Are connected to the first output wiring Lout1 via the program switch P8, the second output wiring Lout2 via the ninth program switch P9, and the first spare wiring LN1 for n-type. The source or drain lead electrode SD5 of the third and fourth transistors TN1 and TN4 is connected to the ground line GND via a second n-type ground program switch PS2.
And the second output wiring Lout2 via the tenth program switch P10.

The source or drain lead electrode SD6 of the fourth transistor TN4 is connected to the second output line Lout2 with the eleventh program switch P11 interposed therebetween and the first electrode SD6 with the twelfth program switch P12 interposed therebetween. Output wiring L
out1 and a first n-type spare line LN1 via a thirteenth program switch P13, and a first output line Lout1 is connected via a seventh program switch P7 to a second p-type spare line LN1. The second output wiring L is connected to the spare wiring LP2.
out2 is the second through the fourteenth program switch P14
Is connected to the n-type spare wiring LN2.

The various program points are formed by fuse elements, anti-fuse elements, p-type or n-type field-effect transistors, which are programmed (blown or activated or turned on, and turned off (in the case of a transistor)). As a result, an electrically insulated state or a conductive state is achieved. Here, in the program symbol diagram of FIG. 15 (b), for the various program points indicated by white square symbols, the case where an anti-fuse element is used, and when it is selected, it is painted black. . Therefore, the unselected portions are left with white square symbols.

[0117] For various program points,
If a fuse element is used and it is selected, the portion to be cut is represented by an open square symbol, and the black portion is the unselected portion. Also, for various program points, when a p-type or n-type field effect transistor is used, when it is in the OFF state, the portion is represented by a white square symbol, and when it is in the ON state, Will paint it black.

As described above, according to the basic cell according to the first embodiment of the present invention, as shown in FIGS. 15A and 15B, the first to fourth transistors TP1, TP2 and TN1 are formed. , TN2
And a plurality of various program switches PD1, PD2, PS1, PS2, P1 to P14 for connecting between them and between wirings.

Therefore, the four transistors TP1, TP
2, TN1, TN2 and a total of 18 program switches PD
1, PD2, PS1, PS2, and P1 to P14 constitute the basic unit of the minimum unit. For example, in the first basic cell,
First and second p-type power supply program switches PD1, PD
2, the first and second n-type ground program switches PS1,
Fuse element, anti-fuse element, p-type or n-type which constitutes PS2 or the fourth and twelfth program switches P4 and P12
Processing of the field-effect transistor.

As a result, the source or drain extraction electrode SD1 of the first transistor TP1 and the power supply line VDD are connected via the first p-type power supply program switch PD1, and the first and second transistors TP1 and TP2 are connected. The source or drain extraction electrode SD2 and the power supply line VDD are connected via a second p-type power supply program switch PD2.

The source or drain lead electrode SD3 of the second transistor TP2 is connected to the first output wiring Lout1 via the fourth program switch P4, and the source or drain lead of the third transistor TN1 is drawn. The electrode SD4 and the ground line GND are connected via a first n-type ground program switch PS1, and the source or drain lead electrode SD5 of the third and fourth transistors TN1 and TN4 is connected to the second ground line GND. Power supply program switch for p-type PS1
Connected via Further, the fourth transistor TN4
The source or drain lead electrode SD6 is connected to the first output line Lout1 via the twelfth program switch P12.

Thus, an inverter circuit can be constituted by the second transistor TP2 formed of a p-type field effect transistor and the fourth transistor TN4 formed of an n-type field effect transistor. From this,
A total of 18 program switches PD1, PD2, PS1, P
S2, P1 to P14 are appropriately programmed, so that four transistors TP1, TP2, TN1, and TN2 are used.
Inverter circuit, inverter (power type) circuit, transmission gate circuit, 2-input NAND circuit, 2
A basic logic cell such as an input NOR circuit can be formed.

It should be noted that the seventh and fourteenth program switches P
7 and P14, the first output wiring Lout1 and the second output wiring Lout2 can be connected to the vertical basic cells.

(2) Description of the Second Embodiment FIGS. 16A and 16B are diagrams showing the configuration of a basic cell according to the second embodiment of the present invention. The second embodiment differs from the first embodiment in that a third p-type power supply program switch PD3 and a third n-type ground program switch PS3 are connected.

That is, the second basic cell 2 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 18 program switches PD1 to PD
3, PS1 to PS3 and P1 to P14.

In the program symbol diagram of FIG. 16B, the third power program switch PD3 for p-type is
The third n-type ground program switch PS3 is connected between the source or drain lead electrode SD3 of the transistor TP2 and the power supply line VDD, and the source or drain lead electrode SD6 of the fourth transistor TN2 and the ground line GND. Connected between Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell according to the second embodiment of the present invention, as shown in FIG.
To the fourth transistors TP1, TP2, TN1, TN2 and 20 program switches PD1 to PD3, PS1 to PS3, P1 to P14 for connecting between them and between the wirings.
A third p-type power supply program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power supply line VDD, and the source or drain extraction electrode SD6 of the fourth transistor TN2. And a third n-type ground program switch PS3 between the ground line GND and the ground line GND.
Is connected.

Therefore, the four transistors TP1, TP
2, TN1, TN2 and a total of 20 program switches PD
1 to PD3, PS1 to PS3, and P1 to P14 constitute a basic unit of the minimum unit. For example, in the second basic cell,
First and third p-type power supply program switches PD1, PD
3, the first n-type grounding program switch PS1 and the third
The two-input NAND circuit can be configured by performing the program processing of the fuse elements, the anti-fuse elements, and the p-type or n-type field-effect transistors constituting the twelfth program switches P3 and P12.

As a result, the number of program switches is increased by two as compared with the first embodiment.
An inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, and the like can be combined. When the second basic cell 2 is combined, the third p-type power supply program switch P
By applying D3 or the third n-type ground program switch PS3, it is possible to configure a three-input, four-input basic logic circuit.

(3) Description of Third Embodiment FIGS. 17A and 17B are diagrams showing the configuration of a basic cell according to a third embodiment of the present invention, and FIGS. The configuration diagrams of the respective basic logic cells when the cells are programmed are shown. The third embodiment differs from the first and second embodiments in that the first and second bypass program switches PB1 and PB2 are connected.

That is, the third basic cell 3 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 20 various program switches PD1, PD
2, PS1, PS2, P1 to P14 and PB1, PB2.

In the program symbol diagram of FIG. 17B, the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2. The second bypass program switch PB2 is connected to the source or drain extraction electrode SD4, of the third or fourth transistor TN1, TN2.
Connected between SD6. Other configurations are the same as those of the first embodiment, and the description thereof is omitted. Next, a description will be given of the basic cell program processing according to the third embodiment of the present invention.

FIGS. 18A and 18B are configuration diagrams of an inverter circuit when a basic cell according to the third embodiment of the present invention is programmed. In FIG. 18A, the inverter circuit includes first and second p-type power supply program switches P.
D1, PD2, a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting the first n-type ground program switch PS1 and the fourth and twelfth program switches P4, P12 are processed. .

As a result, as shown in FIG. 18B, the transistor TP connected between the power supply line VDD and the ground line GND is connected.
2, TN1 to form an inverter circuit that inverts and amplifies the input signal A and outputs the output signal X from the first output wiring Lout1.

FIGS. 19A and 19B are configuration diagrams of an inverter (power type) circuit when a basic cell according to the third embodiment of the present invention is programmed. In FIG. 19 (a), a power type inverter circuit includes a second p-type power supply program switch PD2, a second n-type ground program switch PS2, and first, fifth, ninth, and eleventh program switches. A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting P1, P5, P9, and P11 are programmed.

As a result, as shown in FIG. 19B, the transistor TP connected between the power supply line VDD and the ground line GND is connected.
1, TN1, TP2, and TN2, an inverter (power type) circuit that inverts and amplifies the input signal A and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 20A and 20B are configuration diagrams of a transmission gate circuit when a basic cell according to the third embodiment of the present invention is programmed. In FIG. 20A, the transmission gate circuit includes first, third, fifth, eighth, tenth, and twelfth program switches P1, P
3, fuse elements constituting P5, P8, P10, P12,
The anti-fuse element and the p-type or n-type field effect transistor are programmed.

As a result, as shown in FIG. 20B, the first output wiring Lout1 extends to the connection terminal T1, the second output wiring Lout2 extends to the connection terminal T2, and the second transistor It is possible to form a transmission gate circuit in which the gate G of TP2 is connected to the control terminal S1, and the gate G of the third transistor TN1 is connected to the control terminal S2.

FIGS. 21 (a) and 21 (b) show two-input NA when a basic cell according to the third embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 21A, the two-input NAND circuit includes a second p-type power supply program switch PD2, a first n-type ground program switch PS1, and second, fourth, and twelfth program switches P2, P4. , P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 12 are programmed.

Thus, as shown in FIG. 21B, the input signals A1 and A2 are composed of first to fourth transistors TP1, TP2, TN1 and TN2, and the output signals X are amplified. 2-input NAN output from the first output wiring Lout1
A D circuit can be configured.

FIGS. 22 (a) and 22 (b) show two-input NO when a basic cell according to the third embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 22 (a), two inputs N
The OR circuit includes a first p-type power supply program switch PD
1, the second n-type grounding program switch PS2 and the fifth,
Fuse elements, anti-fuse elements, and p-type or n-type field-effect transistors constituting the ninth and twelfth program switches P5, P9, P11 are programmed.

Thus, as shown in FIG. 22 (b), the circuit comprises the first to fourth transistors TP1, TP2, TN1, and TN2. The input signals A1 and A2 are logically amplified, and the output signal X is output. Two-input NOR output from the second output wiring Lout2
A circuit can be configured.

As described above, according to the basic cell according to the third embodiment of the present invention, as shown in FIG.
To the fourth transistors TP1, TP2, TN1, TN2 and 20 program switches PD1, PD2, PS1, PS2, P1 to P14 and PB1, P2 for connecting between them and between the wirings.
B2, a first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2,
A second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD6 of the fourth transistors TN1 and TN2.

Therefore, the four transistors TP1, TP
2, TN1, TN2 and a total of 20 program switches PD
1, PD2, PS1, PS2, P1 to P14, PB1, and PB2 constitute the basic unit of the minimum unit. Further, the first bypass program switch PB1 can directly connect the source or drain lead electrodes SD1 and SD3 of the first and second transistors TP1 and TP2 without passing through the first output wiring Lout1. Similarly, by the second bypass program switch PB2, the third and fourth transistors T
Source electrodes or drain electrodes SD4, SD6 of N1 and TN2
It is possible to directly connect between them without passing through the second output wiring Lout2.

As a result, the number of program switches is increased by two compared to the first embodiment. However, three third basic cells are connected to form a four-input AND / OR
When configuring an input AND / OR inverter circuit or the like, the first and second bypass program switches PB1 and PB2 can be used efficiently.

Further, the number of transistors and the number of program points are reduced as much as necessary without depending on the number of transistors as in the conventional example in connection with the circuit configuration of the basic cell. 21 types of basic logic circuits can be configured.

Next, a description will be given of a case where a plurality of basic cells are programmed according to the third embodiment of the present invention. FIGS. 23A and 23B show a three-input NAND circuit when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a circuit. In FIG. 23 (a), a three-input NA
The ND circuit first connects two basic cells 3 according to the third embodiment of the present invention. Here, the power line VDD and the ground line GN
D, the first and second p-type spare wirings LP1, LP2 and the first,
The second n-type spare wirings LN1 and LN2 are connected. Also, 2
In one of the basic cells BC1 and BC2, a program point P6 is interposed between the first p-type spare wiring LP1 and a program point P7 is interposed between the second p-type spare wiring LP2 and the first output wiring Lout1. And a first n-type spare wiring LN1
A program point P13 is interposed therebetween, and a program point P14 is interposed between the second spare line LN2 for n-type and the second output line Lout2.

Next, the first and second p-type power supply program switches PD1, PD2, the first and second p-type
Fuse elements, anti-fuse elements, p-type or n-type power supply program switches PS1, PS2 for the n-type, and the fourth, seventh, and thirteenth program switches P4, P7, P13.
And the second p-type power supply program switch PD2, the second, fourth and twelfth program switches P2 and P2 of the other basic cell BC2.
The fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting P4 and P12 are programmed.

As a result, as shown in FIG. 23B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, and logically amplifies the input signals A1, A2, A3 and outputs the output signal X to the first output wiring. 3-input NAN output from Lout1
A D circuit can be configured.

FIGS. 24 (a) and 24 (b) show a three-input NO when a basic cell according to the third embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 24A, three inputs N
The OR circuit connects two basic cells 3 according to the third embodiment of the present invention.

Further, the first and second p-type power supply program switches PD1, PD2, the first, second
N-type power supply program switches PS1, PS2, fourth, sixth, eleventh, and fourteenth program switches P4, P6, P
11 and P14, the fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor are programmed, and the first and second n-type power supply program switches PS1, PS2,. Fuse elements, anti-fuse elements, and p-type or n-type field-effect transistors that constitute the fifth, ninth, and eleventh program switches P5, P9, and P11 are programmed.

As a result, as shown in FIG. 24B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, and logically amplifies the input signals A1, A2, A3 and outputs the output signal X to the first output wiring. 3-input NAN output from Lout1
A D circuit can be configured.

FIGS. 25 (a) and 25 (b) show a 4-input NA when the basic cell according to the third embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 25A, the four-input NAND circuit first connects two basic cells 3 according to the third embodiment of the present invention.

Next, the second p-type power supply program switch PD2, the first n-type power supply program switch PS1, and the second, fourth, seventh and thirteenth program switches P2 of one of the basic cells BC1. , P4, P7, P13, the fuse element, the antifuse element, and the p-type or n-type field effect transistor are programmed, and the other basic cell B is processed.
C2 second p-type power supply program switch PD2,
Fuse elements, anti-fuse elements, and p-type or n-type field effect transistors constituting the fourth and twelfth program switches P2, P4, P12 are programmed.

As a result, as shown in FIG. 25B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3, A4 are logically amplified, and the output signal X is converted to the first signal. A four-input NAND circuit that outputs from the output wiring Lout1 can be configured.

FIGS. 26 (a) and 26 (b) show four-input NO when a basic cell according to the third embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 26A, four inputs N
The OR circuit connects two basic cells 3 according to the third embodiment of the present invention.

The first p-type power supply program switch PD1, the second n-type power supply program switch PS2, and the sixth, ninth, eleventh, and fourteenth program switches P6 of one of the basic cells BC1. The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting P9, P11, and P14 are programmed and the other basic cell B is processed.
C2 second n-type power supply program switch PS2, fifth
The program processing is performed on the fuse elements, anti-fuse elements, and p-type or n-type field effect transistors that constitute the ninth and eleventh program switches P5, P9, and P11.

As a result, as shown in FIG. 26B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3, A4 are logically amplified, and the output signal X is converted to the second signal. A four-input NAND circuit outputting from the output wiring Lout2 can be configured.

FIGS. 27A and 27B show a three-input AN when a basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 27A, a three-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Also, the first and second p-type power supply program switches PD1, PD2, the first, second
N-type power supply program switches PS1, PS2, the fourth, seventh, eleventh, and fourteenth program switches P4, P7, P
11 and P14, the anti-fuse element or the fuse element is programmed, and the first n-type power supply program switch PS1, first, third, fifth and fifth switches of the other basic cell BC2 are processed.
, The eleventh program switches P1, P3, P5, P11
, A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor.

As a result, as shown in FIG. 27B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are subjected to two-input logical amplification first, and the resultant signal and the input signal B are amplified. Logic amplification and output signal X
From the second output line Lout2.
An R inverter circuit can be configured.

FIGS. 28 (a) and 28 (b) show a 4-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 28A, a four-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

The second p-type power supply program switch PD2, the second, fourth, seventh, ninth, thirteenth, and fourteenth program switches P2, P4, P4 of one of the basic cells BC1.
7, P9, P13, and P14, the fuse element, the antifuse element, and the p-type or n-type field-effect transistor are programmed, and the first p-type power supply program switch PD1, of the other basic cell BC2, 2, the n-type power supply program switch PS2, the third, fifth, and eleventh program switches P3, P5, and the fuse element, antifuse element, and p-type or n-type field-effect transistor constituting the P11. I do.

As a result, as shown in FIG. 28B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3 are first subjected to three-input logic amplification, and the resultant signal and the input signal B are amplified. And outputs the output signal X from the second output line Lout2.
A D / OR inverter circuit can be configured.

FIGS. 29 (a) and 29 (b) show a 4-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 29A, a four-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

The second p-type power supply program switch PD2, the first n-type power supply program switch PS1, and the second, fourth, seventh, ninth, and fourteenth programs of one of the basic cells BC1. Fuse elements, anti-fuse elements, p-type or n-type switches constituting switches P2, P4, P7, P9, P14
And the first n-type power supply program switch PS1, the first, third, fifth, and eleventh program switches P1, P3, P5, and P11 of the other basic cell BC2. , A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor.

As a result, as shown in FIG. 29B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are first subjected to two-input logic amplification, and the two input signals A3, A4 are amplified. A four-input AND / OR inverter circuit that performs input logical amplification, logically amplifies both result signals, and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 30A and 30B show a four-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 30A, a four-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

The second n-type power supply program switch PS2 of the one basic cell BC1, the first, fourth, seventh, ninth, eleventh, and fourteenth program switches P1, P4, P
7, P9, P11, and P14, the fuse element, the antifuse element, and the p-type or n-type field-effect transistor are programmed, and the second p-type power supply program switch PD2 of the other basic cell BC2. 1 for the n-type power supply program switch PS1, the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting the second, fourth, and tenth program switches P2, P4, and P10. I do.

As a result, as shown in FIG. 30B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are first subjected to two-input logical amplification, and the resultant signals and the input signals B1, B2 And outputs the output signal X from the second output wiring Lout2.
An input AND / OR inverter circuit can be configured.

FIGS. 31, 32 (a) and 32 (b) are configuration diagrams of a 6-input AND / OR inverter circuit when a basic cell according to the third embodiment of the present invention is programmed. In FIG. 31, a 6-input AND / OR inverter circuit connects three basic cells 3 according to the third embodiment of the present invention.

For example, the first n-type power supply program switch PS1 of the first basic cell BC1, the first, third, fifth, seventh, eleventh, and fourteenth program switches P1, P3, P
5, P7, P11, P14, the fuse element, the antifuse element, and the p-type or n-type field effect transistor are programmed, and the first n-type power supply program switch PS1, PS2 of the second basic cell BC2 is processed. Fuse element, anti-fuse element, p-type or n-type field effect transistor constituting first bypass program switch PB1, third, sixth, eleventh, and fourteenth program switches P3, P6, P11, P14 Program processing. In addition, the third
, The second p-type power supply program switch PD2, the first n-type power supply program switch PS1, and the second, fourth, and eleventh program switches P2, P4, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 11 are programmed.

As a result, as shown in FIGS. 32A and 32B, the first to fourth transistors TP11 of the basic cell BC1 are formed.
, TP12, TN11, TN12, the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2 and the first to fourth transistors TP31, TP32 of the basic cell BC3.
, TN31, TN32, and the input signals A1, A2
The two-input logical amplification of the input signals B1 and B2, the two-input logical amplification of the input signals C1 and C2, and the three-input logical amplification of the three result signals are performed. And a 6-input AND / OR inverter circuit for outputting the output signal X from the second output wiring Lout2.

FIGS. 33 (a) and 33 (b) show a 4-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 33A, a four-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Also, the first p-type power supply program switch PD1, the second bypass program point PB2, the fourth, seventh, eighth, tenth, thirteenth, and thirteenth of the basic cell BC1.
14 program switches P4, P7, P8, P10, P
13 and P14, the fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor are programmed, and the first p-type power supply program switch PD1, the second n-type of the other basic cell BC2. Power supply program switch PS2, fuse elements forming third, fifth, eighth, and eleventh program switches P3, P5, P8, and P11;
The anti-fuse element and the p-type or n-type field effect transistor are programmed.

As a result, as shown in FIG. 33B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1 and A2 are first subjected to two-input logical amplification, and the resultant signal and the input signal B are amplified. A two-input logic amplifier that performs two-input logic amplification of the result signal and the input signal C, and outputs the output signal X from the second output wiring Lout2
A D / OR inverter circuit can be configured.

(4) Description of Fourth Embodiment FIGS. 34 (a) and (b) are configuration diagrams of a basic cell according to a fourth embodiment of the present invention, and FIGS. The configuration diagrams of the respective basic logic cells when the cells are programmed are shown. The difference from the first to third embodiments is the fourth embodiment.
In the embodiment of the present invention, the third p-type power supply program switch P
D3, the third n-type ground program switch PS3 and the first,
The second bypass program switches PB1 and PB2 are connected.

That is, the fourth basic cell 4 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 20 various program switches PD1 to PD
3, PS1 to PS3, P1 to P14 and PB1, PB2.

In the program symbol diagram of FIG. 34B, the third p-type power supply program switch PD3 is the second
The third n-type ground program switch PS3 is connected between the source or drain lead electrode SD3 of the transistor TP2 and the power supply line VDD, and the source or drain lead electrode SD6 of the fourth transistor TN2 and the ground line GND. Connected between

Further, the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2.
The second bypass program switch PB2 is the third or fourth program switch.
Are connected between the extraction electrodes SD4 and SD6 of the sources or drains of the transistors TN1 and TN2. Other configurations are the same as those of the first embodiment, and the description thereof is omitted. Next, a description will be given of the basic cell program processing according to the fourth embodiment of the present invention.

FIGS. 35A and 35B are configuration diagrams of an inverter circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 35A, as in the third embodiment, the inverter circuit includes first and second p-type power supply program switches PD1 and PD2, a first n-type ground program switch PS1 and a fourth and fourth p-type power supply program switches. The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting the twelfth program switches P4 and P12 are programmed.

As a result, as shown in FIG. 35B, the transistor TP connected between the power supply line VDD and the ground line GND is connected.
2, TN1 to form an inverter circuit that inverts and amplifies the input signal A and outputs the output signal X from the first output wiring Lout1.

FIGS. 36A and 36B are configuration diagrams of an inverter (power type) circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 36 (a), the power type inverter circuit includes a second p-type power supply program switch PD2, as in the third embodiment.
The second n-type ground program switch PS2 and the first, fifth, ninth, and eleventh program switches P1, P5, P
9. Program the fuse element, anti-fuse element, p-type or n-type field effect transistor constituting P11.

As a result, as shown in FIG. 36 (b), the transistor TP connected between the power supply line VDD and the ground line GND is connected.
1, TN1, TP2, and TN2, an inverter (power type) circuit that inverts and amplifies the input signal A and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 37A and 37B are configuration diagrams of a transmission gate circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 37 (a), the transmission gate circuit includes first, third, fifth, eighth, tenth, and twelfth program switches P1, P3, P5, P8, as in the third embodiment. A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting P10 and P12 are programmed.

As a result, as shown in FIG. 37B, the first output wiring Lout1 extends to the connection terminal T1, the second output wiring Lout2 extends to the connection terminal T2, and the second transistor It is possible to form a transmission gate circuit in which the gate G of TP2 is connected to the control terminal S1, and the gate G of the third transistor TN1 is connected to the control terminal S2.

FIGS. 38A and 38B show a two-input NA when the basic cell according to the fourth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 38 (a), the two-input NAND circuit includes first and third p-type power supply program switches PD1 and PD3, a first n-type ground program switch PS1, and a third and twelfth program switch P3. , P12
, A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor.

Thus, as shown in FIG. 38 (b), the input signals A1 and A2 are composed of first to fourth transistors TP1, TP2, TN1 and TN2, and the output signals X are amplified. 2-input NAN output from the first output wiring Lout1
A D circuit can be configured.

FIGS. 39 (a) and 39 (b) show two-input NO when a basic cell according to the fourth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 39 (a), two inputs N
The OR circuit includes a third p-type power supply program switch PD
3, the first and third n-type ground program switches PS1,
PS3 and the first, fifth, and tenth program switches P1,
A program process is performed on fuse elements, anti-fuse elements, and p-type or n-type field-effect transistors constituting P5 and P10.

Thus, as shown in FIG. 39 (b), it comprises first to fourth transistors TP1, TP2, TN1, and TN2, performs logical amplification of the input signals A1 and A2, and outputs the output signal X. Two-input NOR output from the second output wiring Lout2
A circuit can be configured.

As described above, according to the basic cell according to the fourth embodiment of the present invention, as shown in FIG.
A third p-type power supply program switch PD3 is connected between the source or drain extraction electrode SD3 of the transistor TP2 and the power supply line VDD.
N2 source or drain lead electrode SD6 and ground line GND
Is connected to the third n-type ground program switch PS3. Further, the first and second transistors TP1, TP2
A first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3, and the second bypass program switch PB1 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TN1 and TN2. Is connected to the bypass program switch PB2.

Therefore, the four transistors TP1, TP
2, TN1, TN2 and a total of 22 program switches PD
1 to PD3, PS1 to PS3, P1 to P14, PB1, and PB2 constitute a basic unit of the minimum unit. Thereby, the first
Although the number of program switches is increased by four as compared with the embodiment, the inverter circuit, the inverter (power type) circuit, the transmission gate circuit, the two-input NAND circuit, the two-input NOR circuit, and the like can be combined.

Next, a description will be given of a case where a plurality of basic cells are programmed according to the fourth embodiment of the present invention. FIGS. 40A and 40B show a three-input NAND circuit when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a circuit. In FIG. 40 (a), a three-input NA
First, the ND circuit connects two basic cells 4 according to the fourth embodiment of the present invention. Here, the power line VDD and the ground line GN
D, the first and second p-type spare wirings LP1, LP2 and the first,
The second n-type spare wirings LN1 and LN2 are connected. Also, 2
In one of the basic cells BC1 and BC2, a program point P6 is interposed between the first p-type spare wiring LP1 and a program point P7 is interposed between the second p-type spare wiring LP2 and the first output wiring Lout1. And a first n-type spare wiring LN1
A program point P13 is interposed therebetween, and a program point P14 is interposed between the second spare line LN2 for n-type and the second output line Lout2.

Next, the first and second p-type power supply program switches PD1, PD2, the first and second p-type
Fuse elements, anti-fuse elements, p-type or n-type power supply program switches PS1, PS2 for the n-type, and the fourth, seventh, and thirteenth program switches P4, P7, P13.
Elements that program the field-effect transistor of the p-type and configure the first and third p-type power supply program switches PD1 and PD3, and the third and twelfth program switches P3 and P12 of the other basic cell BC2. , Anti-fuse element, p-type or n-type field effect transistor.

Thus, as shown in FIG. 40B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, and logically amplifies the input signals A1, A2, A3 and outputs the output signal X to the first output wiring. 3-input NAN output from Lout1
A D circuit can be configured.

FIGS. 41A and 41B show a three-input NO when a basic cell according to the fourth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 41 (a), three inputs N
The OR circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Further, the first and second p-type power supply program switches PD1, PD2, the first and second p-type
N-type power supply program switches PS1, PS2, fourth, sixth, eleventh, and fourteenth program switches P4, P6, P
11 and P14, the fuse element, the antifuse element, and the p-type or n-type field effect transistor are programmed, and the first and third n-type power supply program switches PS1, PS3, Fuse elements, anti-fuse elements, and p-type or n-type field-effect transistors constituting the fifth and tenth program switches P5 and P10 are programmed.

As a result, as shown in FIG. 41B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, and logically amplifies the input signals A1, A2, A3 and outputs the output signal X to the second output wiring. 3-input NAN output from Lout2
A D circuit can be configured.

FIGS. 42 (a) and (b) show a 4-input NA when a basic cell according to the fourth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 42A, a four-input NAND circuit first connects two basic cells 4 according to the fourth embodiment of the present invention.

Next, the first and third p-type power supply program switches PD1 and PD3, the first n-type power supply program switch PS1, and the third, seventh and thirteenth programs of one of the basic cells BC1. The fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting the switches P3, P7, and P13 are programmed, and the other basic cell B
C1 first and third p-type power supply program switches PD1,
The program processing is performed on the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting the PD3, the third and twelfth program switches P3 and P12.

As a result, as shown in FIG. 42B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3, A4 are logically amplified, and the output signal X is converted to the first signal. A four-input NAND circuit that outputs from the output wiring Lout1 can be configured.

FIGS. 43 (a) and 43 (b) show four-input NO when a basic cell according to the fourth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 43 (a), four inputs N
The OR circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Also, the first p-type power supply program switch PD1, the second and third n-type power supply program switches PS1, PS3, the sixth, tenth, and fourteenth program switches of one of the basic cells BC1. A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting P6, P10, and P14 are programmed, and the other basic cell B is processed.
C2, the first and third n-type power supply program switches PS1,
Ps3, the fifth and tenth program switches P5, P10 The fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting the p-type field effect transistor are programmed.

As a result, as shown in FIG. 43B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3, A4 are logically amplified, and the output signal X is converted to the second signal. A four-input NAND circuit outputting from the output wiring Lout2 can be configured.

FIGS. 44A and 44B show a three-input AN when a basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 44A, a three-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

The first and second p-type power supply program switches PD1 and PD2 of the one basic cell BC1 and the first and second p-type power supply program switches PD1 and PD2.
N-type power supply program switches PS1, PS2, the fourth, seventh, eleventh, and fourteenth program switches P4, P7, P
11, P14, the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor are programmed, and the first n-type power supply program switch PS1, first, third , Fifth, and eleventh program switches P1, P3, P5, and P11. The fuse switch, the antifuse element, and the p-type or n-type field effect transistor are programmed.

As a result, as shown in FIG. 44B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are subjected to two-input logical amplification first, and the resultant signal and the input signal B are amplified. Logic amplification and output signal X
From the second output line Lout2.
An R inverter circuit can be configured.

FIGS. 45 (a) and 45 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 45A, a four-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

The first and third p-type power supply program switches PD1, PD3, the third, seventh, ninth, thirteenth, and fourteenth program switches P3, P3 of one of the basic cells BC1 are also provided.
7, P9, P13, and P14, the fuse element, the antifuse element, and the p-type or n-type field-effect transistor are programmed, and the first p-type power supply program switch PD1, of the other basic cell BC2, The second n-type power supply program switch PS2, the third, fifth, and eleventh program switches P3, P5, and the fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor that constitute the P11 are programmed. I do.

As a result, as shown in FIG. 45B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2, A3 are first subjected to three-input logic amplification, and the resultant signal and the input signal B are amplified. And outputs the output signal X from the second output line Lout2.
A D / OR inverter circuit can be configured.

FIGS. 46 (a) and 46 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 46A, a four-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Further, the first and third p-type power supply program switches PD1 and PD3, the first n-type power supply program switch PS1, and the third, seventh, eleventh and eleventh power supply switches of one of the basic cells BC1.
Fuse elements, anti-fuse elements, p-type or n-type elements constituting each of the fourteen program switches P3, P7, P11, P14.
And the first basic power supply program switch PS1, the first, third, fifth and eleventh program switches P1, P3, P5 and P11 of the other basic cell BC2. , A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor.

As a result, as shown in FIG. 46B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are first subjected to two-input logic amplification, and the two input signals A3, A4 are amplified. A four-input AND / OR inverter circuit that performs input logical amplification, logically amplifies both result signals, and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 47 (a) and 47 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 47A, a four-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Further, the first and third n-type power supply program switches PS1 and PS3, the first, fourth, seventh, tenth and fourteenth program switches P1 and P1 of one of the basic cells BC1 are provided.
4, P7, P10, P14, the fuse element, the antifuse element, and the p-type or n-type field effect transistor are programmed, and the first and third cells of the other basic cell BC2 are processed.
P-type power supply program switches PD1, PD3, third n
A fuse power supply, an anti-fuse element, and a p-type or n-type field effect transistor constituting the power supply program switch PS3 for the mold, the third and tenth program switches P3 and P10 are programmed.

As a result, as shown in FIG. 47B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1, A2 are first subjected to two-input logical amplification, and the resultant signals and the input signals B1, B2 And outputs the output signal X from the second output wiring Lout2.
An input AND / OR inverter circuit can be configured.

FIGS. 48, 49 (a) and (b) are configuration diagrams of a 6-input AND / OR inverter circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 48, a 6-input AND / OR inverter circuit connects three basic cells 4 according to the fourth embodiment of the present invention.

For example, the first n-type power supply program switch PS1, the first, third, fifth, seventh, eleventh, and fourteenth program switches P1, P3, P of the first basic cell BC1.
5, P7, P11, P14, the fuse element, the antifuse element, and the p-type or n-type field effect transistor are programmed, and the first n-type power supply program switch PS1, PS2 of the second basic cell BC2 is processed. Fuse element, anti-fuse element, p-type or n-type field effect transistor constituting first bypass program switch PB1, third, sixth, eleventh, and fourteenth program switches P3, P6, P11, P14 Program processing. In addition, the third
, The second p-type power supply program switch PD2, the first n-type power supply program switch PS1, and the second, fourth, and eleventh program switches P2, P4, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 11 are programmed.

As a result, as shown in FIGS. 49A and 49B, the first to fourth transistors TP11 of the basic cell BC1 are provided.
, TP12, TN11, TN12, the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2 and the first to fourth transistors TP31, TP32 of the basic cell BC3.
, TN31, TN32, and the input signals A1, A2
The two-input logical amplification of the input signals B1 and B2, the two-input logical amplification of the input signals C1 and C2, and the three-input logical amplification of the three result signals are performed. And a 6-input AND / OR inverter circuit for outputting the output signal X from the second output wiring Lout2.

FIGS. 50 (a) and 50 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 50A, a four-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Also, the third p-type power supply program switch PD3, the second n-type power supply program switch PS2, the first, third, seventh, ninth, thirteenth, and thirteenth power supply switches of one of the basic cells BC1.
14 program switches P1, P3, P7, P9, P
13 and P14, the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor are programmed, and the first p-type power supply program switch PD1, the second bypass for the other basic cell BC2. Program point PB2, fourth and tenth program switches P4, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 10 are programmed.

As a result, as shown in FIG. 50B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are formed.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1 and A2 are first subjected to two-input logical amplification, and the resultant signal and the input signal B are amplified. A two-input logic amplifier that performs two-input logic amplification of the result signal and the input signal C, and outputs the output signal X from the second output wiring Lout2
A D / OR inverter circuit can be configured.

FIGS. 51A to 51C show configuration diagrams (part 1) of a logic circuit which can be programmed by a basic cell according to the fourth embodiment of the present invention. FIG. 51A shows a three-input OR / AND inverter circuit.
It is a symmetrical type logic circuit of an OR inverter circuit. FIG. 51B shows a 4-input OR / AND inverter circuit, which is a symmetrical logic circuit of the 4-input AND / OR inverter circuit. Further, FIG. 51 (c) shows a 4-input OR
An AND inverter circuit, which is a symmetrical logic circuit of a 4-input AND / OR inverter circuit. For this reason,
The program processing of each program point of the basic cell can also be easily realized by symmetrically connecting.

FIGS. 52A to 52C show configuration diagrams (part 2) of a logic circuit which can be programmed from a basic cell according to the fourth embodiment of the present invention. FIG. 52 (a) shows a 4-input OR / AND inverter circuit.
It is a symmetrical type logic circuit of an OR inverter circuit. Figure
52 (b) is a 6-input OR / AND inverter circuit,
This is a symmetric logic circuit of a 6-input AND / OR inverter circuit. Further, FIG. 52 (c) shows a 4-input OR-AND
This is an inverter circuit, which is a symmetrical logic circuit of a 4-input AND / OR inverter circuit. Therefore, the program processing of each program point of the basic cell can be easily realized by symmetrically connecting.

Thus, by performing the program processing on the two basic cells according to the fourth embodiment, it is possible to form 21 types of basic logic cells. Further, FIG.
(A) and (b) are explanatory diagrams of a D-type flip-flop circuit combining basic cells according to a fourth embodiment of the present invention. In FIG. 53A, a D-type flip-flop circuit DFF is an application circuit in which 12 basic cells according to the first to eighth embodiments of the present invention are combined.

For example, eight inverter circuits IN1 to IN8 based on the basic cells of the first to third or fourth embodiments, and 4
The transmission gate circuits TG1 to TG4 are connected. Thus, a D-type flip-flop circuit DFF can be configured. Further, the total number of transistors is a total of 48, including 16 transistors forming four transmission gate circuits TG1 to TG4 and 32 transistors forming eight inverter circuits IN1 to IN8.

As a result, a D-type flip-flop circuit can be constituted by about half the number of transistors as compared with the conventional example. It is to be noted that, compared to the basic cell in which the two types of the transistor pair tile portion and the RAM logic tile portion are the minimum units as in the conventional example, the D-type flip-flop is obtained by combining the basic cells according to the first to eighth embodiments. Since it is possible to easily configure the flop, it is possible to improve the use efficiency.

(5) Description of Fifth Embodiment FIG. 54 (a) is a configuration diagram of a basic cell according to a fifth embodiment of the present invention. The fifth embodiment differs from the first to fourth embodiments in that the fifteenth and sixteenth program switches P1
5, P16 is added, and each transistor TP1, TP2, TN
1, TN2 source or drain extraction electrodes SD1 to SD6
To fifth program switches P1 to P connected to
5, the eighth to twelfth program switches P8 to P12 are not directly connected to the first and second output wirings Lout1 and Lout2.

That is, the fifth basic cell 5 is the one shown in FIG.
As shown in the program symbol diagram of FIG. 7, the circuit comprises first to fourth transistors TP1, TP2, TN1, and TN2 and 20 program switches PD1, PD2, PS1, PS2, P1 to P16.

The first to fourth transistors TP1, Tp
The gates G of P2, TN1, and TN2 are connected to the input line Lin,
The source or drain lead electrodes SD1 to SD6 of the transistors TP1, TP2, TN1, TN2 are connected to the first and second p-type power supply program switches PD1, PD2, the first and second n-type ground program switches PS1, The power supply line VDD, the ground line GND, the first and second output wirings Lout1, Lout2, the first and second p-type spare wirings LP1, with the PS2 and the first to sixteenth program switches P1 to P16 interposed therebetween. LP2 or the first and second n-type spare wirings LN1 and LN2.

That is, the source or drain extraction electrode SD1 of the first transistor TP1 is connected to the power supply line VDD via the first p-type power supply program switch PD1 and via the first program switch P1. The second p-type spare wiring LP2, the second p-type spare wiring LP2, and the first p-type spare wiring LP1 are connected via the second program switch P2.

The first and second transistors TP1, Tp
The source or drain extraction electrode SD2 of P2 is connected to the second p
Power supply line V with the power supply program switch PD2 for
DD and the second program switch P3
With the p-type spare wiring LP2. The source or drain lead electrode SD3 of the second transistor TP2 is connected to the second p-type spare line LP2 with the fourth program switch P4 interposed therebetween and the second n-type with the fifth program switch P5 interposed therebetween. The auxiliary wiring LN2 for the mold and the first auxiliary wiring LP1 for the p-type are connected via the sixth program switch P6.

Further, the source or drain lead electrode SD4 of the third transistor TN1 is connected to the ground line GND and the eighth ground program switch via the first n-type ground program switch PS1.
The second spare line LP2 for p-type via the program switch P8, the second spare line LN2 for the n-type, and the first spare line LN1 for the first n-type via the ninth program switch P9. Connected to. Third and fourth transistors TN
1, the lead-out electrode SD5 of the source or drain of TN2 is connected to a ground line GND with a second n-type ground program switch PS2 interposed and a second p-type spare wiring with a tenth program switch P10 interposed. LP2.

The source or drain lead electrode SD6 of the fourth transistor TN2 is connected to the second n-type auxiliary wiring LN2 and the second n-type auxiliary wiring LN2 via the eleventh program switch P11.
It is connected to the second spare line LP2 for p-type via the 12 program switches P12 and to the first spare line LN1 for the n-type via the thirteenth program switch P13.

The second spare line LP2 for p-type is connected to the seventh program switch P7, and the second spare line LN2 for n-type is connected to the fourteenth program switch P14. The second spare line LP2 for p-type is connected to the first output line Lout1 via the fifteenth program switch P15, and the second spare line LN2 for n-type is connected via the sixteenth program switch P16. Then, it is connected to the second output wiring Lout2. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell of the fifth embodiment of the present invention, as shown in FIG.
To fourth transistors TP1, TP2, TN1, TN2 and 20 program switches PD1, PD2, PS1, PS2, P1 to P16 for connecting between them and between wirings,
The second p-type spare wiring LP2 is connected to the first output wiring Lout1 via the fifteenth program switch P15, and the second n-type spare wiring LN2 is connected to the sixteenth program switch Pout.
16 is connected to the second output wiring Lout2.

For this reason, the four transistors TP1, TP
2, TN1, TN2 and a total of 20 program switches PD
1, PD2, PS1, PS2, and P1 to P16 constitute a minimum unit basic cell. By selectively conducting (program processing) the fifteenth and sixteenth program switches P15 and P16, the second p-type spare wiring LP2 is connected to the first output wiring Lout1, and the second output wiring Lout1 is connected. Of the n-type spare wiring LN2 and the second output wiring Lout2.
When the fifteenth and sixteenth program switches P15 and P16 are not selected (non-program processing), the first and second output lines Lout are output.
1 and Lout1 can have a through wiring function.

The through wiring function refers to a wiring that passes through the fifth basic cell 5 in the horizontal direction, and is used when direct connection between the basic cells adjacent in the horizontal direction or when the shortest wiring distance is required. It is valid.

As a result, the number of program switches is increased by two compared to the first embodiment. However, the inverter circuit, the inverter (power type) circuit, the transmission gate circuit, the two-input NA
An ND circuit, a two-input NOR circuit, and the like can be combined. It should be noted that two first basic cells are connected to form a three-input NAN.
A D circuit, a 3-input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, a 4-input AND / OR inverter circuit,
By connecting three fifth basic cells 5, a 6-input AND / OR inverter circuit or the like can be configured.

(6) Description of Sixth Embodiment FIG. 54B is a diagram showing the configuration of a basic cell according to a sixth embodiment of the present invention. The sixth embodiment differs from the fifth embodiment in that the third p-type power supply program switch PD3
And the third n-type ground program switch PS3 is connected to the ground line GND.

That is, the sixth basic cell 6 corresponds to FIG.
As shown in the program symbol diagram of FIG. 7, the circuit comprises first to fourth transistors TP1, TP2, TN1, and TN2 and 20 program switches PD1, PD2, PS1, PS2, P1 to P16.

The third p-type power supply program switch PD3 is connected between the source or drain lead electrode SD3 of the second transistor TP2 and the power supply line VDD, and the third n-type ground program switch PS3 is connected to the power supply line VDD. The fourth transistor TN2 is connected between the source or drain lead electrode SD6 and the ground line GND. The other configuration is the same as that of the fifth embodiment, and a description thereof will be omitted.

As described above, according to the basic cell of the sixth embodiment of the present invention, as shown in FIG.
To fourth transistors TP1, TP2, TN1, TN2 and 22 various program switches PD1, PD2, PS1, PS2, P1 to P16 for connecting between them and between wirings,
The source or drain lead electrode SD3 of the second transistor TP2 is connected to the third p-type power supply program switch PD3.
Is connected to the power supply line VDD with the intermediary of the third transistor TN2.
Is connected to the ground line GND via the n-type ground program switch PS3.

For this reason, the four transistors TP1, TP
2, TN1, TN2 and a total of 22 program switches PD
1 to PD3, PS1 to PS3, and P1 to P16 form the basic unit of the minimum unit. Further, like the fifth basic cell 5, the fifteenth and sixteenth program switches P15 and P16 are not selected (non-program processing), so that the first and second output wirings L15 and P16 are not selected.
out1 and Lout1 can have a through wiring function.

Thus, the number of program switches is increased by four as compared with the first embodiment. However, as in the fifth embodiment, the inverter circuit,
An inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, and the like can be combined. Note that two sixth basic cells are connected to form a three-input NAND circuit, a three-input NOR circuit, a four-input NAND circuit, a four-input NOR circuit, and a four-input AND / O.
By connecting three R inverter circuits and six sixth basic cells 6, a 6-input AND / OR inverter circuit can be formed.

(7) Description of Seventh Embodiment FIG. 55 (a) is a configuration diagram of a basic cell according to a seventh embodiment of the present invention. The difference from the fifth embodiment is that in the seventh embodiment, the first and second bypass program switches PB1 and PB2 are connected.

That is, the seventh basic cell 7 corresponds to FIG.
In the program symbol diagram of FIG. 1, first to fourth transistors TP1, TP2, TN1, TN2 and 22 various program switches PD1, PD2, PS1, PS2, P1 to P16 and PB
1, PB2.

The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2, and the second bypass program switch PB2 is connected to the third bypass program switch PB2. , And the fourth transistor TN1 and TN2 are connected between the source or drain extraction electrodes SD4 and SD6. The other configuration is the same as that of the fifth embodiment, and a description thereof will be omitted.

As described above, according to the basic cell of the seventh embodiment of the present invention, as shown in FIG.
To the fourth transistors TP1, TP2, TN1, TN2 and 22 various program switches PD1, PD2, PS1, PS2, P1 to P16 and PB1, P2 connecting between them and between wirings.
B2 is provided, and the first or second transistor TP1, TP2 is provided between the source or drain lead electrodes SD1, SD3 of the first transistor TP1, TP2.
And the second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD4 of the third and fourth transistors TN1 and TN2.

For this reason, the four transistors TP1, TP
2, TN1, TN2 and a total of 22 program switches PD
1, PD2, PS1, PS2, P1 to P16, PB1, and PB2 constitute a minimum unit basic cell. Further, similarly to the third embodiment, the first bypass program switch PB1
As a result, the source or drain lead electrodes SD1 and SD3 of the first and second transistors TP1 and TP2 can be directly connected without passing through the second p-type spare line LP2, and similarly, the second bypass Program switch PB2
A second n-type spare wiring L is provided between the source or drain lead electrodes SD4 and SD6 of the third and fourth transistors TN1 and TN2.
Direct connection is possible without going through N2.

As a result, the number of program switches is increased by four as compared with the first embodiment. However, as in the fifth embodiment, the inverter circuit,
An inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, and the like can be combined. Note that the seventh basic cell 7 is 2
3 input NAND circuits, 3 input NOR circuits, 4
Input NAND circuit, 4-input NOR circuit, 4-input AND
It becomes possible to configure a 6-input AND / OR inverter circuit by connecting three OR inverter circuits or three seventh basic cells.

(8) Description of Eighth Embodiment FIG. 55 (b) is a configuration diagram of a basic cell according to an eighth embodiment of the present invention. The eighth embodiment differs from the first embodiment in that a third p-type power supply program switch PD3
And a third n-type ground program switch PS3, and the first and second bypass program switches PB1, PB2.

That is, the eighth basic cell 8 corresponds to FIG.
In the program symbol diagram of FIG. 5, first to fourth transistors TP1, TP2, TN1, TN2 and 24 program switches PD1, PD2, PS1, PS2, P1 to P16 and PB
1, PB2.

The third p-type power supply program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power supply line VDD.
Is connected between the source or drain extraction electrode SD6 of the fourth transistor TN2 and the ground line GND.

Further, the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2.
The second bypass program switch PB2 is the third or fourth program switch.
Are connected between the extraction electrodes SD4 and SD6 of the source or drain of the transistors TN1 and TN2. Other configuration is 5th
The description is omitted because it is the same as that of the first embodiment.

As described above, according to the basic cell of the eighth embodiment of the present invention, as shown in FIG.
To a fourth transistor TP1, TP2, TN1, TN2 and 24 program switches PD1, PD2, PS1, PS2, P1 to P14 for connecting between them and between wirings,
A third p-type power supply program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power supply line VDD, and the source or drain extraction electrode SD6 of the fourth transistor TN2. And a third n-type ground program switch PS3 between the ground line GND and the ground line GND.
Is connected. Further, the first and second transistors TP1,
A first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of TP2, and a first bypass program switch PB1 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TN1 and TN2. 2 is connected to the bypass program switch PB2.

For this reason, the four transistors TP1, TP
2, TN1, TN2 and a total of 24 program switches PD
1 to PD3, PS1 to PS3, P1 to P16, PB1, and PB2 constitute a basic unit of the minimum unit. Similarly to the fourth embodiment, for example, of the eighth basic cell 8, the first and third p-type power supply program switches PD1 and PD3, the first n-type ground program switch PS1 and the Third, a two-input NAND circuit is formed by performing program processing on fuse elements, anti-fuse elements, and p-type or n-type field effect transistors constituting the twelfth program switches P3 and P12.
A circuit can be configured.

As a result, the number of program switches is increased by six as compared with the first embodiment. However, as in the fifth embodiment, the inverter circuit,
Inverter (power type) circuits, transmission gate circuits, two-input NAND circuits, two-input NOR circuits, and the like can be combined. Also, two second basic cells are connected to form a three-input NAND circuit, a three-input NOR circuit, a four-input NAND circuit, a four-input NOR circuit, and a four-input AND / O.
R inverter circuit and three third basic cells
An input AND / OR inverter circuit or the like can be configured.

The basic cells according to the first to eighth embodiments of the present invention are suitable for forming a relatively small-scale logic gate circuit, whereas the basic cells according to the ninth to twelfth embodiments will be described below. The basic cell according to the embodiment is suitable for forming a relatively large-scale logic gate circuit.

(9) Description of Ninth Embodiment FIG. 56 is a configuration diagram of a basic cell according to a ninth embodiment of the present invention. The difference from the first to eighth embodiments is that in the ninth embodiment, eight transistors TP1 to TP4 and TN1 to TN4 are used.
Form a basic cell.

That is, the ninth basic cell 9 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 30 various program switches PD1 to PD4, PS1 to P for connecting between them and between wirings.
S4, P1 to P22.

For example, the first to eighth transistors TP1 to TP1
Each gate G of TP4, TN1 to TN4 is connected to the input wiring Lin, and the first to eighth transistors TP1 to TP4, TN1 to TN4
The source or drain extraction electrodes SD1 to SD12 are the first.
To the fourth power program switch PD1 to PD4 for the p-type, the first to fourth ground program switches for the n-type PS1 to PS4, and the first to twentieth program switches P1 to P22. Line GND, first and second output wiring Lou
t1 and Lout2.

That is, the source or drain extraction electrode SD1 of the first transistor TP1 is connected to the power supply line VDD via the first p-type power supply program switch PD1 and via the first program switch P1. The second output wiring Lout2 is connected to the first output wiring Lout1 via the second program switch P2.

Also, the first and second transistors TP1, Tp
The source or drain extraction electrode SD2 of P2 is connected to the second p
Power supply line V with the power supply program switch PD2 for
DD and the first program switch P3
And an output line Lout1 of the second transistor T
The source or drain lead electrode SD3 of P2 is connected to the first output wiring Lou via the fourth program switch P4.
t1 and the second through the fifth program switch P5
Of the third transistor TP3) is connected to the output wiring Lout2 of the third transistor TP3) via the sixth program switch P6.

Further, the source or drain lead electrode SD4 of the third transistor TP3 is connected to the power supply line VDD and the seventh power supply program switch PD3 via the third p-type power supply program switch PD3.
Are connected to the second output wiring Lout2 via the program switch P7 and the first output wiring Lout1 via the eighth program switch P8, and are connected to the source or the source of the third and fourth transistors TP3 and TP4. The drain extraction electrode SD5 is connected to the power supply line VDD and the ninth program switch P9 via the fourth p-type power supply program switch PD4.
Is connected to the first output wiring Lout1.

The source or drain lead electrode SD6 of the fourth transistor TP4 is connected to the first output line Lout1 via the tenth program switch P10 and to the second output terminal Lout1 via the eleventh program switch P11. Output wiring L
connected to out2.

The source or drain lead electrode SD7 of the fifth transistor TN1 is connected to the ground line GND via the first n-type ground program switch PS1 and the ground electrode GND via the thirteenth program switch P12. 1 output wiring L
out1 and a second output wiring Lout2 via a fourteenth program switch P13. The source or drain lead electrode SD8 of the fifth and sixth transistors TN1 and TN2 is connected to the ground line GND via the second n-type ground program switch PS2 and the fourteenth program switch P14.
Is connected to the second output wiring Lout2.

The source or drain lead electrode SD9 of the sixth transistor TN2 is connected to the first output line Lout2 via the fifteenth program switch P15 and to the first electrode via the sixteenth program switch P16. Output wiring L
out1 and a source or drain lead electrode SD10 of the seventh transistor TP3) via the seventeenth program switch P17. The source or drain lead electrode SD10 of the seventh transistor TN3 is connected to the ground line GND via a third n-type ground program switch PS3.
Are connected to the first output wiring Lout1 via the eighteenth program switch P18 and to the second output wiring Lout2 via the nineteenth program switch P19.

Further, the seventh and eighth transistors TN3,
The source or drain extraction electrode SD11 of TN4 is connected to the fourth
Is connected to the ground line GND via the n-type ground program switch PS4 and to the second output wiring Lout2 via the twentieth program switch P20. The source or drain extraction electrode SD12 of the eighth transistor TN4 is
The second output wiring Lout2 is connected via a twenty-first program switch P21, and connected to the first output wiring Lout1 via a twenty-second program switch P22. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell of the ninth embodiment of the present invention, as shown in FIG.
Transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 connecting between them and between wirings
To PD4, PS1 to PS4, and P1 to P22.

For this reason, the eight transistors TP1 to TP
4, TN1 to TN4 and a total of 30 program switches PD
1 to PD4, PS1 to PS4, and P1 to P22 form a minimum unit basic cell. For example, of the ninth basic cell 9, the first, second, and fourth p-type power supply program switches PD1, PD2, PD4, the first and second n-type ground program switches PS1, PS2, and the fourth , Eighth, tenth, seventeenth, and twenty-second program switches P4, P8, P10, P17, P22, fuse elements, anti-fuse elements, p-type or n-type.
Processing of the field-effect transistor.

As a result, the source or drain lead electrode SD1 of the first transistor TP1 and the power supply line VDD are connected via the first p-type power supply program switch PD1, and the first and second transistors TP1 and TP2 are connected. The source or drain extraction electrode SD2 and the power supply line VDD are connected via a second p-type power supply program switch PD2.

The source or drain lead electrode SD3 of the second transistor TP2 is connected to the first output line Lout1 via the fourth program switch P4, and the source or drain lead of the fourth transistor TP4 is drawn. The electrode SD4 and the first output wiring Lout1 are connected via an eighth program switch P8. Further, the source or drain lead electrode SD5 of the third and fourth transistors TP3 and TP4 is connected to the power supply line VDD via the fourth p-type power supply program switch PD4, and the fourth transistor TP4
Is connected to the first output wiring Lout1 via the tenth program switch P10.

Further, the source or drain lead electrode SD7 of the fifth transistor TN1 is connected to the ground line GND via the first n-type ground program switch PS1,
The source or drain lead electrodes SD8 of the fifth and sixth transistors TN1 and TN2 are connected to the ground line GND via a second p-type power supply program switch PS2.

Also, the source or drain lead electrode SD9 of the sixth transistor TN2 and the seventh transistor TN3
Is connected via a seventeenth program switch P17, and the source or drain lead electrode SD12 of the eighth transistor TN4 and the first output wiring Lout1 are connected to the twenty-second program switch P22.
Connected via .

Thus, a three-input NAND circuit is constituted by the first to fourth transistors TP1 to TP4 formed of p-type field effect transistors and the fifth to eighth transistors TN1 to TN4 formed of n-type field effect transistors. It is possible to do. From this, a total of 30 program switches PD1 to PD4, PS1 to PS4, and P1 to P22 are appropriately set.
By performing the program processing, eight transistors T
P1 to TP4, TN1 to TN4, 3-input NAND circuit, 3
Input NOR circuit, 4-input NAND circuit, 4-input NOR circuit, 3-input AND / OR inverter circuit, 4-input AND
-It is possible to configure a basic logic cell such as an OR inverter circuit.

(10) Description of Tenth Embodiment FIG. 57 is a configuration diagram of a basic cell according to the tenth embodiment of the present invention. The difference from the ninth embodiment is that the tenth embodiment differs from the fifth and sixth p-type power supply program switches PD.
5, PD6 and fifth and sixth n-type ground program switches PS5 and PS6 are connected.

That is, the tenth basic cell 10 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 34 program switches PD1 to PD6, PS1 to P for connecting between them and between wirings
S6, P1 to P22.

For example, the fifth p-type power supply program switch PD5 is connected between the source or drain lead electrode SD3 of the second transistor TP2 and the power supply line VDD, and the sixth p-type power supply program switch PD6. Is connected between the source or drain extraction electrode SD6 of the fourth transistor TP4 and the power supply line VDD. The fifth n-type ground program switch PS5 is connected between the source or drain lead electrode SD9 of the sixth transistor TN2 and the ground line GND, and the fifth n-type ground program switch PS6
Is connected between the source or drain extraction electrode SD12 of the eighth transistor TN4 and the ground line GND. Other configurations are the same as those in the ninth embodiment, and a description thereof will be omitted.

As described above, according to the basic cell of the tenth embodiment of the present invention, as shown in FIG.
Transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 connecting between them and between wirings
To PD4, PS1 to PS4, P1 to P22, and the source or drain extraction electrode S of the second transistor TP2.
A fifth p-type power supply program switch PD5 is connected between D3 and the power supply line VDD, and a fourth transistor TP4
A sixth p-type power supply program switch PD6 is connected between the source or drain lead electrode SD6 and the power supply line VDD, and the source or drain lead electrode SD9 of the sixth transistor TN2 is connected to the ground line GND. During the fifth n
The mold ground program switch PS5 is connected, and the source or drain lead electrode SD1 of the eighth transistor TN4 is connected.
A sixth n-type ground program switch PS6 is connected between 2 and the ground line GND.

For this reason, the eight transistors TP1 to TP
4, TN1 to TN4, 34 program switches PD in total
1 to PD6, PS1 to PS6, and P1 to P22 form a minimum unit basic cell. For example, of the tenth basic cell 10, the first, third, fifth, and sixth p-type power supply program switches PD1, PD3, PD5, PD6, the first n-type ground program switch PS1, and the third , Ninth, seventeenth, and twenty-second program switches P3, P9, P17, and P22, by programming the fuse elements, the antifuse elements, and the p-type or n-type field-effect transistors. Can be configured.

As a result, the number of program switches is increased by four as compared with the ninth embodiment, but a total of 34 program switches PD1 to PD4, PS1 to PS4, and P1 to P22 are appropriately programmed. , The three-input NAND circuit, the three-input NOR circuit, the four-input NAND circuit, and the four-input N are provided by eight transistors TP1 to TP4 and TN1 to TN4.
Basic logic cells such as an OR circuit, a 3-input AND / OR inverter circuit, and a 4-input AND / OR inverter circuit can be configured.

(11) Description of Eleventh Embodiment FIG. 58 is a diagram showing the structure of a basic cell according to the eleventh embodiment of the present invention. FIGS. The configuration diagrams of the basic logic cells are shown respectively. The difference from the ninth embodiment is that in the eleventh embodiment, the first
To third bypass program switches PB1 to PB4.

That is, the eleventh basic cell 11 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 34 program switches PD1 to PD4, PS1 to P for connecting between them and wiring.
S4, PB1 to PB4, P1 to P22.

For example, the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2,
The second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TP3 and TP4.

Further, the third bypass program switch PB3 is connected between the source or drain extraction electrodes SD7 and SD9 of the fifth and sixth transistors TN1 and TN2.
The fourth bypass program switch PB4 is connected between the source or drain extraction electrodes SD10 and SD12 of the seventh and eighth transistors TN3 and TN4. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

Thus, according to the basic cell of the eleventh embodiment of the present invention, as shown in FIG.
Transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 connecting between them and between wirings
To PD4, PS1 to PS4, and P1 to P22.
Source or drain lead electrodes SD1, SD3 of the second transistors TP1, TP2 and the third and fourth transistors T
Lead electrodes SD4, SD6 of the source or drain of P3, TP4
The first and second bypass program switches PB1,
PB2 are connected to each other, and the fifth and sixth transistors T
N1 and TN2 source or drain extraction electrodes SD7 and SD9
Third and fourth bypass program switches PB3 and PB4 are connected between the source or drain lead electrodes SD10 and SD12 of the seventh and eighth transistors TN3 and TN4, respectively.

For this reason, the eight transistors TP1 to TP
4, TN1 to TN4, 34 program switches PD in total
1 to PD4, PS1 to PS4, PB1 to PB4, and P1 to P22 form a basic unit of the minimum unit. In addition, the first and second
By means of the bypass program switches PB1 and PB2, the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2 and the source or drain extraction electrodes SD4 and SD4 of the third and fourth transistors TP1 and TP2 are used.
SD6 can be directly connected without the first output wiring Lout1.

Similarly, the third and fourth bypass program switches PB3 and PB4 control the source or drain lead electrodes SD7 and SD7 of the fifth and sixth transistors TN1 and TN2.
It is possible to directly connect between SD9 and between the source or drain extraction electrodes SD10 and SD12 of the seventh and eighth transistors TN3 and TN4 without passing through the second output wiring Lout2.

As a result, the number of program switches is increased by four as compared with the ninth embodiment, but a total of 34 program switches PD1 to PD4, PS1 to PS4, and P1 to P22 are appropriately programmed. As shown in FIGS. 59 to 67, a three-input NAND circuit, a three-input NOR circuit, a four-input NAND circuit, a four-input NOR circuit, and a three-input AND / OR are constituted by eight transistors TP1 to TP4 and TN1 to TN4.
Basic logic cells such as an inverter circuit and a 4-input AND / OR inverter circuit can be configured.

Next, the basic cell program processing according to the eleventh embodiment of the present invention will be described. Figure 59
(A), (b) is a configuration diagram of a three-input NAND circuit when the basic cell according to the eleventh embodiment of the present invention is programmed. In FIG. 59 (a), a three-input NAND circuit
First, second, and fourth p-type power supply program switches PD
1, PD2, PD4, first and second n-type power supply program switches PS1, PS2, fourth, eighth, tenth, seventeenth, and twenty-second program switches P4, P8, P10, P17, P22 Constituent fuse element, anti-fuse element, p-type or n
Processing of the field-effect transistor.

Thus, as shown in FIG. 59 (b), the input signals A1, A2, A4 are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Thus, a three-input NAND circuit that amplifies the logic signal 3 and outputs the output signal X from the first output wiring Lout1 can be configured.

FIGS. 60A and 60B show a three-input NO when a basic cell according to the eleventh embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 60 (a), three inputs N
The OR circuit comprises first and second p-type power supply program switches PD1, PD2, first, second, and fourth n-type power supply program switches PS1, PS2, PS4, fourth, sixth, eleventh, First
Fifth, nineteenth and twenty-first program switches P4, P6, P1
1, a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting P15, P19 and P21 are programmed.

Thus, as shown in FIG. 60 (b), the input signals A1, A2, A4 are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Thus, a three-input NAND circuit that amplifies the logic value of 3 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 61A and 61B show a four-input NA when the basic cell according to the eleventh embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 61 (a), the four-input NAND circuit includes second and fourth p-type power supply program switches PD2 and PD4, a first n-type power supply program switch PS1, second, fourth, eighth and eighth power supply program switches. A fuse process, an anti-fuse device, and a p-type or n-type field effect transistor constituting each of the tenth, seventeenth, and twenty-second program switches P2, P4, P8, P10, P17, P22 are programmed.

Thus, as shown in FIG. 61 (b), the input signals A1, A2, and A4 comprise the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
3, a four-input NAND circuit that amplifies the logic of A4 and outputs the output signal X from the first output wiring Lout1 can be configured.

FIGS. 62 (a) and 62 (b) show four-input NO when a basic cell according to the eleventh embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 62 (a), four inputs N
The OR circuit includes a first p-type power supply program switch PD
1, second and fourth n-type power supply program switches PS2,
PS4, a fuse element, an anti-fuse element, a p-type or n-type element constituting each of the sixth, eleventh, thirteenth, fifteenth, nineteenth, and twenty-first program switches P6, P11, P13, P15, P19, and P21.
Processing of the field-effect transistor.

Thus, as shown in FIG. 62 (b), the input signals A1, A2 and A are composed of first to fourth transistors TP1 to TP4 and fifth to eighth transistors TN1 to TN4.
3, a four-input NAND circuit that amplifies the logic of A4 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 63 (a) and (b) show a three-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 63 (a), the three-input AND / OR inverter circuit includes
The second p-type power supply program switches PD1, PD2, the first, second, and third n-type power supply program switches PS1,
PS2, PS3, 4th, 7th, 9th, 11th, 15th, 21st program switches P4, P7, P9, P11, P15, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 21 are programmed.

As a result, as shown in FIG. 63 (b), it is composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4. Logic amplification is performed, and the result signal and the input signal B are logically amplified, and the output signal X is supplied to the second output wiring Lou.
A three-input AND / OR inverter circuit output from t2 can be configured.

FIGS. 64A and 64B show a four-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 64 (a), the four-input AND / OR inverter circuit
Third p-type power supply program switch PD2, PD3, fourth
N-type power supply program switch PS4, the second, fourth, ninth, eleventh, thirteenth, seventeenth, and twenty-first program switches P
2, P4, P9, P11, P13, P17, and P21 are programmed to program fuse elements, antifuse elements, and p-type or n-type field effect transistors.

Thus, as shown in FIG. 64 (b), the input signals A1, A2 and A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
3 is firstly subjected to three-input logical amplification, the logical amplification of the result signal and the input signal B is performed, and the output signal X is output from the second output wiring Lout2 to form a four-input AND / OR inverter circuit. be able to.

FIGS. 65 (a) and (b) show a 4-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 65 (a), a four-input AND / OR inverter circuit includes a second p-type power supply program switch PD2, a first first n-type power supply program switch PS1, PS1, a second, fourth, and fourth power supply program switches. Seventh, ninth, eleventh, fifteenth, and twenty-first program switches P
2, P4, P7, P9, P11, P15, and P21 are programmed to program fuse elements, antifuse elements, and p-type or n-type field-effect transistors.

As a result, as shown in FIG. 65 (b), it is composed of first to fourth transistors TP1 to TP4 and fifth to eighth transistors TN1 to TN4.
Is subjected to two-input logical amplification, and two-input logical amplification of the input signals A3 and A4, and the logical amplification of the result signals of both is performed,
4 to output the output signal X from the second output wiring Lout2
An input AND / OR inverter circuit can be configured.

FIGS. 66 (a) and 66 (b) show a 4-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 66 (a), a four-input AND / OR inverter circuit includes a fourth p-type power supply program switch PD4, second and third n-type power supply program switches PS2, PS3, first, fourth, and fourth power supply program switches. Eighth, tenth, thirteenth, fifteenth, and twentieth program switches P
1, P4, P8, P10, P13, P15, and P20 are programmed to program fuse elements, antifuse elements, and p-type or n-type field effect transistors.

Thus, as shown in FIG. 66 (b), it is composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Is subjected to two-input logic amplification, and the resultant signal and the input signal B1,
A four-input AND-OR inverter circuit that performs three-input logic amplification with B2 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 67 (a) and (b) show a four-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 67A, the four-input AND / OR inverter circuit includes
Third p-type power supply program switches PD1, PD3, fourth
N-type power supply program switch PS4, third bypass program point PB3, fourth, ninth, eleventh, twelfth,
Fourteenth, seventeenth, eighteenth, and twenty-first program switches P4
A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting P9, P11, P12, P14, P17, P18, and P21 are programmed.

Thus, as shown in FIG. 67 (b), it is composed of first to fourth transistors TP1 to TP4 and fifth to eighth transistors TN1 to TN4.
Is subjected to two-input logical amplification, the resulting signal and the input signal B are subjected to two-input logical amplification, and the resulting signal and the input signal C are subjected to two-input logical amplification, and the output signal X is output to the second output. A four-input AND / OR inverter circuit that outputs from the wiring Lout2 can be configured.

(12) Description of Twelfth Embodiment FIG. 68 is a diagram showing the configuration of a basic cell according to a twelfth embodiment of the present invention. FIGS. The configuration diagrams of the basic logic cells are shown respectively. The difference from the ninth embodiment is that the twelfth embodiment differs from the ninth embodiment in that the fifth and sixth p-type power supply program switches PD5 and PD6 and the fifth and sixth n-type ground program switches PS5 and PS6.
Are connected, and the first to fourth bypass program switches PB1 to PB4 are respectively connected.

That is, the twelfth basic cell 12 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 38 various program switches PD1 to PD6, PS1 to P
S6, PB1 to PB4, and P1 to P22.

For example, the fifth p-type power supply program switch PD5 is connected between the source or drain lead electrode SD3 of the second transistor TP2 and the power supply line VDD, and the sixth p-type power supply program switch PD6. Is connected between the source or drain extraction electrode SD6 of the fourth transistor TP4 and the power supply line VDD.

The fifth n-type ground program switch PS5 is connected between the source or drain lead electrode SD9 of the sixth transistor TN2 and the ground line GND.
Is connected between the source or drain extraction electrode SD12 of the eighth transistor TN4 and the ground line GND. Further, the first bypass program switch PB1 is connected to the source or drain extraction electrodes SD1, S2 of the first and second transistors TP1, TP2.
The second bypass program switch PB2 is connected between the source and drain extraction electrodes SD4 and SD6 of the third and fourth transistors TP3 and TP4.

Further, the third bypass program switch PB3 is connected between the source or drain extraction electrodes SD7 and SD9 of the fifth and sixth transistors TN1 and TN2.
The fourth bypass program switch PB4 is connected between the source or drain extraction electrodes SD10 and SD12 of the seventh and eighth transistors TN3 and TN4. Other configurations are the same as those in the ninth embodiment, and a description thereof will be omitted.

Thus, according to the basic cell of the twelfth embodiment of the present invention, as shown in FIG.
Transistors TP1 to TP4, TN1 to TN4 and 38 various program switches P connecting between them and between wirings
D1 to PD4, PS1 to PS4, P1 to P22, and the second
A fifth p-type power supply program switch PD5 is connected between the source or drain lead-out electrode SD3 of the transistor TP2 and the power supply line VDD.
P4 source or drain lead electrode SD6 and power supply line VDD
And a sixth n-type ground program switch PD6 between the ground or ground line GND and the source or drain lead electrode SD9 of the sixth transistor TN2. PS5 is connected to the source or drain extraction electrode S of the eighth transistor TN4.
A sixth n-type ground program switch PS6 is connected between D12 and the ground line GND.

Further, the first and second transistors TP1, Tp
First and second bypass program switches PB1 and PB2 are connected between the source or drain lead electrodes SD1 and SD3 of P2 and the source or drain lead electrodes SD4 and SD6 of the third and fourth transistors TP3 and TP4, respectively. The source or drain extraction electrodes SD7 and SD9 of the fifth and sixth transistors TN1 and TN2 and the source or drain extraction electrodes SD10 of the seventh and eighth transistors TN3 and TN4.
, SD12 are connected to third and fourth bypass program switches PB3, PB4, respectively.

For this reason, the eight transistors TP1 to TP
4, TN1 to TN4, 38 program switches PD in total
1 to PD6, PS1 to PS6, P1 to P22, and PB1 to PB4 form a minimum unit basic cell. For example, of the twelfth basic cells, the third p-type power supply program switch PD
3, the second n-type ground program switch PS2 or the first
Third, tenth, thirteenth, and eighteenth program switches P1, P
3, P10, P13, P18, the first and fourth bypass program switches PB1, PB4, the fuse element, the antifuse element, and the p-type or n-type field-effect transistor are programmed to obtain four inputs. AND ・ O
An R inverter circuit can be configured.

As a result, the number of program switches is increased by eight as compared with the ninth embodiment, but a total of 38 program switches PD1 to PD4, PS1 to PS4, and P1 to P22 are appropriately programmed. As shown in FIGS. 69 to 77, the eight transistors TP1 to TP4, TN1 to TN4
, Three-input NOR circuit, three-input NOR circuit, four-input NOR circuit, three-input AND
Basic logic cells such as an R inverter circuit and a 4-input AND / OR inverter circuit can be configured.

Next, a description will be given of the basic cell program processing according to the twelfth embodiment of the present invention. Fig. 69
(A), (b) is a configuration diagram of a three-input NAND circuit when the basic cell according to the twelfth embodiment of the present invention is programmed. In FIG. 69 (a), the three-input NAND circuit
First to third and sixth p-type power supply program switches PD1
, PD3, PD6, first and second n-type power supply program switches PS1, PS2, fourth, ninth, seventeenth, and twenty-second program switches P4, P9, P17, fuse elements constituting P17, P22; A fuse element and a p-type or n-type field effect transistor are programmed.

Thus, as shown in FIG. 69 (b), the input signals A1, A2, and A4 comprise the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Thus, a three-input NAND circuit that amplifies the logic signal 3 and outputs the output signal X from the first output wiring Lout1 can be configured.

FIGS. 70A and 70B show a three-input NO when a basic cell according to the twelfth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 70 (a), three inputs N
The OR circuit includes first and second p-type power supply program switches PD1 and PD2, first to third and sixth n-type power supply program switches PS1 to PS3, PS6, fourth, sixth, eleventh, and so on. First
Fifth, twentieth program switches P4, P6, P11, P1
5. Program processing of the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting P20.

As a result, as shown in FIG. 70 (b), the input signals A1, A2 and A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Thus, a three-input NAND circuit that amplifies the logic value of 3 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 71 (a) and (b) show a four-input NA when a basic cell according to the twelfth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an ND circuit. In FIG. 71A, the four-input NAND circuit includes first, third, fifth, and sixth p-type power supply program switches PD1, PD3, PD5, PD6, and a first n.
Power supply program switch for mold PS1, third, ninth, seventeenth,
The program processing is performed on the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor constituting each of the 22nd program switches P3, P9, P17 and P22.

As a result, as shown in FIG. 71 (b), the input signals A1, A2, and A4 comprise the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
3, a four-input NAND circuit that amplifies the logic of A4 and outputs the output signal X from the first output wiring Lout1 can be configured.

FIGS. 72 (a) and 72 (b) show four-input NO when a basic cell according to the twelfth embodiment of the present invention is programmed.
FIG. 3 is a configuration diagram of an R circuit. In FIG. 72 (a), four inputs N
The OR circuit includes a first p-type power supply program switch PD
1, 1st, 3rd, 5th, 6th n-type power supply program switches PS1, PS3, PS5, PS6, sixth, eleventh, fourteenth,
Fuse element, anti-fuse element, p-type or n-type constituting each of the 20 program switches P6, P11, P14 and P20.
Processing of the field-effect transistor.

Thus, as shown in FIG. 72 (b), the input signals A1, A2, and A4 comprise the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
3, a four-input NAND circuit that amplifies the logic of A4 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 73 (a) and 73 (b) show a three-input AN when the basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 73 (a), the three-input AND / OR inverter circuit includes
Second p-type power supply program switches PD1, PD2, first
Fuses constituting the third to third n-type power supply program switches PS1 to PS3, the fourth, seventh, ninth, eleventh, fifteenth, and twenty-first program switches P4, P7, P11, P14, P15, and P21. The element, the anti-fuse element, and the p-type or n-type field effect transistor are programmed.

As a result, as shown in FIG. 73 (b), it is composed of first to fourth transistors TP1 to TP4 and fifth to eighth transistors TN1 to TN4. Logic amplification is performed, and the result signal and the input signal B are logically amplified, and the output signal X is supplied to the second output wiring Lou.
A three-input AND / OR inverter circuit output from t2 can be configured.

FIGS. 74 (a) and 74 (b) show a 4-input AN when a basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 74 (a), the four-input AND / OR inverter circuit comprises
Third and fifth p-type power supply program switches PD1, PD
3, PD5, fourth n-type power supply program switch PS4,
Fuse element, anti-fuse element, p-type or n-type field effect constituting each of the third, ninth, eleventh, thirteenth, seventeenth, and twenty-first program switches P3, P9, P11, P13, P17, and P21. Performs transistor program processing.

As a result, as shown in FIG. 74 (b), the input signals A1, A2, and A4 comprise the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
3 is firstly subjected to three-input logical amplification, the logical amplification of the result signal and the input signal B is performed, and the output signal X is output from the second output wiring Lout2 to form a four-input AND / OR inverter circuit. be able to.

FIGS. 75 (a) and (b) show a four-input AN when a basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 75 (a), the four-input AND / OR inverter circuit includes
Fifth p-type power supply program switches PD1, PD5, first and third n-type power supply program switches PS1, PS3,
Fuse element, anti-fuse element, p-type or n-type field effect constituting each of the third, seventh, ninth, eleventh, fifteenth, and twenty-first program switches P3, P7, P9, P11, P15, and P21. Performs transistor program processing.

As a result, as shown in FIG. 75 (b), it is composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
Is subjected to two-input logical amplification, and two-input logical amplification of the input signals A3 and A4, and the logical amplification of the result signals of both is performed,
4 to output the output signal X from the second output wiring Lout2
An input AND / OR inverter circuit can be configured.

FIGS. 76 (a) and (b) show a 4-input AN when the basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 76 (a), the 4-input AND / OR inverter circuit has a third
Sixth n-type power supply program switches PS3, PS6, first, fifth, and sixth n-type power supply program switches PS1,
Fuse elements, anti-fuse elements, p-type or n-type field effect transistors constituting each of the program switches P1, P4, P9, P14, P20; Program processing.

As a result, as shown in FIG. 76 (b), it is composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4, and the input signals A1, A2
Is subjected to two-input logic amplification, and the resultant signal and the input signal B1,
A four-input AND-OR inverter circuit that performs three-input logic amplification with B2 and outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 77 (a) and (b) show a 4-input AN when the basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D-OR inverter circuit. In FIG. 77 (a), the 4-input AND / OR inverter circuit has a third
Fifth p-type power supply program switch PD3, PD5, second
N-type power supply program switch PS2, fourth bypass program point PB4, first, third, tenth, thirteenth,
Seventeenth and twentieth program switches P1, P3, P10,
A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor constituting P13, P17, and P20 are programmed.

As a result, as shown in FIG. 77 (b), it is composed of first to fourth transistors TP1 to TP4 and fifth to eighth transistors TN1 to TN4.
Is subjected to two-input logical amplification, the resulting signal and the input signal B are subjected to two-input logical amplification, and the resulting signal and the input signal C are subjected to two-input logical amplification, and the output signal X is output to the second output. A four-input AND / OR inverter circuit that outputs from the wiring Lout2 can be configured.

As described above, by connecting two or more basic cells according to the first to twelfth embodiments of the present invention, or by combining the basic logic cells to form various logic circuits, high performance, An FPGA capable of programming a high-performance semiconductor integrated circuit can be provided.

Table 1 shows the number of program switches and the minimum unit (BC number) of the basic cells according to the first to twelfth embodiments.

[0338]

[Table 1]

The minimum unit (the number of BCs) is based on four transistors, and the number of program switches is converted per basic cell (BC).

According to this, in the combination of the basic cells of the first embodiment, the number of program switches is set to 1 which is the smallest.
There can be eight. In addition, a three-input AND / OR inverter circuit, a four-input AND / OR inverter circuit,
Input OR / AND inverter circuit, 6 input AND / OR
Although it is not possible to form an inverter circuit, it is possible to form other 16 basic logic cells.

In the combination of the basic cells of the second embodiment, a 4-input AND / OR inverter circuit and a 4-input O
Although an R / AND inverter circuit and a 6-input AND / OR inverter circuit cannot be assembled, other 18 types of basic logic cells can be assembled.

Further, in the fifth to eighth embodiments, the first and second output wirings Lout1 and Lout2 can be used as through wirings. In the ninth to twelfth embodiments, the minimum unit is two basic cells. Is set as one set, the number of program switches can be reduced to 15.

[0343]

As described above, according to the first semiconductor integrated circuit device of the present invention, the first and second transistors comprising p-type field effect transistors and the first and second transistors comprising n-type field effect transistors are used. Third, a fourth transistor and a plurality of various program switches for connecting between them and between wirings are provided.

Therefore, four transistors and a total of 18
The minimum number of basic cells is constituted by the program switches. Further, by performing program processing on a plurality of various program switches of the basic cell, an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input N
A basic logic cell such as an OR circuit can be configured.

Further, according to the second semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the third high / low potential side program switch is provided. .

Therefore, four transistors and a total of 20
The minimum number of basic cells is constituted by the program switches. Further, by combining the basic cells, a four-input AND / OR inverter circuit or the like can be formed.

Further, according to the third semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and a plurality of various program switches for connecting between them and between wirings, A second bypass program switch.

For this reason, four transistors and a total of 20
The minimum number of basic cells is constituted by the program switches. Although the number of program switches increases by two as compared with the first semiconductor integrated circuit device, two or three basic cells are connected, and four or four program switches are used by using the first and second bypass program switches. It is possible to efficiently configure an input AND / OR inverter circuit, a 6-input AND / OR inverter circuit, and the like.

According to the fourth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the third high / low potential side program switch and the first and third transistors are provided. 2 bypass program switches.

Therefore, four transistors and a total of 22
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, two or three of the basic cells are connected and the third high level is connected similarly to the third semiconductor integrated circuit device. Using a low potential side program switch and first and second bypass program switches
Input AND / OR inverter circuit and 6 input AND / OR
It is possible to efficiently configure an inverter circuit and the like.

Furthermore, according to the fifth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the high-potential-side spare wiring and the first output wiring are connected. A fifteenth program switch for connecting the fifteenth program switch and the low-potential-side spare wiring to the second output wiring is provided.

Therefore, four transistors and a total of 20
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by two compared to the first semiconductor integrated circuit device, the through processing of the fifteenth and sixteenth program switches allows the first and second output wirings to have a through wiring function. Can be provided. It is possible to configure basic logic cells such as an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, and the like.

According to the sixth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches and the third high / low potential are provided. And a side program switch.

Therefore, four transistors and a total of 22
The minimum number of basic cells is constituted by the program switches. Although the number of program switches increases by four as compared with the first semiconductor integrated circuit device, the first and second program switches are deselected by the non-selection processing of the fifteenth and sixteenth program switches as in the fifth semiconductor integrated circuit device. 2 can have a through wiring function.

According to the seventh semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches and the first and second bypasses are provided. Program switch.

For this reason, four transistors and a total of 22
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, similar to the fifth semiconductor integrated circuit device, the first and second bypass programs are applied while applying the through wiring function. Various basic cells can be configured by applying switches.

According to the eighth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches,
A third high / low potential side program switch,
Is provided.

For this reason, four transistors and a total of 24
The minimum number of basic cells is constituted by the program switches. Although the number of program switches increases by four as compared with the first semiconductor integrated circuit device, like the fifth semiconductor integrated circuit device, the high / low potential side program switches and Various basic logic cells can be configured by applying the first and second bypass program switches.

Further, according to the ninth semiconductor integrated circuit device of the present invention, the first semiconductor integrated circuit device comprises a p-type field effect transistor.
There are provided fifth to eighth transistors including a fourth transistor and a fourth transistor and an n-type field effect transistor, and a plurality of various program switches for connecting between them and between wirings.

For this reason, eight transistors and a total of 30
The minimum number of basic cells is constituted by the program switches. Incidentally, by appropriately performing a program processing on a total of 30 various program switches of the basic cell, a 3-input NAND circuit,
3-input NOR circuit, 4-input NAND circuit, 4-input NOR
Circuit, 3-input AND / OR inverter circuit, 4-input AN
Basic logic cells such as D / OR inverter circuits can be efficiently configured.

According to the tenth semiconductor integrated circuit device of the present invention, in addition to the first to eighth transistors and various program switches, the fifth and sixth high / low potential side program switches are provided. Provided.

Therefore, eight transistors and a total of 34
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by four as compared with the ninth semiconductor integrated circuit device, various basic logic cells are constituted by eight transistors by appropriately performing program processing on a total of 34 program switches. It is possible to do.

Further, according to the eleventh semiconductor integrated circuit device of the present invention, in addition to the first to eighth transistors and various program switches, there are provided first to fourth bypass program switches.

For this reason, eight transistors and a total of 34
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by four as compared with the ninth semiconductor integrated circuit device, a basic logic cell is constituted by eight transistors by appropriately performing a program processing on a total of 34 program switches. Becomes possible.

In the twelfth semiconductor integrated circuit device of the present invention, in addition to the first to eighth transistors and various program switches, fifth and sixth high / low potential side program switches and first to fourth program switches are provided. And a bypass program switch.

For this reason, eight transistors and a total of 38
The minimum number of basic cells is constituted by the program switches. Although the number of program switches is increased by eight as compared with the ninth semiconductor integrated circuit device, various basic logic cells are constituted by eight transistors by appropriately performing program processing on a total of 38 program switches. It is possible to do.

Incidentally, two or more basic cells comprising the first to eighth semiconductor integrated circuit devices of the present invention are connected, or various logic circuits are formed by combining the basic cells. For this reason, by combining the basic logic cells according to the first to eighth semiconductor integrated circuit devices, a D-type flip-flop circuit can be configured with a smaller number of transistors than in the conventional example. It should be noted that a D-type flip-flop is different from a basic cell in which two types of a transistor pair tile portion and a RAM logic tile portion are the minimum units as in the conventional example.
The flop can be easily configured.

In addition, two or more basic cells comprising the ninth to twelfth semiconductor integrated circuit devices of the present invention are connected, or various logic circuits are formed by combining the basic cells. Therefore, by combining the basic logic cells according to the ninth to twelfth semiconductor integrated circuit devices, it is possible to easily configure a multi-input AND / OR inverter circuit or the like.

This greatly contributes to the provision of an FPGA that can program a high-performance and high-performance semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a principle diagram (part 1) of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a principle diagram (part 2) of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a principle diagram (part 3) of the semiconductor integrated circuit device according to the present invention;

FIG. 4 is a diagram (part 4) illustrating the principle of a semiconductor integrated circuit device according to the present invention;

FIG. 5 is a principle diagram (part 5) of the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a principle diagram (part 6) of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a principle view (No. 7) of the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a principle view (No. 8) of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a principle diagram (No. 9) of the semiconductor integrated circuit device according to the present invention.

FIG. 10 is a principle view (No. 10) of the semiconductor integrated circuit device according to the present invention.

FIG. 11 is a principle view (No. 11) of the semiconductor integrated circuit device according to the present invention.

FIG. 12 is a principle diagram (part 12) of the semiconductor integrated circuit device according to the present invention.

FIG. 13 is a configuration diagram of a chip plane of an FPGA according to each embodiment of the present invention.

FIG. 14 is an explanatory diagram of a basic cell according to each embodiment of the present invention.

FIG. 15 is a configuration diagram of a basic cell according to the first example of the present invention.

FIG. 16 is a configuration diagram of a basic cell according to a second example of the present invention.

FIG. 17 is a configuration diagram of a basic cell according to a third example of the present invention.

FIG. 18 is a configuration diagram of an inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 19 is a configuration diagram of an inverter (power type) circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 20 is a configuration diagram of a transmission gate circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 21 is a configuration diagram of a two-input NAND circuit in which a basic cell is programmed according to a third example of the present invention.

FIG. 22 is a configuration diagram of a two-input NOR circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 23 is a configuration diagram of a three-input NAND circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 24 is a configuration diagram of a 3-input NOR circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 25 is a configuration diagram of a 4-input NAND circuit in which a basic cell is programmed according to a third example of the present invention.

FIG. 26 is a configuration diagram of a four-input NOR circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 27 is a configuration diagram of a 3-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 28 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 29 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 30 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 31 is a configuration diagram of a 6-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 32 is a supplementary diagram of a 6-input AND / OR inverter circuit in which a basic cell is programmed according to the third embodiment of the present invention.

FIG. 33 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 34 is a configuration diagram of a basic cell according to a fourth embodiment of the present invention.

FIG. 35 is a configuration diagram of an inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 36 is a configuration diagram of an inverter (power type) circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 37 is a configuration diagram of a transmission gate circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 38 is a configuration diagram of a two-input NAND circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 39 is a configuration diagram of a two-input NOR circuit according to a fourth embodiment of the present invention, in which a basic cell is programmed.

FIG. 40 is a configuration diagram of a three-input NAND circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 41 is a configuration diagram of a three-input NOR circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 42 is a configuration diagram of a 4-input NAND circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 43 is a configuration diagram of a 4-input NOR circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 44 is a configuration diagram of a three-input AND / OR inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 45 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 46 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 47 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 48 is a configuration diagram of a 6-input AND / OR inverter circuit in which basic cells are programmed according to a fourth embodiment of the present invention.

FIG. 49 is a supplementary diagram of a 6-input AND / OR inverter circuit in which a basic cell is programmed according to the fourth embodiment of the present invention.

FIG. 50 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 51 is a circuit configuration diagram (1) programmable by a basic cell according to a fourth example of the present invention.

FIG. 52 is a circuit configuration diagram (part 2) programmable by a basic cell according to the fourth embodiment of the present invention.

FIG. 53 is an explanatory diagram of a D-type flip-flop circuit combining basic cells according to the fourth embodiment of the present invention.

FIG. 54 is a configuration diagram of a basic cell according to fifth and sixth embodiments of the present invention.

FIG. 55 is a configuration diagram of a basic cell according to seventh and eighth embodiments of the present invention.

FIG. 56 is a configuration diagram of a basic cell according to a ninth embodiment of the present invention.

FIG. 57 is a configuration diagram of a basic cell according to a tenth embodiment of the present invention.

FIG. 58 is a configuration diagram of a basic cell according to an eleventh embodiment of the present invention.

FIG. 59 is a configuration diagram of a three-input NAND circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 60 is a configuration diagram of a three-input NOR circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 61 is a configuration diagram of a four-input NAND circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 62 is a configuration diagram of a four-input NOR circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 63 is a configuration diagram of a three-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 64 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 65 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 66 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 67 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 68 is a configuration diagram of a basic cell according to a twelfth embodiment of the present invention.

FIG. 69 is a configuration diagram of a three-input NAND circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 70 is a configuration diagram of a three-input NOR circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 71 is a configuration diagram of a 4-input NAND circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 72 is a configuration diagram of a 4-input NOR circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 73 is a configuration diagram of a three-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 74 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 75 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 76 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 77 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 78 is a configuration diagram of a logic circuit included in a basic cell of an FPGA according to a conventional example.

[Explanation of symbols]

T1 to T4: first to fourth transistors; T5 to T8: fifth to eighth transistors; P1 to P22: first to 22nd program points; SD1 to SD12: source or drain extraction electrodes; PD6: first to sixth high-potential-side program switches, PS1 to PS6: first to sixth low-potential-side program switches, PB1 to PB4: first to fourth bypass program switches, Lout1, Lout2 ... First and second output wirings, LP1, LP2 ... First and second high-potential side auxiliary wirings, LN1, LN2 ... First and second low-potential side auxiliary wirings, Lin ... Input wiring, VDD , VSS ... first and second power supply lines.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (22)

(57) [Claims] 1. A first source or drain extraction electrode (SD1) and a second drain or source extraction electrode (S1).
D2), a second transistor (T1) including a third source or drain extraction electrode (SD3) and the second drain or source extraction electrode (SD2). T2), a fourth source or drain extraction electrode (SD4) and a fifth
A third transistor (T3) having a drain or source lead electrode (SD5), a sixth source or drain lead electrode (SD6), and a fifth drain or source lead electrode (SD5). A fourth transistor (T4) comprising: a first high-potential-side program switch; an input line (Lin) connected to the gates (G) of the first to fourth transistors (T1 to T4); A first source or drain extraction electrode (SD1) through (PD1)
And the second high-potential side program switch (P
D2) through a first power supply line (VDD) connected to the second drain or source lead electrode (SD2), and a fourth low potential side program switch (PS1). Source or drain extraction electrode (SD4)
A second power supply line (VSS) connected to the fifth drain or source lead electrode (SD5) via a second low-potential side program switch (PS2); Connected to the first source or drain extraction electrode (SD1) via a switch (P2);
Connected to the second drain or source lead electrode (SD2) via a third program switch (P3);
Connected to the third source or drain extraction electrode (SD3) via a fourth program switch (P4);
Connected to a fourth source or drain lead electrode (SD4) via an eighth program switch (P8),
A first output wiring (Lout 1) connected to the sixth source or drain lead electrode (SD6) through a second program switch (P12); and a first program switch (P1) through a first program switch (P1). Connected to a fourth source or drain extraction electrode (SD4);
Connected to the third source or drain lead electrode (SD3) via a fifth program switch (P5);
Connected to the fourth source or drain lead electrode (SD4) via a ninth program switch (P9);
The fifth source or drain extraction electrode (SD5) is connected via a tenth program switch (P10) to the fifth drain or source extraction electrode (SD5). SD6) connected to a second output wiring (Lout2) connected to the first source or drain extraction electrode (SD1), and connected to the third source via a sixth program switch (P6). Alternatively, the first output line (Lout 1) is connected to a first high-potential side spare line (LP1) connected to the drain extraction electrode (SD3) and a seventh program switch (P7). The fourth source or drain lead electrode (SD4) is connected to the second high-potential-side spare wiring (LP2), and the sixth source or drain is connected via the thirteenth program switch (P13). A first low-potential-side spare line (LN1) connected to the rain extraction electrode (SD6); and a second low-voltage side spare line (Lout2) connected to the second output line (Lout2) via a fourteenth program switch (P14). And a low potential side spare line (LN2). 2. The semiconductor integrated circuit device according to claim 1, wherein a third height provided between said first power supply line (VDD) and said third source or drain lead electrode (SD3). And a third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). A) a semiconductor integrated circuit device comprising: 3. The semiconductor integrated circuit device according to claim 1, wherein said first source or drain lead electrode (SD1) is provided between said third source or drain lead electrode (SD3). The first bias program switch (P
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) A semiconductor integrated circuit device comprising: 4. The semiconductor integrated circuit device according to claim 1, wherein a third height provided between said first power supply line (VDD) and said third source or drain lead electrode (SD3). And a third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). ) And a first bias program switch (P) provided between the first source or drain lead electrode (SD1) and the third source or drain lead electrode (SD3).
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) A semiconductor integrated circuit device comprising: 5. The semiconductor integrated circuit device according to claim 1, wherein said first and second transistors (T1, T2) are p-type field-effect transistors, and said third and fourth transistors (T1, T2). T3, T4) comprises an n-type field effect transistor. 6. The semiconductor integrated circuit device according to claim 1, wherein said program switches (PD1 to PD3, PS1 to PS
3, P1 to P14, PB1, PB2) are fuse elements, antifuse elements, or p-type or n-type field-effect transistors. 7. A first source or drain extraction electrode (SD1) and a second drain or source extraction electrode (SD1).
D2), a second transistor (T1) including a third source or drain extraction electrode (SD3) and the second drain or source extraction electrode (SD2). T2), a fourth source or drain extraction electrode (SD4) and a fifth
A third transistor (T3) having a drain or source lead electrode (SD5), a sixth source or drain lead electrode (SD6), and a fifth drain or source lead electrode (SD5). A fourth transistor (T4) comprising: a first high-potential-side program switch; an input line (Lin) connected to the gates (G) of the first to fourth transistors (T1 to T4); A first source or drain extraction electrode (SD1) through (PD1)
And the second high-potential side program switch (P
D2) through a first power supply line (VDD) connected to the second drain or source lead electrode (SD2), and a fourth low potential side program switch (PS1). Source or drain extraction electrode (SD4)
A second power supply line (VSS) connected to the fifth drain or source lead electrode (SD5) via a second low-potential side program switch (PS2); Connected to the first source or drain extraction electrode (SD1) via a switch (P2);
Connected to the second drain or source lead electrode (SD2) via a third program switch (P3);
Connected to the third source or drain extraction electrode (SD3) via a fourth program switch (P4);
Connected to a fourth source or drain lead electrode (SD4) via an eighth program switch (P8),
A second high-potential-side spare line (LP2) connected to the sixth source or drain lead electrode (SD6) through a second program switch (P12), and a first program switch (P1). Connected to the fourth source or drain extraction electrode (SD4),
Connected to the third source or drain lead electrode (SD3) via a fifth program switch (P5);
Connected to the fourth source or drain lead electrode (SD4) via a ninth program switch (P9);
The fifth source or drain extraction electrode (SD5) is connected via a tenth program switch (P10) to the fifth drain or source extraction electrode (SD5). SD6) connected to a second low-potential-side spare wiring (LN2) connected to the first source or drain lead-out electrode (SD1), and connected to the third program switch (P6) via a sixth program switch (P6). A first high-potential-side spare line (LP1) connected to the source or drain extraction electrode (SD3), and a second high-potential-side spare line (LP2) via a fifteenth program switch (P15) Connected to the first output wiring (Lout 1), which is connected to the fourth source or drain lead electrode (SD4), and connected via the thirteenth program switch (P13). A first low-potential-side spare line (LN1) connected to the source or drain extraction electrode (SD6), and a second low-potential-side spare line (LN2) via a sixteenth program switch (P16). And a second output wiring (Lout2) connected to the semiconductor integrated circuit device. 8. The semiconductor integrated circuit device according to claim 7, wherein a third height provided between the first power supply line (VDD) and the third source or drain lead electrode (SD3). A third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6); And a semiconductor integrated circuit device comprising: 9. The semiconductor integrated circuit device according to claim 7, wherein said semiconductor integrated circuit device is provided between said first source or drain lead electrode (SD1) and said third source or drain lead electrode (SD3). The first bias program switch (P
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) A semiconductor integrated circuit device comprising: 10. The semiconductor integrated circuit device according to claim 7, wherein a third height provided between said first power supply line (VDD) and said third source or drain lead electrode (SD3). And a third low-potential-side program switch (PS3) provided between the second power supply line (VSS) and the sixth source or drain lead electrode (SD6). ) And a first bias program switch (P) provided between the first source or drain lead electrode (SD1) and the third source or drain lead electrode (SD3).
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) A semiconductor integrated circuit device comprising: 11. The semiconductor integrated circuit device according to claim 7, wherein said first and second transistors (T1, T2) are p-type field-effect transistors, and said third and fourth transistors. (T3, T4) comprises an n-type field effect transistor. 12. The semiconductor integrated circuit device according to claim 7, wherein said program switches (PD1 to PD3, PS1 to PS
3, P1 to P14, PB1, PB2) are fuse elements, antifuse elements, or p-type or n-type field-effect transistors. 13. A first source or drain extraction electrode (SD1) and a second drain or source extraction electrode (SD).
D2), a second transistor (T1) including a third source or drain extraction electrode (SD3) and the second drain or source extraction electrode (SD2). T2), a fourth source or drain extraction electrode (SD4) and a fifth
A third transistor (T3) having a drain or source lead electrode (SD5), a sixth source or drain lead electrode (SD6), and a fifth drain or source lead electrode (SD5). A fourth transistor (T4) comprising: a seventh source or drain extraction electrode (SD7);
A fifth transistor (T5) having a drain or source lead electrode (SD8), a ninth source or drain lead electrode (SD9), and an eighth drain or source lead electrode (SD8). A sixth transistor (T6) including a tenth source or drain extraction electrode (SD10) and an eleventh drain or source extraction electrode (SD11); The twelfth source or drain lead electrode (SD12) and the eleventh drain or source lead electrode (SD11)
), An input wiring (Lin) connected to the gates (G) of the first to eighth transistors (T1 to T8), and a first high potential side A first source or drain lead electrode (SD1) via a program switch (PD1)
And the second high-potential side program switch (P
D2) to the second drain or source lead electrode (SD2), and via the third high potential side program switch (PD3) to the fourth source or drain lead electrode (SD4). A first power supply line (VDD) connected to the fifth drain or source lead electrode (SD5) via a fourth high-potential side program switch (PD4); The seventh source or drain lead electrode (SD7) via the potential side program switch (PS1)
And a second low-potential-side program switch (P
S2) is connected to the eighth drain or source lead electrode (SD8), and is connected to the tenth source or drain lead electrode (SD10) via the third low potential side program switch (PS3). And a fourth low-potential side program switch (PS4).
A second power supply line (VSS) connected to the drain or source lead electrode (SD11) of the first and second source / drain lead electrodes (SD1) via a second program switch (P2). And
Connected to the second drain or source lead electrode (SD2) via a third program switch (P3);
Connected to the third source or drain extraction electrode (SD3) via a fourth program switch (P4);
A fourth source or drain extraction electrode (SD4) is connected through an eighth program switch (P8),
Connected to the fifth drain or source lead-out electrode (SD5) through the program switch (P9).
Connected to the sixth source or drain lead electrode (SD6) through one program switch (P11);
The seventh source or drain extraction electrode (SD7) is connected via a twelfth program switch (P12), and the ninth source or drain extraction electrode (SD16) is connected via a sixteenth program switch (P16). SD9) and a tenth source or drain extraction electrode (SD10) via an eighteenth program switch (P18).
And the twenty-second program switch (P2
2) a first output wiring (Lout1) connected to the twelfth source or drain lead electrode (SD12) via
Connected to the first source or drain lead electrode (SD1) via a first program switch (P1);
Connected to the third source or drain lead electrode (SD3) via a fifth program switch (P5);
Connected to the fourth source or drain lead electrode (SD4) via a seventh program switch (P7);
Connected to a sixth source or drain extraction electrode (SD6) via an eleventh program switch (P11),
Connected to a seventh source or drain extraction electrode (SD7) via a thirteenth program switch (P13),
Connected to an eighth drain or source lead electrode (SD8) via a fourteenth program switch (P14),
Connected to a ninth source or drain extraction electrode (SD9) via a fifteenth program switch (P15),
Through the nineteenth program switch (P19)
Is connected to the source or drain extraction electrode (SD10), and is connected to the eleventh drain or source extraction electrode (SD11) via the twentieth program switch (P20), and is connected to the twenty-first program switch (P21). Through the twelfth source or drain extraction electrode (SD12)
And a second output wiring (Lout2) connected to the semiconductor integrated circuit device. 14. The semiconductor integrated circuit device according to claim 13, wherein said fifth power supply line is provided between said first power supply line (VDD) and said third source or drain lead electrode (SD3). A potential-side program switch (PD5); and a sixth high-potential-side program switch (PD6) provided between the first power supply line (VDD) and the sixth source or drain lead electrode (SD6). A fifth low-potential-side program switch (PS5) provided between the second power supply line (VSS) and the ninth source or drain extraction electrode (SD9); A sixth low potential side program switch (PS6) provided between a power supply line (VSS) and the twelfth source or drain lead electrode (SD12). . 15. The semiconductor integrated circuit device according to claim 13, provided between the first source or drain lead electrode (SD1) and the third source or drain lead electrode (SD3). The first bias program switch (P
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) and a third bias program switch (P) provided between the seventh source or drain lead electrode (SD7) and the ninth source or drain lead electrode (SD9).
B3) and the tenth source or drain extraction electrode (SD10
) And a fourth bias program switch (PB4) provided between the twelfth source or drain lead electrode (SD12). 16. The semiconductor integrated circuit device according to claim 13, wherein a fifth source or drain extraction electrode (SD3) and a fifth power supply line (VDD) are provided between the third power supply line and the first power supply line (VDD). A high-potential-side program switch (PD5); a sixth high-potential-side program switch provided between the sixth source or drain lead electrode (SD6) and the first power supply line (VDD). (PD6), a fifth low-potential-side program switch (PS5) provided between the ninth source or drain extraction electrode (SD9) and the second power supply line (VSS), Twelfth source or drain extraction electrode (SD12
) And the second power supply line (VSS), a sixth low-potential-side program switch (PS6), the first source or drain extraction electrode (SD1) and the third A first bias program switch (P) provided between the source or drain lead electrode (SD3).
B1) and a second bias program switch (P) provided between the fourth source or drain lead electrode (SD4) and the sixth source or drain lead electrode (SD6).
B2) and a third bias program switch (P) provided between the seventh source or drain lead electrode (SD7) and the ninth source or drain lead electrode (SD9).
B3) and the tenth source or drain extraction electrode (SD10
) And a fourth bias program switch (PB4) provided between the twelfth source or drain lead electrode (SD12). 17. The semiconductor integrated circuit device according to claim 13, wherein said first to fourth transistors (T1 to T4) are p.
Type field effect transistors, wherein the fifth to eighth transistors (T5 to T8) are n
A semiconductor integrated circuit device comprising a field-effect transistor of a type. 18. The semiconductor integrated circuit device according to claim 13, wherein said program switches (PD1 to P
D6, PS1 to PS6, P1 to P22, PB1 to PB4) are fuse elements, antifuse elements, or p-type or n-type.
A semiconductor integrated circuit device comprising a field-effect transistor of a type. 19. A semiconductor integrated circuit device comprising a logic circuit formed by combining two or more of the basic cells comprising the semiconductor integrated circuit device according to claim 1. 20. A semiconductor integrated circuit device comprising a logic circuit by combining two or more of the basic cells comprising the semiconductor integrated circuit device according to claim 7. 21. A semiconductor integrated circuit device comprising two or more basic cells comprising the semiconductor integrated circuit device according to claim 13 to form a logic circuit. 22. A semiconductor integrated circuit device, comprising a logic circuit formed by combining two or more basic cells comprising the semiconductor integrated circuit device according to claim 19.