JP3062092B2 - Oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit built in a semiconductor integrated circuit, and more particularly to an oscillation circuit capable of generating a frequency equivalent to an oscillation frequency in a normal operation in a wafer sorting inspection process in a manufacturing process. .

[0002]

2. Description of the Related Art Referring to FIG. 5, which shows an example of this type of oscillation circuit, inverters 5, 6, and 7 are cascaded, and the input terminal of an initial stage inverter 5 is connected to a pad 1 and the final stage inverter 7 is connected to a pad 1. Output terminals are connected to the pads 2 respectively. A resistance element 4 is connected between the pad 1 and the pad 2 via the pad 3 , and a capacitance element 8 is connected between the pad 1 and the output terminal of the inverter 6. Inverter 5
Are connected to a predetermined circuit of an internal circuit via an inverter 9.

In this circuit, the output of the inverter 7 is connected to one of the resistance elements 4 by short-circuiting the pads 2 and 3 with metal wiring outside the wafer (indicated by dotted lines in the figure). , Set to a state where oscillation is possible. When the power supply voltage is supplied in this state, the capacitance element 8 is charged as the power supply voltage increases. When the voltage at the connection point A rises and exceeds the input threshold of the inverter 5, the output of the inverter 5 is inverted. In response to this inversion, the outputs of the inverters 6 and 7 are also inverted, and the output of the inverter 7 becomes a logic low level, and the voltage at the point A starts to decrease.

When the inverter 7 goes to a low level, the inverter 7 is discharged through a transistor on the ground side of the inverter 7, and the output of the inverter 5 is inverted to a high level. In response to this inversion, the output of the inverter 7 is also inverted to a high level, and the voltage at the point A starts to rise. By repeating this, a signal of a constant frequency is obtained.

On the other hand, depending on a customer's request, a signal is input from the outside via the pad 1 without causing self-oscillation to operate the internal circuit. At that time, the external connection wiring between the pads 2 and 3 is released, and a signal is input from the pad 1.

In the above-described oscillation circuit, the IC tester 2
When measuring the oscillation frequency in the wafer state by the method 2, a probe is set on each pad and the frequency output from the output of the pad 2 is measured.

Another conventional oscillator circuit is disclosed in Japanese Unexamined Patent Publication No. 63-2 / 1988.
66373. Referring to FIG. 6 which shows a circuit diagram of the oscillation circuit described in the publication, one end of a transmission gate 13 is connected to the pad 1, and the other end of the transmission gate 13 is connected to the pad 1.
Each input terminal of the Schmitt circuit 19 and the inverter 6 against
It is continued further, the output terminal of the Schmitt circuit 19 is connected via an inverter 5 and a resistance element 4. The output terminal of the Schmitt circuit 19 is further connected to an internal circuit and connected to one input terminal of an OR circuit 20 and an AND circuit 21. The other terminal of the OR circuit 20 and the AND circuit 21 is connected to the output terminal of the inverter 6. Ru are connected. OR
The output terminal of the circuit 20 is a P-channel MOS transistor 2
Lee of two and N-channel MOS transistor 23
It is connected to the gate electrode of the P-channel MOS transistor 22 of the inverter, the output terminal of the AND circuit 21, N channel
N is connected to the gate electrode of the MOS transistor 23.
The drain electrode of the channel MOS transistor 22 is also connected to the other end of the transmission gate 13, and the capacitor 8 is also connected between the other end and the ground terminal.

When the internal circuit is operated by inputting a signal from the outside to the oscillation circuit having the above configuration, the transmission gate 13 is turned on by a test signal and a signal is input from the pad 1. Output to

When operating the internal circuit by self-oscillation, the test signal is deactivated, the transmission gate 13 is turned off, and cut off from the external circuit to start oscillation.

In order to confirm this oscillation, the transmission gate 13 is turned on and an oscillation signal is output from the pad 1 to the outside to confirm the oscillation.

When the oscillation frequency is measured by the IC tester 22, the transmission gate 13 must be in a conductive state and the probe must be set up on the pad 1 in the same manner as described above.

[0012]

In the above-mentioned conventional oscillation circuit, there is a problem that the oscillation frequency measured by the IC tester is different from the oscillation frequency in a normal use state.

The reason is that in the conventional example shown in FIG.
If you try to measure the oscillation frequency in the C tester 22, each pad is in contact with the probe of the IC tester 22, the IC tester 22 which is particularly connected to the probe and this probe is in contact with the pad 1 Due to the influence of the parasitic capacitance, the oscillation frequency becomes different from the actual oscillation frequency.

For example, if the sum of the parasitic capacitances applied to the capacitive element 8 and the pad 1 is designed to be 10 pF, the probe in contact with the pad 1 and the IC tester 22 connected to the probe 1 Assuming that the parasitic capacitance on the side is 5 pF, the oscillation frequency measured at the pad 2 is 1/1 / the actual oscillation frequency.
It becomes 1.5 times, and a shift of 33% occurs.

Further, since the parasitic capacitance value of the IC tester 22 differs depending on the model or the like, the magnitude of the deviation of the transmission frequency cannot be specified.

From the above description, the difference between the measured oscillation frequency value and the design value is due to the influence of the parasitic capacitance of the IC tester 22 generated through the probe in contact with the pad 1 or due to defective manufacturing. It cannot be determined whether or not the actual oscillation frequency itself deviates from the designed oscillation frequency.

In the latter case due to a manufacturing defect, the cause of the failure of the semiconductor integrated circuit incorporating the oscillation circuit, the oscillation signal of the semiconductor integrated circuit itself, or the oscillation signal is transmitted through the internal circuit of the semiconductor integrated circuit. It can be a factor of causing an operation failure in another semiconductor integrated circuit using the output signal.

In the conventional example shown in FIG. 6, when the self-oscillation is performed, the transmission gate 13 is made non-conductive to disconnect from the external circuit. Therefore, the parasitic capacitance of the IC tester 22 generated through the probe contacting the pad 1 is generated. Is not affected.

However, when measuring the oscillation frequency, the transmission gate 13 must be turned on and the oscillation signal must be measured at the pad 1. In this case, the oscillation signal is generated through the probe in contact with the pad 1. This is affected by the parasitic capacitance of the IC tester 22, and an oscillation frequency different from the actual oscillation frequency is measured.

Whether the deviation of the measurement frequency is due to the influence of the parasitic capacitance generated in the IC tester 22 through the probe in contact with the pad 1 as in the conventional example of FIG.
It is not possible to determine whether or not the actual oscillation frequency itself deviates from the designed oscillation frequency due to a manufacturing defect.

In the case of a manufacturing defect, also in this example, the cause of the defect of the semiconductor integrated circuit incorporating the oscillation circuit, the oscillation signal of the semiconductor integrated circuit itself, or the oscillation signal is transmitted to the internal circuit of the semiconductor integrated circuit. It may be a factor of causing an operation failure in another semiconductor integrated circuit that uses a signal output through the semiconductor integrated circuit.

An object of the present invention has been made in view of the above-mentioned drawbacks. In an inspection process of a semiconductor integrated circuit having a built-in oscillation circuit, an oscillation frequency capable of inspecting the same oscillation frequency as in a normal operation state with high accuracy. It is to provide a circuit and contribute to improvement of reliability.

[0023]

A feature of the oscillation circuit of the present invention is that an odd number of inverters are connected in cascade, and a capacitive element is provided between the input terminal of the first-stage inverter and the output terminal of the even-numbered inverter. Connected, a resistor element is connected between the input terminal of the first-stage inverter and the output terminal of the odd-numbered inverter, and a first pad is connected to the first-stage input terminal.
In an oscillation circuit in which a second pad is connected to an output terminal of the odd-numbered stage, a dummy pad having the same structure and the same parasitic capacitance as the first pad is further connected to an input terminal of the first-stage inverter; A switch means is provided between the first pad and the dummy pad and the input terminal of the first stage, in which conduction and non-conduction are controlled in a complementary relationship in response to control signals having opposite polarities. .

The switch means is a transmission gate combining a P-channel type MOS transistor and an N-channel type MOS transistor.
The control signal is supplied to the OS transistor and the N-channel MOS transistor of the other transmission gate by the N-channel MOS transistor of one transmission gate.
An inversion signal of the control signal is supplied to the OS transistor and the P-channel MOS transistor of the other transmission gate to be controlled.

Further, each of the switch means has a P
It can be composed of only channel type MOS transistors.

Further, each of the switch means may be constituted only by an N-channel MOS transistor.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION The oscillation circuit of the present invention turns off the first switch element when measuring the oscillation frequency, thereby cutting off the influence of the parasitic capacitance of the IC tester attached through the probe contacting the pad. Since the input terminal of the oscillation circuit has the same parasitic capacitance as this input terminal and replaces it with a dummy pad that does not touch the probe, it does not differ from the parasitic capacitance during normal operation and has an accuracy that is not affected by the parasitic capacitance of the IC tester. This is a circuit that can measure high oscillation frequency.

FIG. 1 is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention. Referring to FIG. 1, an odd number of inverters 5, 6, and 7 are connected in cascade, and a capacitive element 8 is connected between the input terminal of the first-stage inverter 5 and the output terminal of the second-stage.
Connect. Input terminal and output terminal 3 of first stage inverter 5
And a first pad 1 connected to an input terminal of the first-stage inverter 5 via a switch element 10.
However, the second pad 2 is connected to the output terminal of the third stage. A pad 12 having the same structure and the same parasitic capacitance as the first pad 1 is further connected to the input terminal of the first-stage inverter 5 via the switch element 11. Switch elements 10 and 11 connected between pads 1 and 12 and the input terminal of first-stage inverter 5 are provided with switch elements 10 and 11 whose conduction and non-conduction are controlled in a complementary manner by a test signal and a test signal bar. The configuration is such that a clock is supplied from the output of the inverter 5 to the internal circuit via the inverter 9.

The pad 12 is provided as a dummy pad so that the probe for measurement does not come into contact with the pad.

The switch element 10 and the switch element 11 perform a complementary operation. That is, when the switch element 10 is in the conductive state, the switch element 11 is in the non-conductive state, and when the switch element 10 is in the non-conductive state, the switch element 11 is in the conductive state.

When an operation test of an IC is performed by inputting a clock signal from the outside, switch element 10 is rendered conductive, and a signal is transmitted to an internal circuit via inverter 5 and inverter 9.

When the oscillation frequency is measured by self-oscillation, the switch element 10 is turned off by a test signal, the switch element 11 is turned on by a test signal bar, and the pad 1 is disconnected from the oscillation circuit. And the dummy pad 12 is connected.

At this time, the pads 2 and 3 are externally connected by wiring (equivalently indicated by dotted lines in the figure). Due to this external connection, even when the IC tester 22 is connected through the probe in contact with the pad 1, the switching element 10 is in a non-conductive state, so that oscillation is not affected by the parasitic capacitance of the IC tester 22. The frequency can be measured.

Further, since the dummy pad 12 equal parasitic capacitance between the pad 1 is connected, during normal operation pad
Will be 1 and similar parasitic capacitance is had with, it is possible to measure the same oscillation frequency as the normal operation with high precision.

When measuring the oscillation frequency, a pad
Perform in 2. At this time, pads 2 and 3 are connected externally.
However, the resistance element 4 has a high resistance and
Since the conduction resistance of the resistor 7 is low,
Indicates that the parasitic capacitance of the IC tester 22 is added to the pad 3.Be
However, the influence on the oscillation frequency is negligible.

For example, assume that the resistance element 4 is 1 MΩ and the conduction resistance of the inverter 7 is 100 Ω. Also,
The capacitance of the capacitance element 8 is 10 pF, and the total parasitic capacitance added to the pad 2 or the pad 3 is 10 pF.

The oscillation frequency f of this type of oscillation circuit is obtained by the following equation: 1 / f = −R · C · ln (Vt · (Vdd−Vt) / (Vdd + Vd) ² ) (1) .

Here, R is a resistance value (in this case, 1M
Ω), C is a capacitance value (design value is 10 pF), Vdd is a power supply voltage (3 V in this case), Vt is a logical threshold value of the inverter 5 (Vdd / 2 in this case), and Vd is an overshoot of the oscillation waveform. Alternatively, it indicates an undershoot (in this case, 0.5 V).

Under the above conditions, the oscillation frequency f is 5
9 KHz.

On the other hand, when the total value of the parasitic capacitance added to pad 2 or pad 3 is 10 pF, this parasitic capacitance is charged through the P-channel MOS transistor of inverter 7 and discharged through the N-channel MOS transistor. The charge / discharge time constant τ of the pad 3 is as follows: τ = 100Ω × 10 pF = 1 nS (2)

Therefore, an error of less than 0.01% with respect to the oscillation period of 16.95 μS is obtained.

FIG. 2 shows a modification of the first embodiment.
Switch elements 11 and 12 have a transmission gate structure in which a P-channel MOS transistor and an N-channel MOS transistor, which are semiconductor elements, are connected in parallel. The other configuration is the same as the circuit configuration shown in FIG. The same reference numerals are given to the same components, and the description of the configuration here is omitted.

Transmission gates 13 and 14 operate in the same manner as switching elements 10 and 11, respectively.

For example, when an operation test of an IC is performed by inputting a clock signal from the outside, transmission gate 13 is turned on to transmit a signal to an internal circuit via inverter 5 and inverter 9.

When the oscillation frequency is measured by self-oscillation, the test signal is set to a low level to make the transmission gate 13 non-conductive, the transmission gate 14 is made conductive, and the pad 1 is separated from the oscillation circuit. The pad 12 is connected.

At this time, similarly, the pad 2 and the pad 3 are connected to the outside to cause self-transmission. Pad 1
Even when the IC tester 22 is connected through the probe contacted with the IC, the transmission gate 13 is in a non-conductive state, so that the oscillation frequency can be measured without being affected by the parasitic capacitance of the IC tester 22. .

FIG. 3 shows another modification of the first embodiment, in which switch elements 10 and 11 are replaced by P-channel MOS transistors 15 and 16. The other configuration is the same as the circuit configuration shown in FIG. 1, so the same components are denoted by the same reference numerals,
The description of the configuration here is omitted.

When an operation test of the IC is performed by inputting a clock signal from the outside, the test signal is set to a low level to make P channel MOS transistor 15 conductive, and an internal circuit is connected via inverter 5 and inverter 9. Signal.

When the oscillation frequency is measured by self-oscillation, the test signal is set to the high level and the P-channel M
The OS transistor 16 is turned on, and the P-channel MO
The S transistor 15 is turned off, the pad 1 is disconnected from the oscillation circuit, and the dummy pad 12 is connected. Also in this case, the pads 2 and 3 are externally connected by wiring.
Due to this external connection, even if the IC tester 22 is connected through the probe in contact with the pad 1,
Since 0 is in the non-conductive state, the oscillation frequency can be measured without being affected by the parasitic capacitance of the IC tester 22.

FIG. 4 shows still another modification of the first embodiment, in which switch elements 10 and 11 are replaced with N-channel MOS transistors 17 and 18, and the other structure is the same as that of FIG. Since the circuit configuration is the same as that described above, the same reference numerals are given to the same components, and the description of the configuration is omitted.

When an operation test of an IC is performed by inputting a clock signal from the outside, the test signal is set to a high level to make N-channel MOS transistor 17 conductive, and an internal circuit is provided via inverter 5 and inverter 9. Transmit signals to the circuit.

When the oscillation frequency is measured by self-oscillation, the test signal bar is set at a high level to turn on the N-channel MOS transistor 18, the N-channel MOS transistor 17 is turned off, and the pad 1 is oscillated. Separate from the circuit and connect the dummy pad 12.
Also in the case of this modification, as described above, the pad 2 and the pad 3
Is connected to the outside and self-originated, and pad 1
Even when the IC tester 22 is connected through the probe contacted with the IC, the transmission gate 13 is in a non-conductive state, so that the oscillation frequency can be measured without being affected by the parasitic capacitance of the IC tester 22. .

[0053]

As described above, in the oscillation circuit of the present invention, an odd number of inverters are connected in cascade, and a capacitive element is connected between the input terminal of the first-stage inverter and the output terminal of the even-numbered stage. A resistor is connected between the input terminal of the first-stage inverter and the output terminal of the odd-numbered inverter, and a first pad is connected to the first-stage input terminal, and a second pad is connected to the odd-numbered output terminal. A dummy pad having the same structure and the same parasitic capacitance as the first pad is connected to the input terminal of the first-stage inverter, and the oscillation circuit is connected between the first and first pads and the first-stage input terminal. Is provided with switch means for controlling conduction and non-conduction in a complementary relationship in response to control signals having opposite polarities, so that the oscillation frequency can be measured with high accuracy regardless of the parasitic capacitance of the measurement system. be able to.

For example, if the parasitic capacitance of the capacitive element of the oscillation circuit and the input side pad is 10 pF, and the parasitic capacitance of the measuring device attached to this pad is 5 pF, the conventional example causes a frequency shift of about 33%. In this case, since a dummy pad having the same structure and the same parasitic capacitance as the input side pad is replaced, the frequency shift becomes almost 0%. If the measured oscillation frequency is different from the oscillation frequency at the time of design, it can be determined that the deviation of the generated frequency is due to the actual oscillation frequency itself deviating from the oscillation frequency at the time of design due to diffusion conditions at the time of manufacture. Therefore, when an oscillation signal of a semiconductor integrated circuit incorporating an oscillation circuit or a signal obtained through the internal circuit of the semiconductor integrated circuit uses the oscillation signal by another semiconductor integrated circuit, By checking whether or not the measured oscillation frequency falls within the operation guarantee range, it can be determined whether or not another semiconductor integrated circuit operates.

Another effect of the present invention is improvement in reliability for actual operation. The reason is that if the measured oscillation frequency is different from the oscillation frequency at the time of design, the deviation is caused by manufacturing variations.If the measured value exceeds the allowable range for the product, It can be removed as a defective product, and the outflow of the defective product can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a modified example of the first embodiment.

FIG. 3 is a circuit diagram of another modification of the first embodiment.

FIG. 4 is a circuit diagram of still another modification of the first embodiment.

FIG. 5 is a circuit diagram of an example of a conventional oscillation circuit.

FIG. 6 is a circuit diagram of another example of the conventional oscillation circuit.

[Explanation of symbols]

 1, 2, 3, 12 Pad 4 Resistance element 5, 6, 7, 9 Inverter 8 Capacitance element 10, 11 Switch element 13, 14 Transmission gate 15, 16, 22 P-channel MOS transistor 17, 18, 23 N-channel MOS transistor 19 Schmitt circuit 20 OR circuit 21 AND circuit 22 IC tester

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 G01R 31/26 H01L 21/66 H01L 21/82 H01L 21/822 H01L 27 / 04

Claims (4)

(57) [Claims] 1. An odd number of inverters are connected in cascade, a capacitive element is connected between an input terminal of a first stage inverter and an output terminal of an even number stage inverter, and an input terminal of the first stage inverter is connected to an odd number stage. An oscillation circuit in which a resistance element is connected between the output terminal of the first inverter and a first pad is connected to the input terminal of the first stage, and a second pad is connected to the output terminal of the odd stage. A dummy pad having the same structure as that of the first pad and having the same parasitic capacitance is further connected to an input terminal of the first-stage inverter, and a mutual connection is provided between the first pad and the dummy pad and the first-stage input terminal. An oscillator circuit, comprising: switch means for controlling conduction and non-conduction in a complementary relationship in response to a control signal having a reverse polarity. 2. The switch means is a P-channel type MO.
A transmission gate in which an S transistor and an N-channel MOS transistor are combined, wherein a P-channel MOS transistor of one transmission gate and an N-channel MOS transistor of the other transmission gate
2. The control circuit according to claim 1, wherein the control signal is supplied to a channel MOS transistor, and an inverted signal of the control signal is supplied to an N-channel MOS transistor of one transmission gate and a P-channel MOS transistor of the other transmission gate. Oscillator circuit. 3. The oscillation circuit according to claim 1, wherein each of said switch means comprises only a P-channel MOS transistor. 4. The oscillation circuit according to claim 1, wherein each of said switch means comprises only an N-channel MOS transistor.