JP3065002B2 - Interface circuit and semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit and a semiconductor integrated device. For example, the present invention is applied to an interface circuit for performing a level shift with respect to a semiconductor integrated circuit device having a power supply voltage of 5 V in a semiconductor integrated circuit device having a power supply voltage of 3 V. What you get.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor integrated circuits (hereinafter abbreviated as "LSIs"), the power supply voltage supplied to LSIs also increases from 5V.
It has been scaled down to 3V. However, in reality, there are many LSIs that operate at a power supply voltage of 5V.

For this reason, LSIs with power supply voltages of 5 V and 3 V are often used on the same system. Therefore, a so-called input / output interface circuit for transmitting and receiving signals to and from the 5V power supply LSI on the 3V power supply LSI side is required.

[0004] From the output of the LSI of the power supply voltage 3V to L of the power supply voltage 5V
When data is output to the SI bus, it is often pulled up with an external resistor in order to secure the output level of 5 V, and 5 V is applied to the output of the LSI with the power supply voltage of 3 V.

However, since the thickness of the gate oxide film of the MOS transistor constituting the LSI having the power supply voltage of 3 V is about 10 nm, the applied voltage is determined from the reliability of the oxide film.
Must be 4.5V or less.

An example of this type of conventional interface circuit is described in Japanese Patent Application Laid-Open No. Hei 5-327465, and as an improvement example, the "interface circuit" of the invention described in Japanese Patent Application Laid-Open No. 8-37457 is disclosed. Has been proposed. Here, the interface circuit of the invention described in Japanese Patent Application Laid-Open No. 5-327465 will be described with reference to FIG.

In this figure, the output circuit is connected to the power supply potential.
Connect the gate electrode between the VDD terminal and the ground potential GND as an input terminal
A P-channel MOS transistor connected to I1 (hereinafter “PMO
N-channel MOS transistor (hereinafter referred to as "NMOS") that connects M1 and the gate electrode to the input terminal I2.
M2 is connected in series, an NMOS M3 is connected between the series connection point A and the output terminal B, and the gate electrode is connected to VDD.
It is configured to be connected to terminals. Here, the substrate potential of the PMOS (N-well potential) is fixed to the power supply potential, and the substrate potential of the NMOS is fixed to the ground potential. The NMOS M3 is a non-doped transistor, and has a threshold voltage VT set near "0V".

On the other hand, as shown in FIG. 4 (a cross-sectional view schematically showing a part of this output circuit), this output circuit has an N-well region 42 and an N ⁺ diffusion layer 43 on a P-type semiconductor substrate 41. And 4
4 are formed, these N ⁺ diffusion layers 43 and 44 form the source and drain electrodes of the NMOS M3, and the gate is connected to the power supply voltage VD.
Connected to D terminal. In the N well region 42, a P ⁺ diffusion layer 45
And 46 and an N ⁺ diffusion layer 47 are formed, and P ⁺ diffusion layers 45 and 46 are formed.
Form the source and drain electrodes of the PMOS M1, and the N ⁺ diffusion layer 47 is connected to the VDD terminal together with the P ⁺ diffusion layer 46. Further, the P ⁺ diffusion layer 45 and the N ⁺ diffusion layer 44 are commonly connected.

When a signal voltage of 5 V is supplied to the output terminal B, the potential "VA" at the point A (see FIG. 3) via the NMOS M3.
Is represented by: Equation (1) VA = VDD−VTHM3. VTHM3 is the threshold voltage of M3.

Here, the power supply voltage is a maximum of 3.6 V,
If VTM3 is set to “0V”, the potential at point A will be about 3.6
V, the potential difference between the gate and the source and the potential difference between the gate and the drain are about 4.5 V or less, and the reliability of the gate oxide film is secured.

A transistor having VT ≒ 0 V can be easily realized by forming a transistor on a commonly used P-type substrate having a concentration of 1E15 (cm ⁻³ ) without channel doping. However, in the circuit described above, NM
When "VT" of OSM3 becomes a negative voltage due to manufacturing variations, there is a problem that a leak current flows.

If the case of "VTM3 = -0.5V" is taken as an example, when 5 V is applied to the output terminal B, the contact A
From the above equation (1), the following equation is obtained: Equation (2) VA = VDD−VTM3 = 3.5V

Here, referring again to FIG.
^A forward voltage of 0.5 V is applied to the PN junction formed between ⁺ diffusion layer 45 and N well 42, and a leak current flows. In particular, configure the output circuit
In a so-called high impedance state in which both the PMOS M1 and the NMOS M2 are in a non-conductive state, this leakage current becomes a serious problem.

In order to solve such a problem, Japanese Patent Application Laid-Open
An "interface circuit" described in JP-A-8-37457 has been proposed. This "interface circuit" will be described with reference to FIG. In FIG. 5, in the interface circuit, a PMOS M1 connecting the gate electrode to the input terminal I1 and an NMOS M2 connecting the gate electrode to the input terminal I2 are connected in series between the power supply potential VDD terminal and the ground potential GND terminal. An NMOS is connected between the series connection point A and the output terminal B.
M3 is connected, and its gate electrode is connected to the VDD terminal.

Further, the substrate (N well) of the PMOS M1 is an NMO
It is connected to VDD via SM4, and its gate electrode is connected to the power supply voltage VDD terminal. On the other hand, the structure of a part of this output circuit will be described with reference to FIG. 6 which is a cross-sectional view. On a P-type semiconductor substrate 61, an N well 62, N ⁺ diffusion layers 63 and 64,
N ⁺ diffusion layers 65 and 66 are provided, and N ⁺ diffusion layers 63 and 64 are provided.
Form the source and drain of the NMOS M3, and the N ⁺ diffusion layer 65,
66 forms the source and drain of the NMOS M4.

The gate electrode of the NMOS M3, the gate electrode of the NMOS M4, and the N ⁺ diffusion layer 65 are connected to the power supply voltage VDD. On the N well 62, P ⁺ diffusion layers 67 and 68 and an N ⁺ diffusion layer 69 are formed. The P ⁺ diffusion layers 67 and 68 form the drain and source of the PMOS M1, and the N ⁺ diffusion layer 69 is the N ⁺ of the NMOS M4. ⁺ Connected to diffusion layer 66. Further, the P ⁺ diffusion layer 67 and the N ⁺ diffusion layer
64 are connected in common. (Note that the illustration of the NMOS M2 is omitted in the cross-sectional view shown in FIG. 6.)

In the above-described configuration, the NMOS M3 connected between the series connection point A and the output terminal B in FIG. 5 operates as a level shifter to realize a power supply voltage 5V system and a 3V system interface circuit. This is no different from the prior art described in JP-A-5-327465. here,
In the improvement example, the NMOS M4 is set so that the potential of the N-well region where the PMOS M1 is formed becomes the same as the potential of the point A in FIG.

Next, the problem of the conventional example described in Japanese Patent Application Laid-Open No. 5-327465, that is, when this output circuit is in a high impedance state, the "VT" of the NMOS M3 and the NMOS M4 is high.
Will be described. For example, if "VT = -0.5",
When "5V" is applied to the output terminal, the potential at point A in FIG. 5 becomes "3.5V" as described above. At this time, FIG.
P ⁺ diffusion layer 67 shown in is transient current is biased in the forward direction flows, the potential of the N well 62 becomes 3.5V instantaneously. At this time, the NMOS M4 having the same VT as the NMOS M3 is turned off, and no current flows. Therefore, no leak current occurs in the steady state.

[0019]

However, the above-mentioned improved example still has a drawback that latch-up easily occurs for the following two reasons. First, since the forward current flows transiently, the forward current triggers the latch-up. Second, since the potential of the N-well 62 in FIG. 6 is fixed by the NOMOS M4 having VT of "about 0 V", the impedance to the VDD terminal is high, and electrons are injected into the N-well 62 due to external noise or the like. In this case, the potential of the N-well 62 immediately drops, and the possibility of occurrence of latch-up increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a circuit for performing a level shift between circuits having different power supply voltages. It is an object of the present invention to provide an interface circuit and a semiconductor integrated device which prevent the occurrence of an error and do not cause latch-up.

[0021]

According to another aspect of the present invention, there is provided an interface circuit comprising a complementary semiconductor integrated circuit, wherein a first high-potential power is supplied and an internal circuit is provided. And an output terminal for outputting the signal of the output circuit and receiving a second high-potential higher than the first high-potential power supply from outside, and an output terminal between the output terminal and the output circuit. Second inserted
And a level shifter for lowering the level to a predetermined voltage so that the higher potential of the output circuit is not directly applied to the output circuit, the N-well where the first P-channel transistor forming the output circuit is formed is in a steady state. Is connected to a first high-potential power supply, and has a means for connecting to the same potential as the output point of the output circuit when the output circuit is in a high-impedance state and a high-potential is supplied to the output terminal. (Claim 1).

The interface circuit according to the present invention, in the above interface circuit, comprises a series connection point A between the first N-channel transistor and the first P-channel transistor constituting the output circuit; A second N-channel transistor for a level shifter is connected between the first and second transistors.

Further, in the interface circuit according to the present invention, in the above-mentioned interface circuit, the N-well is connected in series between the first high-potential power supply and the serial connection point A. Series connection point C between the second P-channel transistor connected to the power supply of the second power supply and the third P-channel transistor connected to the series connection point A
And the second P-channel transistor is turned on in a steady state.
(Claim 3).

As a result, in the steady state, the N-well operates by the application of the first high potential by the second P-channel transistor. For this reason, compared with the conventional example in which the connection is made by N-channel transistors, the power supply can be connected to the first high-potential power supply with lower impedance, and the risk of occurrence of latch-up can be significantly reduced.

Still further, in the interface circuit according to the present invention, in the above interface circuit, the third P-channel transistor is turned on only when the output circuit is in a high impedance state and the second high potential is applied to the output terminal. It further comprises a NAND circuit for controlling the operation (claim 4). According to the present invention,
High impedance with one input terminal of NAND circuit,
A third N-channel transistor for level shift is interposed between the other input terminal and the output terminal of the NAND circuit (claim 5).

With the above configuration, when the output circuit is in a high impedance state, the second high potential is externally applied to the output terminal, and the drain diffusion layer of the first P-channel transistor constituting the output circuit And the N-well have the same potential, thereby preventing generation of a leak current without flowing in the forward direction. Also, latch-up can be reduced.

Further, the semiconductor integrated device according to the present invention is
An N well, a P channel type diffusion layer, and an N channel type diffusion layer are formed on a P channel type semiconductor substrate, and the N well, the P channel type diffusion layer, and the N channel type diffusion layer are used. And a signal having a higher potential than the power supply potential in the device is applied to the output terminal to perform an interface operation. By adopting such a configuration, transmission and reception of signals operating at different voltages can be performed freely, and the reliability and functionality of the device can be increased.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an interface circuit and a semiconductor integrated device according to the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of an interface circuit according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a partial structure of the output circuit of the present embodiment.

As shown in FIG. 1, the interface circuit of the present embodiment includes a PMOS M1 having a gate electrode connected to an input terminal I1 between a power supply potential VDD terminal and a ground potential GND terminal.
And an NMOS M2 for connecting the gate electrode to the input terminal I2 is connected in series, and NO is connected between the series connection point A and the output terminal B.
The MOSM3 is connected, and its gate electrode is connected to the VDD terminal.

Further, the substrate (N well) of the PMOS M1 is a PMO
Controlled by a series connection point C between SM5 and PMOS M6, in a steady state, PMOS M5 is turned on and connected to VDD.
Further, the output circuit formed of the PMOS M1 and the NMOS M2 by the NAND1 is in a high impedance state, and the PMOS M6 is turned on only when a high potential is applied to the output terminal B,
It is configured to be connected to point A. Output terminal B
An NMOS M7 for level shift is connected between the input of NAND1 and the NMOS M3.

Next, the structure of a part of the output circuit will be described with reference to FIG. 2 which is a schematic sectional view. In FIG. 2, on a P-type semiconductor substrate 21, regions of the N-well 22 and N ⁺ diffusion layers 24 and 25 are provided, the N ⁺ diffusion layer 24 and 25, N
The source and drain of the MOSM3 are formed. Also, NMOS M3
Are connected to the power supply voltage VDD. On the N-well 22, P ⁺ diffusion layers 26 and 27 and the N ⁺ diffusion layer 28 is formed, P ⁺ diffusion layers 26 and 27, the drain of PMOSM1, to form a source, P ⁺ diffusion layer 27 to VDD Connected and N ⁺
A diffusion layer 28 exists for fixing the well potential.

Further, on the N well 23, a P + diffusion layer 2 is formed.
9, 2A, 2B, 2C and an N ⁺ diffusion layer 2D are provided, and P ⁺
The diffusion layers 2B and 2C form the source and drain of the PMOS M5, and the P ⁺ diffusion layers 29 and 2A form the source and drain of the PMOS M5. Further, the P ⁺ diffusion layer 2C has a VD together with the N ⁺ diffusion layer 2D.
Connected to D terminal. P ⁺ diffusion layers 2A and 2B are commonly connected and also connected to N ⁺ diffusion layer 28. Furthermore, P ⁺
Diffusion layer 29 is connected to series connection point A. (Note that FIG. 2
Here, the illustration of the NMOS M7 and the NAND 1 is omitted. )

In the configuration described above, the NMOS M3 connected between the series connection point A and the output terminal B operates as a level shifter, and is the same as the conventional one in that the power supply voltage 5V system and the 3V system interface circuit are realized. is there. Here, in the present invention, the potential of the N-well 22 where the PMOS M1 is formed is controlled by the common connection point C between the PMOS M5 and the PMOS M6. That is, in the steady state, the N-well 22 is connected to the PMOS M5.
As a result, the power supply potential VDD is reached and the operation is performed.

Here, the problem of the conventional example, that is, when the output circuit is in the high impedance state, the "V" of the NMOS M3
For example, in the case of “VT = −0.5”, when “5 V” is applied to the output terminal, the potential at point A becomes “3.5 V” as described above. At this time, NAND1
Are both at the high level, the PMOS M5 is turned off and the PMOS M6 is turned on at the same time, and the potential of the N-well 22 becomes the same potential as the series connection point A.

Therefore, the potential difference between the drain 26 of the PMOS M1 (see FIG. 2) and the N well 22 disappears, and the leak current which has been a problem in the conventional example does not occur. At this time, since the series connection point A and the N ⁺ diffusion layer are short-circuited by the PMOS M6, no forward current flows as in the conventional example. Further, in a steady state, the potential of the N-well 22 (see FIG. 2) is
Since the voltage is controlled by M5, the impedance with respect to the VDD terminal can be reduced as compared with the conventional case where the voltage is controlled by an NMOS.

The above-described interface circuit can be applied to a semiconductor integrated device. That is, in the semiconductor integrated device according to the present invention, an N-ur, a P-channel type diffusion layer and an N-channel type diffusion layer are formed on a P-channel type semiconductor substrate, and these N well, P-channel type diffusion layer and N-type diffusion layer are formed. The above-described interface circuit is formed using the channel-type diffusion layer, and a signal having a potential higher than the in-device power supply potential is applied to the output terminal to perform an interface operation.
Therefore, according to such a configuration, signals operating at different voltages can be freely transmitted and received, and the reliability and functionality of the device can be increased.

[0037]

As described above, in the interface circuit according to the present invention, when a higher voltage than the power supply voltage is applied to the output terminal when the output circuit is in the high impedance state, the P-channel type circuit comprising the complementary semiconductor integrated circuit is used. Since the drain diffusion layer of the P-channel transistor forming the output circuit by the transistor and the N-well where the P-channel transistor is formed have the same potential, a leak current can be prevented without flowing a forward current. .

Further, even in the normal state, since the above-mentioned N well potential is supplied to the VDD potential by the P-channel type transistor, it can be connected to the VDD terminal with a lower impedance than in the conventional example connected by the N-channel type transistor. Thus, it is possible to realize an interface circuit that significantly reduces the risk of occurrence of latch-up.

By providing the interface circuit in the device, the reliability of the device is increased, and a semiconductor integrated device with further improved functionality can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of an interface circuit according to the present invention.

FIG. 2 is a fragmentary cross-sectional view showing a partial structure of an output circuit according to an embodiment of the interface circuit according to the present invention;

FIG. 3 is a circuit configuration diagram of an example of a conventional interface circuit.

FIG. 4 is a cross-sectional view showing a partial structure of an output circuit of a conventional interface circuit.

FIG. 5 is a circuit configuration diagram of an example of a second conventional interface circuit.

FIG. 6 is a sectional view showing a partial structure of an output circuit of an interface circuit according to a second conventional example.

[Explanation of symbols]

M1, M5, M6 P-channel MOS transistors M2 to M4, M7 N-channel MOS transistors 21, 41, 61 P-type semiconductor substrate 22, 23 N-wells 24, 25, 28, 2D, 43, 44, 47, 63 to 66,69 N ⁺ diffusion layer 26,27,29,29,2A-2C, 45,46,67,68 P ⁺ diffusion layer

Claims (6)

(57) [Claims] 1. An output circuit comprising a complementary semiconductor integrated circuit, to which power of a first high potential is supplied and for outputting a signal of an internal circuit, and for outputting a signal of this output circuit and for receiving said first high potential An output terminal to which a second higher potential higher than a potential power supply is externally applied, and a predetermined high-potential inserted between the output terminal and the output circuit so that the second high potential is not directly applied to the output circuit. An interface circuit including a level shifter for lowering a voltage to a level, wherein an N-well in which a first P-channel transistor forming the output circuit is formed is connected to the first high-potential power supply in a steady state. When the output circuit is in a high impedance state and a high potential is supplied to the output terminal, there is provided a means for connecting to the same potential as the output point of the output circuit. Interface circuit to be. 2. The level shifter for a level shifter is connected between a series connection point A between a first N-channel transistor and the first P-channel transistor constituting the output circuit and the output terminal. 2. The interface circuit according to claim 1, wherein two N-channel transistors are connected. 3. The second P-well connected to the first high-potential power supply connected in series between the first high-potential power supply and the series connection point A. A channel type transistor and a third connected to the series connection point A.
Is controlled by the potential of the series connection point C between the second P-channel transistor and the second P-channel transistor in a steady state.
3. The interface circuit according to claim 2, wherein the channel type transistor is turned on. 4. The interface circuit according to claim 3, wherein the third P-channel transistor is turned on only when the output circuit is in a high impedance state and the second high potential is applied to the output terminal. An interface circuit, further comprising: a NAND circuit that controls to operate. 5. The method according to claim 1, wherein one of the input terminals of the NAND circuit has a high impedance, and a third N-channel transistor for level shift is interposed between the other input terminal of the NAND circuit and the output terminal. Claim 4
2. The interface circuit according to claim 1. 6. An N-well, a P-channel type diffusion layer and an N-channel type diffusion layer are formed on a P-channel type semiconductor substrate, and these N-well, P-channel type diffusion layer and N-channel type diffusion layer are formed. 6. The semiconductor integrated circuit according to claim 1, wherein a signal having a potential higher than a power supply potential in the device is applied to the output terminal to perform an interface operation. apparatus.