JP3066679B2 - Redundant system switching control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system switching control system in a redundant system for improving reliability.
In a system requiring high reliability, it is general to use a redundant configuration. In such a case, for example, only important devices such as a clock supply unit and a main signal processing unit in a communication system are economically configured as a redundant configuration, and when a failure occurs, the redundant system is switched at a high speed to minimize the propagation of the failure. It is demanded that it be limited to the limit.

[0002]

2. Description of the Related Art A clock supply system in a communication system has, for example, the configuration shown in FIG.
Is a system clock supply unit, 41 is a system clock supply unit, 42-1 to 42-n are devices for performing communication processing by receiving a clock signal, 43 is a system switching control unit, and 44-0 and 44-1. Is a clock generator, 45-0,
45-1 is a gate circuit, 46-1 to 46-n are selectors (SEL), 47 and 48 are clock signal lines, 49 and 50.
Is an alarm signal line, and 51 and 52 are switching control signal lines.

For example, if the 0-system clock supply unit 40 is an active system and the 1-system clock supply unit 41 is a standby system, the system switching control unit 43
1, the gate circuit 45-0 is opened, and the gate circuit 45-0 is opened.
-1 is closed, and each of the devices 42-1 to 42-2 is controlled.
The -n selectors 46-1 to 46-n are controlled to select the clock signal from the 0-system clock supply unit 40 via the switching control signal line 52. Thereby, each of the devices 42-1 to 42-n is connected to the 0-system clock supply unit 4
Communication processing is performed based on the clock signal from 0.

In such a state, when the system switching control unit 43 receives an alarm signal indicating that the clock signal has been cut off from the system 0 clock supply unit 40 via the alarm signal line 49, the switching control unit 43 performs switching control. The gate circuit 45-0 is closed via the signal line 51, and the gate circuit 45-1 is closed.
And the selectors 46-1 to 46-n select the clock signal from the 1-system clock supply unit 41 via the switching control signal line 52.
That is, switching of the redundant system in which the system 0 is the standby system and the system 1 is the active system is performed.

[0005]

In the above-mentioned prior art, the 0-system clock supply unit 40, the 1-system clock supply unit 41 and the other devices 42 are used for the redundant system switching control.
-1 to 42-n, a system switching control unit 43 is required, and an alarm signal line 49,5 is provided between the system switching control unit 43 and each of the devices 42-1 to 42-n.
0 and a switching control signal line 52 must be laid, and a switching control signal line 51 must be laid between the 0-system clock supply unit 40 and the 1-system clock supply unit 41. Therefore, there is a drawback that the system becomes large-sized, and there is a drawback that the number of wirings is increased and the configuration is complicated. An object of the present invention is to provide a simple and economical configuration by omitting a system switching control unit and the like.

[0006]

A redundant configuration switching control system according to the present invention, which will be described with reference to FIG. 1, includes a 0-system apparatus 0 and a 1-system apparatus 1 for one or a plurality of apparatuses 2. And said
Different transmissions from the 0-system device 0 and the 1-system device 1
A signal is supplied to the single or multiple devices 2 via a path.
The single or multiple devices 2 are in front of the 0-system device 0.
The switching control signal of the own system supplied from each of the first system devices 1
Signal from the 0-system device 0 and the 1-system device 1
In the redundant system for selecting any one of the signals from the system, the 0-system device 0 and the 1-system device 1 control the switching of the own system.
Switching settlement control unit 3 and 4 for outputting a signal is provided, this
The switching control signal of the own system is provided between the switching discussion control units 3 and 4.
Interconnected so that it is transferred to the switchover control section of the other system
Then, the switching information control units 3 and 4 transfer from the other system device.
The other system switching control signal and the single or plural devices.
The signal from the 0-system device 0 and the 1-system device in the device 2
Said single or plural indicating the state of each signal from the device 1
Based on the status information transferred from the device 2 of the
Generate a switching control signal and send it to the single or multiple devices 2
It is sent to the system to perform system switching.

[0007]

The redundant system is constituted by the 0-system apparatus 0 and the 1-system apparatus 1. For example, the clock signal CLK0 from the 0-system apparatus 0 and the clock signal CLK1 from the 1-system apparatus 1 are transmitted to each apparatus 2
To the selector 5 of FIG. The selector 5 is controlled via switching control signal lines 6 and 7 from the switching discussion controllers 3 and 4, and transfers state information between the switching discussion controllers 3 and 4. In addition, the switching information controllers 3 and 4 receive status information such as an alarm signal from each device 2 upon detection of a clock signal loss. When such switching alarm control units 3 and 4 receive such an alarm signal, state information is transferred between the switching notification control units 3 and 4 and whether to switch to system 0 or system 1 or to maintain the current state Is determined, the selector 5 is controlled, and system switching is performed.

[0008]

FIG. 2 is an explanatory view of an embodiment of the present invention.
Reference numerals 0 and 11 denote a 0-system clock supply unit and a 1-system clock supply unit, 12-1 to 12-n perform processing in accordance with a clock signal, and 13 and 14 denote a switching information control unit, 1
5-1 to 15-n are selectors (SEL), 16-1 to 1
6-n is a disconnection detection unit, 17-1 to 17-n are flip-flops, 18-1 to 18-n are decoding circuits, 19-0,
19-1 is a clock generator, 20-0 and 20-1 are fault state decode circuits, 21-0 and 21-1 are self-selection request decode circuits, 22 and 23 are clock signal lines, and 24 and 2
5 is a roundabout signal line, 26 and 27 are alarm signal lines, 28 and
29 is a switching control signal line, 30-0 and 30-1 are power-on reset signal lines in the unit, and 31-0 and 31-1 are self-monitoring signal lines.

The 0-system clock supply unit 10 and the 1-system clock supply unit 11 correspond to the redundant system composed of the 0-system device 0 and the 1-system device 1 in FIG.
Numeral 4 corresponds to the switching chat control units 3 and 4 in FIG. The switching indication control units 13 and 14 are provided with a failure state decoding circuit 20.
−0, 20-1 and the self-selection request decoding circuit 21-0,
21-1 and are connected to each other by the consultation signal lines 24 and 25 to transfer state information.

The clock signal from the clock generator 19-0 of the 0-system clock supply unit 10 and the clock signal from the clock generator 19-1 of the 1-system clock supply unit 11 are transmitted via the clock signal lines 22 and 23. Are added to the selectors 15-1 to 15-n of the devices 12-1 to 12-n, and the selectors 15-1 to 15-n are controlled by the output signals of the terminals Q of the flip-flops 17-1 to 17-n. And selectively outputs a clock signal from either one.

The decoding circuits 18-1 to 18-n are composed of AND circuits and inverters, and decode switching control signals from switching indication control units 13 and 14 via switching control signal lines 28 and 29. Flip-flops 17-1 to 17-1
17-n. For example, if the switching control signal from the switching discussion control unit 13 is “1” and the switching control signal from the switching discussion control unit 14 is “0”, the decoding circuit 18-
1 to 18-n to flip-flops 17-1 to 17-n
Is "0" for the set terminal S and "1" for the reset terminal R.
Of the flip-flops 17-1 to 17-n and the selector 1
A control signal of “0” is applied to 5-1 to 15-n, and the selectors 15-1 to 15-n operate in the 1-system clock supply unit 1
1 is selectively output. When a decode output signal of "1" is added to the set terminal S of the flip-flops 17-1 to 17-n and set, a control signal of "1" is sent from the terminal Q to the selectors 15-1 to 15-n. In addition, the clock signal from the 0-system clock supply unit 10 is selectively output.

The disconnection detectors 16-1 to 16-n include a 0-system clock supply unit 10 and a 1-system clock supply unit 1.
1 to monitor the clock signal supplied through the clock signal lines 22 and 23, and when the disconnection is detected, switches the alarm signal through the alarm signal lines 26 and 27.
3 and 14 are added to the failure state decoding circuits 20-0 and 20-1. This failure state decoding circuit 20-
0, 20-1 are provided with self-monitoring signal lines 31-0, 31-1.
, An alarm signal in the own system clock supply unit is added.

FIG. 3 is an explanatory diagram of the control logic of the embodiment of the present invention. FIG. 3 (A) shows the control logic of the switchover control units 13 and 14, * PONR is a power-on reset signal, * DWN
Y is alarm signal due to clock signal cut off of other system, * DW
NM is an alarm signal due to the clock signal cutoff of its own system, * S
ELY is a switching control signal of the other system, and * SELM is a switching control signal of the own system. (B) shows the switching control logic of the clock signal on the device 12-1 to 12-n side, * SEL1 is 1
Switching control signal from the system clock supply unit 11, * S
EL0 indicates a switching control signal from the 0-system clock supply unit 10. Holding the selected system indicates that the current state is maintained, and that the 0 system and 1 system are switched to the 0 system and 1 system, respectively.

The power-on reset signal * RONR in the 0-system clock supply unit 10 and the 1-system clock supply unit 11 is connected to the power-on reset signal line 30-0,
30-1 via the self-selection request decoding circuit 21-0,
20-1 and the power-on reset signal * R
When ONR is at the low level L, the switching control signal * SELM of the high level H is unconditionally transmitted via the switching control signal lines 28 and 29. The power-on reset signal * PONR in each of the devices 12-1 to 12-n is not shown in FIG.

When the power is turned on in the 0-system clock supply unit 10 or the 1-system clock supply unit 11,
The power-on reset signal * PONR changes to low level L, and the self-selection request decoding circuits 21-0 and 21-1 of the switching indication control units 13 and 14 output a high-level H self-system switching control signal * SELM. For example, when power is turned on in the 0-system clock supply unit 10, a high-level H signal is output from the self-selection request decode circuit 21-0 of the switching indication control unit 13, and each device 12 is switched via the switching control signal line 28. Switching control signal * SE to -1 to 12-n
L0 will be added, and the switching and discourse control unit 14 of the first system clock supply unit 11 will be connected via the discourse signal line 24.
Is added as a switching control signal * SELY of another system to the self-selection request decoding circuit 21-1. After the power-on reset, the power-on reset signal * PONR becomes high level H
Becomes Also, the 0-system clock supply unit 10 and the 1-system clock supply unit 11 are packaged and hot-swapping is enabled by selecting the shape of the connector pins. It is also possible to adopt a configuration in which on-reset is performed.

Each of the devices 12-1 to 12-n receives a switch control signal * SEL1 applied via a switch control signal line 29 when the switch control signal * SEL0 of a high level H is applied.
Is high level H, the state immediately before it is held, and if low level L, switching is performed so as to select the clock signal from the first system clock supply unit 11. That is, the decoding circuits 18-1 to 18-n output the switching control signal * SEL0 applied via the switching control signal line 28 to "1",
Switching control signal applied via switching control signal line 29 *
If SEL1 is “1”, the flip-flop 17-1
A signal of "0" is applied to both the set terminal S and the reset terminal R of the flip-flops 17-n.
Since the states of the terminals Q of .about.17-n do not change, the selected states of the selectors 15-1 to 15-n are held. Similarly,
If the switching control signals * SEL0 and * SEL1 are both "0" (low level L), the decoding circuits 18-1 to 18-
Since a signal of "0" is applied from n to the set terminal S and the reset terminal R of the flip-flops 17-1 to 17-n, the state of the flip-flops 17-1 to 17-n does not change.

If the switching control signal * SEL1 applied via the switching control signal line 29 is "0", the decoding circuits 18-1 to 18-n output the flip-flops 17-1 to 17-n.
A signal of "1" is applied to the reset terminal R of 17-n, and the flip-flops 17-1 to 17-n are reset. Therefore, a signal of "0" is supplied from the terminal Q of the flip-flops 17-1 to 17-n to the selectors 15-1 to 15-n.
Therefore, the selectors 15-1 to 15-n select and output the clock signal of the first system clock supply unit 11 which is applied via the clock signal line 23. If the switching control signal * SEL0 is "0" and the switching control signal * SEL1 is "1", the decoding circuits 18-1 to 18-1
The signal "1" is added to the set terminals S of the flip-flops 17-1 to 17-n from 18-n to be set, and the terminal Q becomes "1".

When the terminals Q of the flip-flops 17-1 to 17-n are "0", the selectors 15-1 to 15-n are set to 1
The clock signal of the system clock supply unit 11 is selected and output. In this state, the switching information control unit 13 of the system 0 clock supply unit 10 outputs * PONR
= H, * DWNY = H, * DWNM = H, * SELY =
L, * SELM = H, and the switching information control unit 14 of the first system clock supply unit 11 outputs * PONR = H, *
DWNY = H, * DWNM = H, * SELY = H, * S
ELM = L. 0 system clock supply unit 1
The switching control signal * SELM of 0 is transmitted to the switching control signal * SE of the first system clock supply unit 11 through the communication signal line 24.
LY, and the switching control signal * SELM of the 1-system clock supply unit 11 becomes the switching control signal * SELY of the 0-system clock supply unit 10 via the communication signal line 25.

In this state, the disconnection detectors 16-1 to 16-1
6-n, when the interruption of the clock signal applied via the clock signal line 22 is detected, an alarm signal is transmitted via the alarm signal line 26. 0 system clock supply unit 1
0, this alarm signal is used as the alarm signal * DWNM for detecting the clock signal disconnection of the own system, and the failure state decoding circuit 2
0-2, and the 1-system clock supply unit 11 adds it to the fault state decoding circuit 20-1 as an alarm signal * DWNY for detecting the clock signal cutoff of the other system. Therefore, the 0-system clock supply unit 10
Then, * PONR = H, * DWNY = H, * DWNM =
L, * SELY = L, so that * SELM = H. In the first system clock supply unit 11, * SELM = H
PONR = H, * DWNY = L, * DWNM = H, * S
Since ELY = H, * SELM = L. Therefore, in each of the devices 12-1 to 12-n, *
PONR = H, * SEL1 = L, * SEL0 = H, and the state of switching to the 1 system is continued. That is, since it is the case of the interruption of the unselected clock signal, the previous state is maintained.

When the disconnection detectors 16-1 to 16-n detect the disconnection of the clock signal applied via the clock signal line 23, the 0-system clock supply unit 10 outputs * PONR = H, * DWNY = L, * DWNM =
H, * SELY = L, so * SELM = L. In the first system clock supply unit 11, * SELM = L
PONR = H, * DWNY = H, * DWNM = L, * S
Since ELY = H, * SELM = L. However, since the switching control signal * SELM = L from the switching consultation control unit 13 of the 0-system clock supply unit 10, the consultation signal line 2
4 and transferred to the switching message control unit 14 of the first system clock supply unit 11, where * PONR = H, * DWNY =
H, * DWNM = L, * SELY = L, whereby * SELM = H. The switching control signal * SELM = H is also transferred to the switching discussion control unit 13 of the 0-system clock supply unit 10 via the discussion signal line 25.
Therefore, in each of the devices 12-1 to 12-n, * PO
NR = H, * SEL1 = H, * SEL0 = L, and 0
It will be switched to the system.

When the disconnection detecting sections 16-1 to 16-n detect the disconnection of the clock signal applied via the clock signal lines 22 and 23, * DWNY = L, * DWNM =
L, in which case * SELM = ＄. That is,
In order to select the system 0, the system 0 clock supply unit 10
* SELM = L, 1-system clock supply unit 1
In the case of 1, * SELM = H. This is to prevent the system switching control in each of the devices 12-1 to 12-n from becoming unstable due to the interruption of the clock signal between the system 0 and the system 1. The alarm signal in the 0-system clock supply unit 10 and the alarm signal in the 1-system clock supply unit 11 are the same as those of the own system clock signal disconnection detection signal.
0-0, 20-1 and the above-mentioned alarm signal *
The determination according to the logic by the DWNM is performed.

As described above, the switching information control units 13 and 14 are provided according to the control logic of FIG. 3A, and the status information is transferred to each other to determine the status of the system switching and to determine the system switching. A switching control signal can be output. In each of the devices 12-1 to 12-n, a simple decode circuit 18-1 to 18-n according to the control logic shown in FIG.
The switching between the 0-system and the 1-system can be performed simply by providing. Therefore, the switching message control units 13 and 14 and the decoding circuits 18-1 to 18-n can adopt various logical configurations without being limited to the above-described embodiment, and can operate at high speed. System switching can be performed.

[0023]

As described above, according to the present invention, the switching communication control unit 3 and the 0-system device 0 such as the 0-system clock supply unit 10 and the 1-system device 1 such as the 1-system clock supply unit 11 are provided. 4 to transfer state information such as a switching control state to each other.
A system switching control signal is transmitted to the other apparatus 2 based on status information such as an alarm signal from the other apparatus 2 connected to the system apparatus 0 and the system 1 apparatus, as in the conventional example. No special system switching control unit is required, and 0
There is an advantage that a simple and economical configuration can be achieved because only a small number of signal lines need to be provided between the system devices 0 and 1.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is a control logic explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 0 0-system device 1 1-system device 2 device 3, 4 switching consultation control unit 5 selector 6, 7 switching control signal line

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Yamazaki 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Noriaki Ouchi 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 1/22 G06F 1/04 303 G06F 11/20 310 H04L 7/00 H04L 12/28

Claims (1)

(57) [Claims] 1. A zero-system device comprising a zero- system device (0) and a one-system device (1) for a single or a plurality of devices (2).
(0) and different transmissions from the first system device (1)
A signal is supplied to the single or multiple devices (2) via a path
And the single device or the plurality of devices (2) are
(0) and self-supply supplied from each of the first system devices (1).
A signal from the 0-system device (0) is transmitted by the system switching control signal.
Signal and any one of the signals from the first system device (1). In the redundant system, the zero system device (0) and the first system device (1) are provided with the own device.
Switching information control unit (3, 4) that outputs a system switching control signal
Is provided between the switching and discussion control units (3, 4).
The system switching control signal is transferred to the switching
Are connected to each other so that the switching
4) is a switching control signal of the other system transferred from the other system device
And the 0-system device in the single or multiple devices (2)
Signal from the device (0) and the signal from the first system device (1)
The single or multiple devices (2) indicating each state
Switching control signal of the own system based on the status information transferred from the
Generating a signal for said single or multiple devices (2)
A redundancy switching control method characterized by transmitting .