JP3066864B2 - Dynamic random access memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A DRAM device, in particular, a row access selection signal (or row address strobe signal) ▼ and a column access selection signal (or column address strobe signal) ▼ from an external device at a predetermined timing. A technique for controlling the refresh in the DRAM device based on the applied signal, the purpose of which is to simplify the refresh control from the outside when the memory is not accessed for a long time, and to control the column access selection signal and the row from the outside. A detection signal of a predetermined level is output when each of the access selection signals is input at a predetermined timing. Thereafter, in response to a refresh request signal generated internally, an internal row access selection signal (or an internal row address strobe signal) and an internal row access strobe signal are output. Column access selection signal (or internal column add A control circuit for outputting a reset strobe signal), a memory cell array, and the memory cell array in response to the internal row access selection signal and the internal column access selection signal.
A peripheral circuit that accesses the array, a circuit that oscillates pulses at a predetermined cycle, and counts the oscillated pulses in response to the detection signal. The first signal is output when one predetermined time (time until the first refresh is performed) has elapsed, and then the second predetermined time (refresh cycle) until the detection signal deviates from the predetermined level A circuit for outputting a second signal every time the detection signal is at the predetermined level, and a circuit for generating the refresh request signal in response to the first or second signal. .

[Industrial applications]

The present invention relates to a dynamic random access memory device (hereinafter, referred to as a DRAM device), and more particularly, to externally applying a row access selection signal ▼ and a column access selection signal ▼ at a predetermined timing (for example, ▲).
▼ before ▲ ▼, so-called CBR method), and a technique for controlling refresh in the DRAM device based on the applied voltage.

[Conventional technology and problems to be solved by the invention]

In the DRAM device, it is necessary to refresh the data at least once every predetermined time in order to retain the data written in the memory cell regardless of whether or not the memory is accessed.

When performing refresh using the CBR method, first, the level of the row-active column access selection signal ▲ ▼ is lowered at a predetermined timing to enable peripheral circuits such as the column decoder, and then the row-active row access selection signal By lowering the level of ▲ ▼, the peripheral circuits such as the row decoder are enabled, whereby the cells in the cell array are sequentially refreshed on a word line basis.
▼ and ▲ ▼ levels are set up. That is, the refresh control is performed by lowering the levels of the signals ▼ and ▼ at a predetermined time by the CBR method and raising the levels of the signals after a certain time.

Such refresh control is naturally necessary even when the memory is not accessed for a long time, and in that case,
A signal from the outside at a predetermined timing every fixed time
It is necessary to lower or raise the levels of ▼ and ▲ ▼. This means that refresh control becomes complicated when viewed from a device that supplies the signal, for example, a CPU, and thus the configuration of the device is complicated, which is preferable. Absent.

The present invention has been made in view of the above-described problems in the related art, and is capable of simplifying an external refresh control when a memory is not accessed for a long time.
It aims to provide AM equipment.

[Means for solving the problem]

The above-mentioned problem in the prior art is that once a column access selection signal ▼ and a row access selection signal ▼ are applied at a predetermined timing, a control signal based on the timing is only held at a predetermined level, so that the internal The problem is solved by devising the circuit configuration so that the refresh (self-refresh) is performed automatically.

Accordingly, in the DRAM device according to the present invention, as shown in the block diagram of FIG. 1 (a), a column access selection signal ▼ and a row access selection signal ▼ at a predetermined level are externally provided at predetermined timings ( CB
R), a detection signal C ₀ of a predetermined level is output, and then an internally generated refresh request signal C ₃
In response to the internal row access selection signal ▲ of a predetermined level.
▼ and internal column access selection signal ▲
▼ output control circuit 1 and memory cell array 2
A peripheral circuit 3 for accessing the memory cell array in response to the internal row access selection signal and the internal column access selection signal; a circuit 4 for oscillating a pulse P at a predetermined cycle; Counting the number of pulses in response to the detection signal, outputting a _first signal C ₁ at a time when a _first predetermined time t _{1 has} elapsed from the time when the detection signal has reached the predetermined level, and thereafter, the detection signal A circuit 5 for outputting a _second signal C2 every _second predetermined time t2 until the signal deviates from the predetermined level, and the first or second signal is output when the detection signal is at the predetermined level. And a circuit 6 for generating the refresh request signal in response.

Here, the first predetermined time is set to a time from when the detection signal reaches the predetermined level to when the first refresh is performed, and the second predetermined time is set to a refreshing cycle.

According to a preferred aspect of the present invention, the external row access selection signal and the external column access selection signal are the same as the CBR.
, And the self-refresh operation is repeated in response to the internal row access selection signal while the external row access selection signal maintains the active state.
An AM device, wherein when the external row access selection signal transitions from an active state to an inactive state, if the internal row access selection signal is in an active state, the internal row access selection signal is deactivated from an active state. A DRAM device characterized in that the self-refresh operation is canceled in response to a transition to a state.

(Operation)

According to the above-described configuration, as shown in the timing chart of FIG.
When the row access selection signal ▼ changes to a predetermined level (“L” level in the illustrated example) at a predetermined timing, a detection signal of a predetermined level (“H” level in the illustrated example)
C ₀ is output, and the time measurement circuit 5 responds to this detection signal.
Starts counting the pulses of the oscillation circuit 4 for a first predetermined time t ₁
And outputs a first signal C ₁ has passed since the beginning. Refresh request signal generating circuit 6 outputs a refresh request signal C ₃ in response to the first signal C ₁ (1 st refresh). After this first refreshing is performed, the detection signal C ₀ is "H" the second signal C ₂ to the second predetermined time t ₂ as long as it is in level is outputted, thereby the refresh request signal C ₃ Is output.

That is, the column access selection signal ▲ ▼
And after temporarily applying a row access select signal ▲ ▼ at a predetermined timing, and holds the detection signal C ₀ which is based on the timing to a predetermined level, the refresh request signal
Controls the internal row access select signal ▲ ▼ and internal column access selection signal ▲ ▼ by C _3, whereby the column access select signal externally ▲ ▼
And the same state as when the row access selection signal ▲ ▼ is input at a predetermined timing internally,
Self refresh is performed.

Therefore, if the memory is not accessed for a long time, there is no need to externally apply a signal for refreshing every fixed time, so that external refresh control is simplified.

If the internal row access selection signal is in the active state at the time when the external row access selection signal transitions from the active state to the inactive state, the internal row access selection signal responds to the transition from the active state to the inactive state. In the case where the self-refresh operation is cancelled, the inconvenience that the operation is interrupted during the self-refresh operation and the information stored in the memory cell is destroyed can be solved.

The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

〔Example〕

FIG. 2 is a block diagram showing a configuration of a DRAM device as one embodiment of the present invention.

In FIG. 1, reference numeral 10 denotes a normal memory cell array in which a dynamic memory cell, for example, a one-transistor one-capacitor cell, is disposed at each intersection of a plurality of word lines and bit lines. An address buffer for buffering an external address signal ADD. Reference numeral 12 designates an output address from the address buffer 11 or an output address from the refresh address counter 20 in response to a CBR detection signal φ ₈ (described later). 13 is a column decoder for decoding a column address inputted via the address buffer 11 in response to an internal column access selection signal φ ₇ (described later), and 14 is an address selector. A pre-row decoder that decodes a row address input through 12 in advance, 15 is a pre-row decoder A row decoder that decodes a row address based on decoding in response to an internal row access selection signal φ ₆ (described later); 16 is a sense amplifier that operates in response to the internal row access selection signal φ ₆ and an input / output ( I / 0) gate.

Reference numeral 21 denotes a substrate potential generating circuit, which is usually provided in a DRAM for biasing the substrate to a predetermined potential, and generates a pulse signal at a predetermined cycle (output signal φ
₁ ). 22 shows a waveform shaping circuit for shaping the pulse signal phi ₁ of the waveform in the short form and its output signal phi _2.

23 shows the counter, (in this example "H" level) CBR detection signal phi ₈ predetermined levels becomes an enable state when it is in, a pulse signal inputted through the waveform shaping circuit phi
Divide ₂ by _two . The counter 23 functions as a timer, and when a predetermined time determined by the number of bits of the counter elapses, an “L” level signal φ ₃ (lower bit counter output signal) or an “L” level signal φ ₄ (upper bit) Bit counter output signal). The predetermined time in this case is, for upper bit counter output signal phi _4, is set to a time from when the CBR detection signal phi ₈ is changed to the "H" level until the first refresh, whereas the lower the bit counter output signal phi _3, is set to a period to be refreshed.

Switching of the output of the upper bit counter output signal phi ₄ and a lower bit counter output signal phi _3, the AND gate 24
Performed by the output signal phi _12. This And Gate 24
Are the CBR detection signal φ ₈ and the counter output selection signal φ ₉
The signal φ ₁₂ (upper bit counter enable signal) is output in response to the signal φ.
Upper bit counter output signal φ when ₁₂ is at “H” level
₄ is outputted, whereas, CBR detection signal phi ₈ is "H" and the counter output selection signal phi ₉ at the level "L" so that the lower-bit counter output signal phi ₃ is output when the level.

25 is a refresh request signal generating circuit, when the CBR detection signal phi ₈ is at the "H" level, based on the pulse signal phi ₂ to be inputted via the waveform shaping circuit, and High order bits
Counter and to output the refresh request signal phi ₁₁ in response to an output signal phi ₄ or lower bit counter output signal phi _3. The above-mentioned counter output selection signal φ ₉ becomes “H” level when the CBR detection signal φ ₈ changes to “L” level, and the counter 23 outputs an “L” level upper bit counter output signal φ _4. It becomes “L” level when it is done.

Reference numeral 26 denotes an arbiter, which is a low-active row access selection signal ▼, a refresh request signal φ _11, and a low-active internal row access selection signal φ output from an internal ▼, ▼ generation circuit 27 (described later). in response to the ₆ outputs an arbiter output signal phi _5. The main function of this arbiter 26 is to eliminate the possibility of a malfunction that may occur when resetting the self-refresh operation (specifically, when the row access selection signal ▲ is raised to “H” level). have.

The internal ▲ ▼, ▲ ▼ generation circuit 27 includes a row access selection signal ▲ ▼, a low active column access selection signal ▲ ▼, and a refresh request signal φ ₁₁
, An internal row access selection signal φ ₆ and a column access selection signal φ _{7 which are} active low in response to the arbiter output signal φ ₅ and the active timeout signal φ _10.
Has the function of generating

The internal row access selection signal φ ₆ and the internal column access selection signal φ ₇ are initially set to “L” when the “L” level column access selection signal ▼ and the row access selection signal ▼ are input by the CBR method. Level, and then the first refresh request signal φ ₁₁ (“H”
Becomes "H" level when the level) is outputted, when the refresh request signal phi ₁₁ becomes "L" level "L"
Level, and further, "L" level in response to an active time-out signal phi ₁₀ of which is controlled so that the "H" level. That is, the pulse width of the internal row access select signal phi ₆ is defined by the active time-out signal phi _10. This active timeout signal φ ₁₀
Is a control signal that is input when the operation of the sense amplifier is completed. More specifically, the control signal responds when the voltage applied to the sense amplifier changes to “H” level or “L” level. This is the signal that is output.

When the first refresh is completed, the subsequent internal row access select signal phi ₆ and internal column access selection signal phi _7, in response to the falling edge of the refresh request signal phi ₁₁ becomes "L" level, the active time-out signal in response to the falling edge of phi ₁₀ becomes "H" level. This change is automatically repeated until the row access selection signal ▼ changes to “H” level.

That is, the column access selection signal ▲ ▼
And wax the access selection signal ▲ ▼ is once entered the CBR method, thereafter the internal row access select signal based on the refresh request signal phi ₁₁ in an internal memory phi
₆ and the internal column access selection signal φ ₇ , whereby a column access selection signal
The same state as when ▼ and the row access selection signal ▲ ▼ are input by the CBR method is automatically created, and the self refresh is performed.

Finally, reference numeral 28 denotes a mode control circuit, which responds to the row access selection signal ▼, the internal row access selection signal φ ₆ and the internal column access selection signal φ ₇ , and outputs signals φ ₆ and φ ₇ , Access selection signal ▲
▼ and column access selection signal ▲ ▼ are CBR
And detecting a change in the "L" level at the timing of and to output a CBR detection signal phi ₈ of the aforementioned "H" level.

Next, a specific circuit configuration of a main part in FIG. 2 will be described with reference to FIGS.

FIG. 3 shows a configuration example of the refresh request signal generation circuit 25. In the figure, 33 and 35 each represent 2
Reference numeral 36 denotes a flip-flop comprising two NOR gates.

This refresh request signal generation circuit
A NOR gate 31 responsive to the output signal of the counter output signal phi ₃ and the flip-flop 35, a NOR gate 32 responsive to the output signal and the upper bit counter output signal phi ₄ of the NOR gate 31, the output signal and the CBR detection of the NOR gate 32 Signal φ
A flip-flop 33 responsive to _8, a NAND gate 34 responsive to the output signal and the NOR gate 2 of the output signal of the flip-flop 33, a flip-flop 35 responsive to the output signal and the CBR detection signal phi ₈ of the NAND gate 34, waveform a flip-flop 36 responsive to the output signal of the output signal phi ₂ and the NAND gate 34 of the shaping circuit, a NAND gate 37 responsive to the output signal and the CBR detection signal phi ₈ of the flip-flop 35,
A NOR gate 38 which outputs a refresh request signal phi ₁₁ in response to the output signals of the NAND gate 34 of flip-flop 36, an inverter 39 for outputting a counter output selection signal phi ₉ inverts the output signal of the NAND gate 37 It is configured.

FIG. 4 shows an example of the configuration of the arbiter 26. In the figure, reference numeral 44 denotes a flip-flop composed of two NAND gates.

The arbiter includes an inverter 41 responding to a row access select signal ▲ ▼, NAND gate 42 responsive to the output signal and the refresh request signal phi ₁₁ of the inverter 41
And a NAND gate 43 responding to a row access selection signal ▲ ▼ and an internal row access selection signal φ ₆ , and a flip-flop 44 outputting an arbiter output signal φ ₅ in response to the output signals of the NAND gates 42 and 43. ing.

FIG. 5 shows a configuration example of the internal ▼ and ▼ generation circuits 27. In the figure, reference numeral 52 denotes a flip-flop including two NAND gates.

The internal ▲ ▼, ▲ ▼ generating circuit includes an inverter 51 which responds to an active time-out signal phi ₁₀
When NAND gate that responds with flip-flop 52 responsive to the output signal and the refresh request signal phi ₁₁ of the inverter 51, an inverter 53 in response to the refresh request signal phi _11, the output signals of the inverter 51 of flip-flop 52 and 54, a NAND gate 55 responsive to the output signal of the output signal and the inverter 53 of the NAND gate 54, a NOR gate 56 responsive to the output signal and the arbiter output signal phi ₅ of the NAND gate 55, responsive to the output signal of the NOR gate 56 An inverter 57, and a NAND gate 58R responsive to an output signal of the inverter 57 and a row access selection signal ▲ ▼
When an inverter 59R to output the internal row access select signal phi ₆ inverts the output signal of the NAND gate 58R,
Inverter 57 output signal and column access selection signal ▲
The NAND gate 58C responding to ▼ and the NAND gate 5
And an inverter 59C to output the internal column access selection signal phi ₇ inverts the output signal of 8C.

FIG. 6 shows a configuration example of the mode control circuit 28.
In the figure, reference numeral 68 denotes a flip-flop including two NAND gates.

This mode control circuit controls the internal row access selection signal φ
_6. A delay circuit 64 for delaying and transmitting the change of ₆ by a predetermined time
When, a NOR gate 65 responsive to the output signal and the internal column access selection signal phi ₇ of the delay circuit 64, an inverter 66 responsive to the output signal of the NOR gate 65, an inverter 67 responding to a row access select signal ▲ ▼, and a flip-flop 68 for outputting a CBR detection signal phi ₈ in response to the output signal of the inverter 66 and 67. The delay circuit 64 includes an inverter 61 responsive to an input signal and a resistor
A delay circuit composed of an integrating circuit composed of 62 and a MOS capacitor 63 has a configuration in which three stages are connected in series.

Next, the self-drive of the DRAM device shown in FIGS.
The refresh operation will be described with reference to the operation timing chart of FIG.

When column access selection signal ▲ ▼ and row access select signal ▲ ▼ changes to "L" level at the timing of the CBR, CBR detection signal phi ₈ becomes "H" level,
The counter 23 is enabled both in the upper and lower parts. The counter 23 receives the pulse signal φ via the waveform shaping circuit 22.
₂ is supplied, and the timer operation of the waiting time until the self-refresh mode (the mode in which the self-refresh operation is performed) is started.

Since when the timer operation is started upper bit counter enable signal phi ₁₂ is "H" level, the upper bit counter output signal phi ₄ of the counter 23
Becomes effective. Time of the upper-bit counter output signal phi ₄ is "L" level falls, i.e. the first refresh request signal phi ₁₁ is output when the above-described wait time has ended. While inside the active state at this time, the refresh request signal phi ₁₁ internal simultaneously become "H" level row access select signal phi ₆ is once standby state rises to "H" level.

Then, internal row access select signal phi ₆ when the refresh request signal phi ₁₁ is "L" stand lowered to the level falls to "L" level. In this case, the mode control circuit 28 is also internal column access selection signal phi ₇ to determine that the CBR mode "L" to the level falls. Active Timeout signal phi _10, the internal row access select signal phi ₆ becomes "H" level when after the falls to "L" level. The signal phi ₁₀ when the sense amplifier operation is completed becomes the "L" level, internal row access select signal phi ₆ and internal column access selection signal phi ₇ in response to the falling edge
Goes to the “H” level and enters the standby state.

Waits in this state until the next refresh request signal phi ₁₁ is output, when the signal phi ₁₁ is "L" dropped to the level falling, the internal row access select signal as described above phi ₆
And internally into the CBR mode the level of the internal column access selection signal phi ₇ controlled manner. Such operation, that refresh, row access select signal ▲ ▼ is until rises to "H" level, is repeated for each falling edge of the refresh request signal phi _11.

Next, the self-drive of the DRAM device shown in FIGS.
The refresh / reset operation will be described with reference to the operation timing charts of FIGS.

FIG. 8 shows a timing waveform when the row access selection signal ▼ is raised to “H” level during the execution of the self refresh operation.

Since in this case is in the middle of the CBR mode, when the from the time when the row access select signal ▲ ▼ becomes "H" level the mode ends, that is, an active time-out signal phi ₁₀ becomes "L" level the internal row access select signal phi ₆ to the time after kept at "L" level enters the normal standby mode. Note that the refresh request signal φ
_If the falling point of ₁₁ coincides with the rising point of the row access select signal ▲ ▼, a malfunction may occur. Therefore, as described above, the arbiter 26 enters the normal standby mode or enters the internal CBR mode. To decide.

FIG. 9 shows a timing waveform when the row access selection signal ▼ rises to “H” level when the self refresh operation is not performed.

In this case, since the CBR mode is not in progress, the normal standby mode can be entered immediately when the row access selection signal ▼ rises to the “H” level.

〔The invention's effect〕

As described above, according to the DRAM device of the present invention, if the memory is not accessed for a long time, it is not necessary to apply a signal for refreshing every fixed time from the outside each time. Refresh control can be simplified. Further, since the internal refresh cycle is relatively long on the order of μsec, the average current consumption is small, and battery backup can be performed with a relatively simple configuration.

[Brief description of the drawings]

1A and 1B are diagrams showing the principle of a DRAM device according to the present invention, wherein FIG. 1A is a block diagram, FIG. 1B is a timing diagram conceptually showing the operation, and FIG. FIG. 3 is a block diagram showing a configuration of one embodiment of the present invention, FIG. 3 is a circuit diagram showing one configuration example of a refresh request signal generation circuit in FIG. 2, and FIG. 4 is a configuration example of an arbiter in FIG. FIG. 5 is a circuit diagram showing a configuration example of the internal 内部 and ▼ generation circuits in FIG. 2, FIG. 6 is a circuit diagram showing a configuration example of the mode control circuit in FIG. FIG. 7 is an operation timing chart for explaining a self-refresh operation by the device of FIG. 2, FIG. 8 is an operation timing chart for explaining an example of a self-refresh reset operation by the device of FIG. 2, and FIG. Is a self-refresh Timing diagram for explaining another example of the setting operation, it is. (Explanation of symbols) 1 ... control circuit, 2 ... memory cell array, 3 ... peripheral circuit, 4 ... oscillation circuit, 5 ... time measurement circuit, 6 ... refresh request signal generation circuit, ▲ ▼ …… Row access selection signal, ▲ ▼… Column access selection signal, ▲ ▼… Internal row access selection signal, ▲ ▼… Internal column access selection signal, C ₀ …… CBR detection signal, C ₁ , C ₂ … … Output signal of the time measurement circuit, C ₃ … Refresh request signal, P… Output pulse of the oscillation circuit, t ₁ , t ₂ … Predetermined time.

Continuation of the front page (72) Inventor Takaaki Koyama 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (56) References JP-A-61-57097 (JP, A) (JP, A)

Claims (1)

(57) [Claims] An external row address strobe signal and an external column address strobe signal are CBR (▲ ▼ be
Fore ▲ ▼), the self-refresh mode is entered while the external row address strobe signal is active while the external row address strobe signal is active, and a dynamic random mode that repeats the self-refresh operation in response to the internal row address strobe signal An access memory device, wherein the internal row address strobe signal is in an active state when the internal row address strobe signal is in an active state when the external row address strobe signal transitions from an active state to an inactive state; And an arbiter for canceling the self-refresh mode after transitioning from the active state to the inactive state.
Access memory device.