JP3067329B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to one MOS transistor and one
Dynamic random access memory (DRAM) having a memory cell composed of two stacked capacitors
And a method of manufacturing the same.

[0002]

2. Description of the Related Art A DRAM having a memory cell comprising one MOS transistor and one capacitor has been developed under the proposition that the occupied area of the memory cell is reduced and the capacitance value of the capacitor is increased as much as possible. I've been. The area occupied by the memory cell has been mainly realized by miniaturization of the MOS transistor, but the area occupied by the capacitor has been reduced accordingly. In order to obtain a large capacitance value while reducing the occupied area, the capacitor has been devised into a planar type, a trench type, or a stacked type with a vertical structure.

A DRAM having a stacked capacitor
, The MOS transistor comprises a gate insulating film, a gate electrode also serving as a word line, a node diffusion layer, and a bit diffusion layer, and the capacitor has a node electrode connected to the node diffusion layer via a node contact hole, a capacitor insulating film, And a cell plate electrode. One way to increase the capacitance value in this DRAM is to increase the area of opposition between the node electrode and the cell plate electrode.
This is mainly achieved by increasing the surface area of the node electrode. This method is described in, for example, I.E.D.M., Technical Digest, 592-595 in 1988 by T. EMA.
Page (IEDM Tech. Dig., 1988, p.
pp. 592-595), a fin structure node electrode is reported. This report proposes a structure in which a bit line is formed above a stacked capacitor and a structure in which a stacked capacitor is formed above a bit line.
Taking the former structure as an example, a method of forming a memory cell of a DRAM having a node electrode of a fin structure will be described with reference to FIGS.
This will be described with reference to FIG.

First, on the surface of a p-type silicon substrate 201,
A field oxide film 202 is formed, and a gate oxide film 202 is formed.
A MOS transistor including a, a gate electrode 203 also serving as a word line, an n-type node diffusion layer 204a, and an n-type bit diffusion layer 204b is formed. A first interlayer insulating film 205 is deposited on the entire surface. At least the surface of the interlayer insulating film 205 is formed of a silicon nitride film. A silicon oxide film 227, a first n-type polycrystalline silicon film 213, and a silicon oxide film 228 are sequentially formed (FIG. 11A).

Next, a photoresist film 218 having an opening at a position where a node contact hole is to be formed is formed, and a silicon oxide film 228, a polycrystalline silicon film 213, a silicon oxide film 227, and an interlayer insulating film 215 are sequentially etched. Then, a node contact hole 206a reaching the node diffusion layer 204a is opened. By this etching, the silicon oxide film 228, the polycrystalline silicon film 213, and the silicon oxide film 227 become a silicon oxide film 228a, a polycrystalline silicon film 213a, and a silicon oxide film 227a, respectively (FIG. 11B).

Next, the photoresist film 218 is removed,
A second n-type polycrystalline silicon film is formed on the entire surface. A photoresist film 219 is formed in a region where a node electrode is to be formed, and RIE using the photoresist film 219 as a mask is performed.
The second n-type polycrystalline silicon film, the silicon oxide film 228a, the polycrystalline silicon film 213a, and the silicon oxide film 227a are sequentially etched by anisotropic etching such as a method. By this etching, the second n-type polycrystalline silicon film, silicon oxide film 228a, polycrystalline silicon film 21
3a and the silicon oxide film 227a become a polycrystalline silicon film 223a, a silicon oxide film 228b, a polycrystalline silicon film 213b, and a silicon oxide film 227b, respectively [FIG.
1 (c)].

Next, after removing the photoresist film 219, the silicon oxide film 228b and the polycrystalline silicon film 21 sandwiched between the polycrystalline silicon films 223a and 213b are etched by hydrofluoric acid based wet etching.
Silicon film 2 sandwiched between 3b and interlayer insulating film 205
27b is removed. As a result, a fin-structured node electrode 217 composed of the n-type polycrystalline silicon film 223a and the n-type polycrystalline silicon film 213b is formed.
[FIG. 12 (a)].

Next, a capacitance insulating film 207 is deposited on the entire surface. Forming a third n-type polycrystalline silicon film on all surfaces;
This third n-type polycrystalline silicon film is etched to form a cell plate electrode 208. Using the cell plate electrode 208 as a mask, the capacitor insulating film 207 is removed by etching to form a stacked capacitor. Next, a second interlayer insulating film 209 is deposited on the entire surface, and the interlayer insulating films 209 and 205 on the bit diffusion layer 204b are sequentially etched to open a bit contact hole 206b. Next, a bit line 210 is formed to complete the DRAM [FIG. 12 (b)].

[0009]

The surface area of the node electrode 217 having the fin structure shown in FIG. 12A is sufficiently large. However, in the above-described method, two photolithography steps are required to form the node electrode 217, and the formation step is long and complicated. Further, in realizing this structure, at the stage where the silicon oxide films 227b and 228b sandwiched between the polycrystalline silicon films are removed by etching, the mechanical strength of the node electrode 217 is reduced, and a process such as cleaning becomes extremely difficult. .

[0010]

According to the present invention, there is provided a dynamic random access memory having a stacked capacitor according to the present invention, wherein the stacked capacitor comprises a stacked film in which first conductive films and second conductive films are alternately stacked. And a first electrode on the side surface of the laminated film.
The end of the conductive film is located at a position depressed from the end of the second conductive film.

The first conductive film is preferably an n-type polycrystalline silicon film. This second conductor film is preferably an n-type polycrystalline silicon film containing oxygen.

The method for manufacturing a semiconductor memory device according to the present invention
In a method of manufacturing a node electrode of a dynamic random access memory comprising one MOS transistor and one stacked capacitor, a gate electrode serving also as a word line and an n-type node diffusion layer are formed on a p-type silicon substrate surface. Forming a MOS transistor composed of an N-type bit diffusion layer and an n-type bit diffusion layer, depositing an interlayer insulation film over the entire surface, and opening a node contact hole reaching the node diffusion layer in the interlayer insulation film; Forming a stacked film by alternately depositing a second conductive film and a second conductive film; forming a photoresist film in a region where a node electrode is to be formed; A step of performing isotropic etching and a step of performing isotropic etching on at least an exposed surface of the laminated film by the anisotropic etching.

When the first conductive film is made of an n-type polycrystalline silicon film and the second conductive film is made of an n-type polycrystalline silicon film containing oxygen, the step of forming the laminated film is as follows. ,
Preferably, the non-doped polycrystalline silicon film is alternately deposited and the oxygen-containing non-doped polycrystalline silicon film is formed on the surface of the non-doped polycrystalline silicon film by exposing the non-doped polycrystalline silicon film to an oxygen atmosphere. Forming a first stacked film composed of a polycrystalline silicon film and a non-doped polycrystalline silicon film containing oxygen, and diffusing phosphorus into the first stacked film;
Consists of Another method of forming this laminated film is preferably
An n-type polycrystalline silicon film is deposited by a CVD method using a silane-based gas containing phosphine, and the surface of the n-type polycrystalline silicon film contains oxygen by exposing the n-type polycrystalline silicon film to an oxygen atmosphere. It comprises a step of alternately forming n-type polycrystalline silicon films and a step of performing heat treatment in an inert atmosphere.

[0014]

Preferably, the isotropic etching is dry etching using a gas containing at least sulfur hexafluoride gas.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2 which are schematic cross-sectional views in the order of steps for explaining a first embodiment of the present invention in accordance with a method of manufacturing the same, a semiconductor memory device of the present invention firstly comprises p-type silicon. By forming a field oxide film 102 on the surface of the substrate 101, an active region and an element isolation region are defined. After forming the gate oxide film 102a on the active region, a gate electrode 103 also serving as a word line is formed. Using the gate electrode 103 on the active region as a mask, an n-type node diffusion layer 104a and a bit diffusion layer 104b are formed on the surface of the active region, and the formation of the MOS transistor of the DRAM is completed.
A first interlayer insulating film 105 made of, for example, a silicon oxide film having a thickness of about 300 nm is formed on the entire surface. Interlayer insulating film 10
5 does not need to have at least its surface made of a silicon nitride film as in the conventional example. Next, the node diffusion layer 10
By etching the interlayer insulating film 105 on 4a and opening the node contact hole 106, the structure shown in FIG. 1A is obtained.

Next, 500 ° C. to 6 ° C. in an LPCVD apparatus.
By thermal decomposition of silane (SiH ₄ ) in a temperature range of 00 ° C., a non-doped polycrystalline silicon film 111 having a thickness of, for example, about 150 nm is deposited. Subsequently, oxygen (O
₂ ) is exposed to an argon atmosphere containing 0.2% to 5%, thereby forming a non-doped polycrystalline silicon film 112 containing oxygen on the surface of the polycrystalline silicon film 111. By repeating the same operation two more times, the non-doped polycrystalline silicon film 121, the non-doped polycrystalline silicon film 122 containing oxygen, the non-doped polycrystalline silicon film 131,
A non-doped polycrystalline silicon film 132 containing oxygen is sequentially formed to form a laminated polycrystalline silicon film, and the structure shown in FIG. 1B is obtained.

Here, the flow rates of the silane and the oxygen diluted with argon are periodically changed, for example, as shown in FIG. Non-doped polycrystalline silicon films 111, 121, 13
The thickness of the non-doped polycrystalline silicon films 112, 122, 132 containing oxygen formed on the surface of
The thickness is determined by the temperature, pressure, partial pressure of oxygen, time and the like in the PCVD apparatus, and is considered to be a film thickness corresponding to one to several atomic layers of a silicon layer. At this time, it is considered that the bond between oxygen and silicon should be completely silicon dioxide (SiO2 ₂ ).

Next, it is taken out of the LPCVD apparatus and
The non-doped polycrystalline silicon films 111, 121 and 131 and the non-doped polycrystalline silicon films 112, 122 and 132 containing oxygen are made n-type by diffusion of phosphorus oxychloride (POCl ₃ ) by bubbling at 0 ° C. to 850 ° C. I do. Within the above range, the thickness of the n-type polycrystalline silicon film containing oxygen is 5 nm to 200 nm, and the sheet resistance of this film is about 200 Ω / □ to 1000 Ω / □. This is because, due to the diffusion of phosphorus and the accompanying heat treatment, the oxygen contained in the non-doped polycrystalline silicon film containing oxygen does not form a silicon oxide, but this oxygen is more widely dispersed in the silicon crystal. It is considered to be in the state of having done. Due to the phosphorus diffusion, the lowermost non-doped polycrystalline silicon film 111 also becomes n-type, so that oxygen in the non-doped polycrystalline silicon film containing oxygen is completely Si.
This supports the observation that the bond O ₂ is not formed.

For example, in the laminated film made of n-type polycrystalline silicon formed on the interlayer insulating film 105 (flat portion on the gate electrode 103), the distribution of the oxygen concentration in the depth direction is shown in FIG. become that way. This is a measurement result by SIMS. There are three oxygen concentration peaks, a first peak at the surface, a second peak at a depth of about 150 nm, and a third peak at a depth of about 300 nm.
The second and third peaks have a considerable width, and the maximum value of the oxygen concentration at these peaks is about one digit lower than the oxygen concentration of the silicon oxide film. The first peak has a very high oxygen concentration value in a very narrow range (5 × 10 ²¹ a
toms / cm ^3, which is about the same as the oxygen concentration of the interlayer insulating film) and a region similar to the second and third peaks. This first
The region where the value of the oxygen concentration is extremely high at the peak of corresponds to the natural oxide film formed on the surface of the laminated film.

Next, a photoresist film 119 is formed in a region where a node electrode is to be formed, and anisotropic etching is performed on the laminated film made of n-type polycrystalline silicon.
Thus, as shown in FIG. 1C, the n-type polycrystalline silicon film 1 containing oxygen is formed in the region where the node electrode is formed.
34b, an n-type polycrystalline silicon film 133b, an oxygen-containing n-type polycrystalline silicon film 124b, an n-type polycrystalline silicon film 123b, an oxygen-containing n-type polycrystalline silicon film 114b, and an n-type polycrystalline silicon film 114b. A laminated film made of the polycrystalline silicon film 113b is formed. The side surface of this laminated film is substantially flat. This anisotropic etching is RIE under a pressure of about 200 mTorr and an RF power of about 300 W using dichlorodifluoromethane (CCl ₂ F ₂ ) of about 40 sccm as an etchant gas.

Next, without removing the photoresist film 119, sulfur hexafluoride (SF ₆ ) is used as an etchant gas.
Isotropic etching is performed on the exposed surface of the laminated film. By this etching, the n-type polycrystalline silicon film 134b containing oxygen and the n-type polycrystalline silicon film 133 are formed.
b, n-type polycrystalline silicon film 124b, n containing oxygen
As shown in FIG. 2A, an n-type polycrystalline silicon film 123b, an n-type polycrystalline silicon film 114b containing oxygen and an n-type polycrystalline silicon film 113b A polycrystalline silicon film 134c, an n-type polycrystalline silicon film 133c, an oxygen-containing n-type polycrystalline silicon film 124c, an n-type polycrystalline silicon film 123c, an oxygen-containing n-type polycrystalline silicon film 114c, And n
The polycrystalline silicon film 113c is formed, and the formation of the node electrode 117a of the stacked capacitor of the present embodiment composed of these laminated films is completed.

Here, when isotropic etching using sulfur hexafluoride is used, the n-type polycrystalline silicon film containing oxygen has no oxygen (or contains a very small amount of oxygen). Since the etching rate is lower than that of the polycrystalline silicon film, irregularities due to the depressions of the n-type polycrystalline silicon films 113c, 123c, and 133c are formed on the side surfaces of the node electrode 117a. In the isotropic etching used here, for example, 60 sccm sulfur hexafluoride is used as an etchant gas, and 100 sccm helium (He) is used.
Is used as a carrier gas and the pressure is 400 mTorr, RF
The power is 400W.

The depression at this time is about 0.1 to 0.3 μm. Although the increase in the surface area of the node electrode 117a due to the individual depressions is small, for example, even if the increase in the surface area due to one depression is about 6%, as shown in FIG. Can be increased to increase the surface area of the node electrode. In the case of this embodiment, the n-type polycrystalline silicon film containing no oxygen (or containing a very small amount of oxygen) is composed of three layers, each having a thickness of about 150 nm, and increasing the surface area of the node electrode. Is about 18%. For example, if the thickness of an n-type polycrystalline silicon film that does not contain oxygen (or contains a very small amount of oxygen) is reduced to about 50 nm and this film is increased from three layers to ten layers, the node electrode The increase in surface area is about 60%.

Next, the photoresist film 119 is removed,
Forming a capacitor insulating film 107 and a cell plate electrode 108;
Complete a stacked capacitor. Subsequently, a second interlayer insulating film 109 is deposited on the entire surface, and the bit diffusion layer 104b is formed.
The upper interlayer insulating films 109 and 105 are sequentially etched to open the bit contact holes 106b. Finally, a bit line 110 is formed, and as shown in FIG.
The DRAM having the node electrode 117a of the embodiment is completed.

In this embodiment, as described above, one photolithography step (and two etching steps) is required, and the number of steps is smaller than in the conventional manufacturing method for obtaining a fin structure. Further, in the present embodiment, the depth of the concave portion of the fin is at most about 0.3 μm, so that the mechanical strength at the stage when the node electrode is formed is secured. Further, as described above, since it is easy to increase the number of depressions on the side surface of the node electrode, a capacitor having a large capacitance can be easily obtained even if the occupied area of the stacked capacitor is small. .

Referring to FIG. 6, which is a schematic cross-sectional view of a main process for explaining a semiconductor memory device according to a second embodiment of the present invention along with a method of manufacturing the same, first, FIG.
1 are formed in the same manner as in the first embodiment.

Next, in an LPCVD apparatus, 500 ° C. to 6 ° C.
By thermal decomposition using a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ) in a temperature range of 00 ° C., an n-type polycrystalline silicon film 113 having a thickness of, for example, about 150 nm is deposited. Subsequently, oxygen (O ₂ ) was reduced to 0.2% in the same apparatus.
By exposing in an argon atmosphere containing about 5%, an n-type polycrystalline silicon film 114 containing oxygen is formed on the surface of the polycrystalline silicon film 113. By repeating the same operation twice more, the n-type polycrystalline silicon film 123, the oxygen-containing n-type polycrystalline silicon film 124, the n-type polycrystalline silicon film 133, and the oxygen-containing n-type polycrystalline silicon film 133 are formed. A crystalline silicon film 134 is sequentially formed, and a laminated polycrystalline silicon film is formed to obtain a structure shown in FIG.

Next, a heat treatment is performed in an inert atmosphere at 600 ° C. to 850 ° C., as shown in FIG. 6B, the n-type polycrystalline silicon film 134 containing oxygen and the n-type polycrystalline silicon film. 133, N-type polycrystalline silicon film 1 containing oxygen
24, n-type polycrystalline silicon film 123, n containing oxygen
The n-type polycrystalline silicon film 134a, the n-type polycrystalline silicon film 133a, and the n-type polycrystalline silicon film 133a,
N-type polycrystalline silicon film 124a containing oxygen, n-type polycrystalline silicon film 123a, n-type polycrystalline silicon film 114a containing oxygen, and n-type polycrystalline silicon film 1
13a. The purpose of this heat treatment is, for example, to disperse oxygen in the n-type polycrystalline silicon film 114 containing oxygen. As a result, the film thickness of the n-type polycrystalline silicon film 114a containing oxygen contains oxygen. This is larger than the thickness of the n-type polycrystalline silicon film 114.

Next, FIG. 1 in the first embodiment will be described.
(C), through the same steps as in FIG. 2 (a), the node electrode of this embodiment is completed. Further, by the same manufacturing method as shown in FIG. 2B in the first embodiment, a DRAM including the node electrode of this embodiment is completed.

In this embodiment, a laminated film made of an n-type polycrystalline silicon film is formed from the beginning. The growth rate of the n-type polycrystalline silicon film by the above-described method is the first
Lower than the growth rate of the non-doped polycrystalline silicon film in the embodiment. In this embodiment, it is possible to accurately form an n-type polycrystalline silicon film having a small thickness. Also,
For example, the thickness of the n-type polycrystalline silicon film 114a containing oxygen depends on the conditions of the above heat treatment. Therefore, the first
Compared to the embodiment, for example, n-type polycrystalline silicon film 113
a and n-type polycrystalline silicon film 114a containing oxygen
Can be formed even thinner. As a result,
In this embodiment, the surface area of the side surface of the node electrode can be further increased as compared with the first embodiment.

In the first and second embodiments, the laminated film made of the polycrystalline silicon film is formed by the LPCVD method. However, by using the MBE apparatus, the thickness of the polycrystalline silicon film containing oxygen and the oxygen There is also a method of forming the thickness of a polycrystalline silicon film containing no (or containing a very small amount of oxygen) with good controllability and a small thickness.

Referring to FIGS. 7 and 8 which are schematic cross-sectional views of main steps for explaining a semiconductor memory device according to a third embodiment of the present invention along with a method of manufacturing the same, FIG.
The steps up to the step shown in (a) are formed in the same manner as in the first embodiment.

Next, 500 ° C. to 6 ° C. in an LPCVD apparatus.
A non-doped polycrystalline silicon film 111 having a thickness of, for example, about 100 nm is deposited by thermal decomposition of silane (SiH ₄ ) in a temperature range of 00 ° C. Subsequently, a tungsten silicide film 115 having a thickness of, for example, about 50 nm is formed on the polycrystalline silicon film 111 by a reaction between tungsten hexafluoride (WF ₆ ) and silane (a so-called silane reduction method) in the same apparatus. The growth rate of the tungsten silicide film is a fraction of the growth rate of the non-doped polycrystalline silicon film 111.
Therefore, the thickness of the tungsten silicide film can be accurately formed. The same operation is repeated twice more to obtain a non-doped polycrystalline silicon film 121 having a thickness of about 100 nm.
A tungsten silicide film 125 having a thickness of about 50 nm,
Non-doped polycrystalline silicon film 13 having a thickness of about 100 nm
A tungsten silicide film 136 having a thickness of about 1 nm and a thickness of about 100 nm is formed to obtain the structure shown in FIG. Here, the thickness of the tungsten silicide film 136 is set to be larger than the thicknesses of the other tungsten silicide films 115 and 125. Further, in the laminated film including the polycrystalline silicon film and the tungsten silicide film in the present embodiment,
Preferably, the lowermost film is a polycrystalline silicon film.
This is for improving the adhesion between the node electrode to be formed in the node contact hole 106a and the node diffusion layer 104a, and the ohmic contact.

Next, a photoresist film 119a is formed in a region where a node electrode is to be formed. Subsequently, as shown in FIG. 7B, anisotropic etching is performed to form a tungsten silicide film 136a,
Non-doped polycrystalline silicon film 131a, tungsten silicide film 125a, non-doped polycrystalline silicon film 12
1a, a tungsten silicide film 115a, and a non-doped polycrystalline silicon film 111a are formed. This anisotropic etching is RIE using tetrafluoromethane (CF ₄ ). Etching conditions are
The flow rate of tetrafluoromethane is 50 sccm, the pressure is 100 mTorr, and the RF power is 300 W. Since the etching rate for the silicon oxide film is high in this etching, the interlayer insulating film 105 does not serve as a stopper in this etching. Therefore, the etching of the lowermost non-doped polycrystalline silicon film 111 requires careful attention.

Next, the photoresist film 119a is removed, and phosphorus is diffused. Thereby, the non-doped polycrystalline silicon films 131a, 121a, 111a are
As shown in FIG. 3A, n-type polycrystalline silicon films 133b, 123b, and 113b are obtained. This diffusion of phosphorus is possible because the diffusion coefficient of the polycrystalline silicon film is about one order of magnitude larger than that of single crystal silicon.

Next, by performing isotropic etching with an etchant gas containing sulfur hexafluoride (SF ₆ ), as shown in FIG. 8B, a tungsten silicide film 136a and an n-type polycrystalline silicon film are formed. 133b, a tungsten silicide film 125a, an n-type polycrystalline silicon film 123b, a tungsten silicide film 115a, and a laminated film composed of an n-type polycrystalline silicon film 113b are respectively a tungsten silicide film 136b and an n-type polycrystalline silicon film 133c. , Tungsten silicide film 12
5b, a laminated film including an n-type polycrystalline silicon film 123c, a tungsten silicide film 115b, and an n-type polycrystalline silicon film 113c. The node electrode 117b is constituted by this laminated film. In this etching, n
Since the etching rate of the polycrystalline silicon film is sufficiently higher than the etching rate of the tungsten silicide film (selectivity is high), a depression is formed on the side surface of the node electrode 117b due to the n-type polycrystalline silicon film.
In order to form this depression effectively, it is preferable to provide a tungsten silicide film instead of a polycrystalline silicon film in the uppermost layer. At the time of this etching, the thickness of the tungsten silicide film 136a as the uppermost layer becomes thin. Therefore, as described above, it is preferable that the thickness of the tungsten silicide film 136a is set to be thicker than the other tungsten silicide films.

The isotropic etching using an etchant gas containing sulfur hexafluoride (SF ₆ ) will be described. For example, 50 sccm of sulfur hexafluoride and 50 sccm of chlorine (Cl ₂ ) gas are used as an etchant gas, and the pressure is 100 to 100 sccm.
In dry etching at 150 mTorr and RF power of 200 to 300 W, the etching rate of the tungsten silicide film and the n-type polycrystalline silicon film is 70 to 9
0 nm / min, and 600 to 700 nm / min. In addition, as the etchant gas, sulfur hexafluoride alone or a mixed gas of sulfur hexafluoride and hydrogen bromide (HBr) can be used. Note that it is preferable to perform this isotropic etching after the polycrystalline silicon film is made n-type. In the case of a non-doped polycrystalline silicon film, the selectivity of the etching rate of this film to the tungsten silicide film decreases.

Next, similarly to the first embodiment, the capacitor electrode, the cell plate electrode, the second interlayer insulating film, the bit contact hole, and the bit line are formed, so that the node electrode of the present embodiment is formed. The provided DRAM is formed. In the first and second embodiments, a silicon oxide film formed by thermal oxidation can be used as the capacitance insulating film.
In this embodiment, for example, dichlorosilane (SiH
It is necessary to form a capacitive insulating film by a CVD method, such as a silicon nitride film by a CVD method of ₂ Cl ₂ ) and ammonia (NH ₃ ) gas.

In this embodiment, as described above, in the isotropic etching when forming the node electrode, the etching rate of the n-type polycrystalline silicon film is sufficiently higher than the etching rate of the tungsten silicide film. Therefore, the depression formed on the side surface of the node electrode is deeper than the depressions of the first and second embodiments. The surface area of the node electrode is larger than in the first and second embodiments.

In this embodiment, an n-type polycrystalline silicon film is used as the first conductor film and a tungsten silicide film is used as the second conductor film. For example, other refractory metal silicide films such as a molybdenum silicide film and a titanium silicide film can be used.

In the isotropic etching in the present embodiment, when a gate electrode having a so-called polycide structure in which the lower layer is made of an n-type polycrystalline silicon film and the upper layer is made of a refractory metal silicide film, the lower layer is made of n. The inconvenience that an undercut occurs in the mold polycrystalline silicon film is positively diverted.

Referring to FIGS. 9 and 10, which are schematic cross-sectional views of main steps for explaining a semiconductor memory device according to a fourth embodiment of the present invention along with a method of manufacturing the same, FIG. The steps up to the step shown in (a) are formed in the same manner as in the first embodiment.

Next, in an LPCVD apparatus, 500 ° C. to 6 ° C.
By thermal decomposition using a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ) in a temperature range of 00 ° C., for example, an n-type polycrystalline silicon film 113 having a thickness of about 75 nm is deposited. Subsequently, tungsten hexafluoride (WF)
₆ ) A tungsten silicide film 115 having a thickness of, for example, about 75 nm is formed on the polycrystalline silicon film 113 by a reaction between silane and silane (a so-called silane reduction method). Since the growth rate of the tungsten silicide film and the growth rate of the n-type polycrystalline silicon film are substantially the same and are a fraction of the growth rate of the non-doped polycrystalline silicon film 111 in the third embodiment, The thickness of the film and the n-type polycrystalline silicon film can be accurately formed. The same operation is repeated twice more to form an n-type polycrystalline silicon film 123 having a thickness of about 75 nm, a tungsten silicide film 125 having a thickness of about 75 nm, an n-type polycrystalline silicon film 133 having a thickness of about 75 nm, and a film thickness of about 75 nm. A tungsten silicide film 135 having a thickness of about 75 nm is formed to obtain a structure shown in FIG.

Next, a photoresist film 119b is formed in a region where a node electrode is to be formed. Subsequently, as shown in FIG. 9B, anisotropic etching is performed to form a tungsten silicide film 135a,
A stacked film including an n-type polycrystalline silicon film 133b, a tungsten silicide film 125a, an n-type polycrystalline silicon film 123b, a tungsten silicide film 115a, and an n-type polycrystalline silicon film 113b is formed. This anisotropic etching is performed under the same conditions as in the third embodiment.

Next, without removing the photoresist film 119b, sulfur hexafluoride (SF ₆ ) under the same conditions as in the third embodiment.
By performing isotropic etching with an etchant gas containing, as shown in FIG. 10, a tungsten silicide film 135b, an n-type polycrystalline silicon film 133c,
A tungsten silicide film 125b, an n-type polycrystalline silicon film 123c, a tungsten silicide film 115b,
The node electrode 117b of this embodiment is formed by a laminated film including the n-type polycrystalline silicon film 113c.

Next, similarly to the first embodiment, the capacitor electrode, the cell plate electrode, the second interlayer insulating film, the bit contact hole, and the bit line are formed, so that the node electrode of the present embodiment is formed. The provided DRAM is formed.

This embodiment is superior to the third embodiment in the controllability of the formation of the tungsten silicide film and the n-type polycrystalline silicon film. Therefore, it is easy to increase the number of depressions on the side surfaces of the node electrode by setting the respective film thicknesses to be thinner, and it is easy to further increase the surface area of the node electrode as compared with the third embodiment.

In the first, second, third, and fourth embodiments, the first conductive film is an n-type polycrystalline silicon film, and the second conductive film is an n-type oxygen-containing film. Dry etching using an etchant gas containing at least sulfur hexafluoride (SF ₆ ) is used as the polycrystalline silicon film or the tungsten silicide film and isotropic etching, but the present invention is not limited to these combinations. One condition to be selected as the material of the first and second conductor films is that the selectivity of the etching rate of the first and second conductor films to the isotropic etching is a sufficient value.

[0051]

According to the semiconductor memory device of the present invention, the second conductive film is formed on the side surface of the node electrode formed of the laminated film in which the first conductive film and the second conductive film are alternately stacked. The surface area of the side surface is increased due to the depression due to the above. For this reason, even if the occupied area of the stacked capacitor is reduced, a node electrode having a large opposing area can be obtained, and a DRAM having a high-density memory cell and a stacked capacitor having a large capacitance value can be realized. Although the increase in the surface area of the side surface of the node electrode due to one depression is small, in the present invention, the number of depressions can be increased by increasing the number of stacked films, so that the surface area of the side surface of the node electrode can be easily increased.

In the method for manufacturing a semiconductor memory device according to the present invention, a node film is formed by anisotropically etching a laminated film including a first conductive film and a second conductive film and further isotropically etching the laminated film. Electrodes are being formed. In the method for manufacturing a semiconductor memory device according to the present invention, the first conductor film and the second conductor film are formed such that the etching rate of the first conductor film in the isotropic etching is higher than the etching rate of the second conductor film. The material of the second conductive film, the etchant gas for isotropic etching and the etching conditions are selected, and the end of the first conductive film exposed on the side surface of the node electrode is exposed on the side surface of the node electrode. The second conductor film has a shape that is recessed from the end of the conductor film. Therefore, a node electrode having a large surface area on the side surface is formed by a simpler manufacturing process than in the related art. Further, by adopting the above-described manufacturing process, a reduction in mechanical strength in the manufacturing process of the node electrode does not occur, and a stable manufacturing method can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention in the order of steps for describing the semiconductor memory device according to a method of manufacturing the semiconductor memory device.

FIG. 2 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention in the order of steps for describing the semiconductor memory device according to a method of manufacturing the semiconductor memory device.

FIG. 3 is a diagram for explaining a method of manufacturing a laminated film constituting a node electrode of the semiconductor memory device of the first embodiment, and is a graph showing a temporal change of a gas region used for film formation.

FIG. 4 is a graph for explaining the effect of the first embodiment, and is a graph showing a change in the surface area of the node electrode with respect to the number of oxygen-containing polycrystalline silicon films.

FIG. 5 is a graph showing a distribution of oxygen concentration in a depth direction in a stacked film forming a node electrode of the semiconductor memory device of the first embodiment.

FIG. 6 is a schematic cross-sectional view of a main process for describing a semiconductor memory device according to a second embodiment of the present invention along a method of manufacturing the same.

FIG. 7 is a schematic cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention in a process order for describing the semiconductor memory device according to a manufacturing method thereof.

FIG. 8 is a schematic cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention in a process order for describing the semiconductor memory device according to a manufacturing method thereof.

FIG. 9 is a schematic cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present invention in a process order for describing the semiconductor memory device according to a manufacturing method thereof.

FIG. 10 is a schematic cross-sectional view of a main process for describing a semiconductor memory device according to a fourth embodiment of the present invention along a method of manufacturing the same.

FIG. 11 is a schematic cross-sectional view of a conventional stacked capacitor DRAM having a fin-type node electrode in order of steps for describing the DRAM along a manufacturing method.

FIG. 12 is a schematic cross-sectional view of a conventional stacked capacitor DRAM having a fin-type node electrode in order of steps for describing the DRAM along a manufacturing method.

[Explanation of symbols]

101, 201 silicon substrate 102, 202 field oxide film 102a, 202a gate oxide film 103, 203 gate electrode 104a, 204a node diffusion layer 104b, 204b bit diffusion layer 105, 205, 209 interlayer insulating film 106a, 206a node contact hole 106b, 206b Bit contact hole 107, 207 Capacitance insulating film 108, 208 Cell plate electrode 110, 210 Bit line 111, 121, 131 Non-doped polycrystalline silicon film 112, 122, 132 Non-doped polycrystalline silicon film containing oxygen 113, 113a, 113b , 113c, 123, 12
3a, 123b, 123c, 133, 133a, 133
b, 133c, 213, 213a, 213b, 223a
n-type polycrystalline silicon film 114, 114a, 114b, 114c, 124, 12
4a, 124b, 124c, 134, 134a, 134
b, 134c N-type polycrystalline silicon film containing oxygen 115, 115a, 115b, 125, 125a, 12
5b, 135, 135a, 135b, 136, 136
a, 136b Tungsten silicide film 117a, 117b, 217 Node electrode 119, 119a, 119b, 218, 219 Photoresist film 227, 227a, 227b, 228, 228a, 22
8b Silicon oxide film

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-120050 (JP, A) JP-A-63-313854 (JP, A) JP-A-2-10762 (JP, A) JP-A-3-3 16258 (JP, A) JP-A-4-65159 (JP, A) JP-A-4-6865 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21 / 822 H01L 21/8242 H01L 27/04

Claims (5)

(57) [Claims] 1. A dynamic random access memory having a node electrode connected to a node diffusion layer formed by diffusion of an impurity into a semiconductor substrate and a stacked capacitor including a capacitive insulating film, wherein the node electrode is a first type. A conductive film and a second conductive film are alternately stacked, and on the side surface of the laminated film,
The end of the first conductor film is located at a position depressed from the end of the second conductor film, and the second conductor film is capable of absorbing oxygen.
A semiconductor memory device comprising an n-type polycrystalline silicon film . 2. The semiconductor memory device according to claim 1, wherein said first conductor film is an n-type polycrystalline silicon film. (3)One MOS transistor and one star
Dynamic random consisting of a locked capacitor
In a method of manufacturing a node electrode of an access memory, a p-type
A gate insulating film and word line
Gate electrode, n-type node diffusion layer and n-type bit diffusion layer
MOS transistor consisting of
A node contact that deposits a film and reaches the node diffusion layer
Opening a hole in the interlayer insulating film;
A laminated film formed by alternately depositing a film and a second conductor film is formed.
And a photoresist in an area where a node electrode is to be formed.
A photoresist film and using the photoresist film as a mask
Anisotropically etching the laminated film; and
At least the exposed surface by the anisotropic etching,
Anisotropic etching step,  The first conductor film is an n-type polycrystalline silicon film.
The second conductive film is an n-type polycrystalline silicon containing oxygen.
When formed of a recon film, the step of forming the laminated film is non-
Deposition of doped polycrystalline silicon film, said non-doped polycrystalline
The above method by exposing a silicon film to an oxygen atmosphere.
Non-doped oxygen-containing polycrystalline silicon film surface
The formation of a polycrystalline silicon film is performed alternately,
Polycrystalline silicon film and non-doped polycrystalline silicon containing oxygen
Forming a first stacked film made of a crystalline silicon film;
Diffusing phosphorus into the first laminated film.
And a method for manufacturing a semiconductor memory device. (4)One MOS transistor and one star
Such as cooked capacitors Dynamic random type
In a method of manufacturing a node electrode of an access memory, a p-type
A gate insulating film and word line
Gate electrode, n-type node diffusion layer and n-type bit diffusion layer
MOS transistor consisting of
A node contact that deposits a film and reaches the node diffusion layer
Opening a hole in the interlayer insulating film;
A laminated film formed by alternately depositing a film and a second conductor film is formed.
And a photoresist in an area where a node electrode is to be formed.
A photoresist film and using the photoresist film as a mask
Anisotropically etching the laminated film; and
At least the exposed surface by the anisotropic etching,
Anisotropic etching step,  The first conductor film is an n-type polycrystalline silicon film.
The second conductive film is an n-type polycrystalline silicon containing oxygen.
When comprising a recon film, the step of forming the laminated film,
The above n by CVD of a silane-based gas containing phosphine.
Depositing an n-type polycrystalline silicon film;
The n-type multi-layer by exposing the capacitor film to an oxygen atmosphere.
An n-type polycrystalline silicon containing oxygen on the surface of the crystalline silicon film;
Alternate formation of a recon film and an inert atmosphere
Performing a heat treatment with air.
Manufacturing method of a semiconductor memory device. 5. The method according to claim 1, wherein the isotropic etching comprises at least 6
Method of manufacturing have some claim 3, characterized in that the dry etching with an etchant gas containing sulfur hexafluoride semiconductor memory device according to claim 4, wherein.