JP3068317B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a capture function for latching the contents of a counter by inputting a trigger signal.

[0002]

2. Description of the Related Art In recent years, the application fields of microcomputers have been rapidly expanding and are being used in various fields. In particular, recently, microcomputers are increasingly used for controlling motors for moving objects in OA, FA, and the like. Motor control requires a microcomputer equipped with hardware suitable for motor control. Generally, a microcomputer has a configuration as shown in FIG. In the microcomputer 1, the CPU 3 performs arithmetic processing according to the instructions stored in the memory 2, and the peripheral functions 4 are controlled. The peripheral function 4 controls the external device by outputting a control signal to an external device connected to the outside of the microcomputer 1 or inputting a status signal from the external device. Hardware suitable for controlling the motor belongs to the peripheral function 4.

Next, FIG. 7 shows a configuration diagram of a capture circuit, FIG. 6 shows a detailed configuration diagram of one bit of a capture register, and measurement of a time interval of a pulse generated from an external device using a timing chart of FIG. The method will be described.
In FIG. 7, the trigger signal is a signal obtained by synchronizing a pulse input from another peripheral function, for example, from the outside of the microcomputer, to a system clock in the man-computer. The trigger signal is connected to the capture register 110 and also serves as an interrupt request signal to the CPU.

A counter (CNT) 150 counts up each time a count clock is input. The count clock is input at fixed time intervals. In FIG. 7, the capture register is illustrated by CTO. The CPU inputs the address of the capture register 110 to the address bus 100, and the read signal (RD) 10
2 from the signal line 102, the RDCTO
A signal is output from the read control circuit 104. At the same time, the data bus 107 and the bus 108 connecting the capture register 110 are connected by the bus connection circuit 106. Therefore, the value of the capture register 110 is read onto the data bus 100.

[0005] The counter bus 109 of the counter 150 is
Capture register 110 via bus connection circuit 152
Is connected to the data input of each bit latch 202. Therefore, the trigger input is the latch clock of the latch 202. Therefore, when there is a trigger input, the content of the counter 150 is latched in the capture register 110 via the counter bus 109.

[0008] In FIG. 8, it is assumed that there is a trigger input at stage C. The trigger input is output as an interrupt request signal to the CPU and the capture register 1
10 is input. Therefore, the capture register 110
Latches the content "01H" of the counter 150. CP
In U, when the interrupt request signal is received, the processing being executed is interrupted, and in the stage G, the capture register 110
Is read out and stored.

Next, it is assumed that there is a trigger input at stage L. Similarly, the capture register 110 latches the content "0AH" of the counter 150. When the CPU accepts the interrupt request signal, the CPU interrupts the processing being executed, reads out the content “0AH” of the capture register 110 at stage P, and reads the content “01H” of the capture register 110 stored in the previous interrupt processing, and this time. The difference "09H" from the content "0AH" of the capture register 110 is obtained by calculation.

Since the count clock of the counter 150 is input at regular time intervals, the capture register 1
By calculating the product of the difference “09H” of the content of 10 and the input time interval of the count clock, the time interval of the pulse emitted from the external device can be easily obtained. C
The PU determines the time interval between the obtained pulses and performs control on the external device, for example, turning the motor faster.

In recent years, since the speed of microcomputers has been rapidly increased, the speed of measuring the time interval of the pulse generated from the above-mentioned external device is also required to be increased. However, in the conventional microcomputer, the capture register to which the trigger input is connected is fixed. Therefore, when the CPU reads the contents of the counter latched by the capture register every time a trigger is input,
If there is a next trigger input before the CPU reads the contents of the capture register after the input of the trigger, the capture register re-latches the contents of the counter. Therefore, the contents of the counter latched by the capture register for the first time are erased. Therefore, the time interval of the trigger input must be equal to or longer than the time from when the CPU accepts the interrupt and when the CPU completes the operation of reading the contents of the capture register.

[0010]

The problem to be solved is that there is a limit to the time interval of the pulse which can be measured by the microcomputer, and the control of the external device cannot be speeded up.

[0011] In order to solve the above-mentioned problems, a mask according to the present invention is used.
Microcomputer stores programs or data
DoExecutes arithmetic processing according to the memory and the program
DoIn a microcomputer including a CPU,
Update content based on supplied clockDoSingular
Or a plurality of counters and latch the contents of the counters
DoA plurality of capture registers;
The timing at which the register latches the contents of the counter
DesignationDoTrigger signal inputEvery,The contents of the counterLa
SwitchSelect the capture register to
A register can continuously latch the contents of the counter.
And banWith the CPU
An interrupt request signal to read out the contents latched by the
EmpowerA capture register selection circuit. Ma
The capture register according to the present inventionSelection circuit
Latches each of the trigger signalsDoMultiple latch means
And the order of each trigger signalYou
ToTrigger judgment means and,Determine latch conditionDoMore than one
And a switch condition determining means. Further according to the invention
Each of the latch means in the D-latch circuit and the RS latch
Switch and a trigger circuit.
The determination means is constituted by an AND circuit, and
The switch condition determination means uses an inverter and another AND circuit.
It is configured.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a capture circuit in a microcomputer according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a capture register selection circuit;
4 is a read control circuit, 150 is a counter, 110, 1
20 is a capture register, 131, 133,
134, 137, 161, 162, 163, and 164 are latch circuits, 112, 122, 136, and 166 are AND circuits, 130, 135, 138, and 15, respectively.
1 and 160 are inverters and 105 and 165 are O
R gate.

The counter 150 and the capture register 110 (CT0) operate in the same manner as in the conventional example. The capture register (CT1) operates in the same manner as the capture register 110 (CT0) described in the conventional example, and a description thereof will be omitted. Also, the components having the same reference numerals as those in the conventional example perform the same operations as those in the conventional example, and the description thereof is omitted. A trigger input signal input from another peripheral function is input to the set input terminal of the RS latch circuit 133 via the D latch circuit 131,
The output of the RS latch circuit 133 is input to the set input terminal of the RS latch circuit 137 via the AND circuit 136 and the D latch circuit 134 whose other input terminals are trigger input signal terminals.

The trigger input signal is a trigger input to the capture register 110 (CT0) via the AND circuit 112 connected to the other input terminal changing inverter 135 and the output of the inverter 130. The output of the AND circuit 112 is an interrupt request signal to the CPU. The output of the latch circuit 133 and the system clock are input to the inverters 135 and 130, respectively. The other input terminals of the trigger input signal are the inverter 138, the D latch circuit 133, and the inverter 1
A trigger input of the capture register 120 is provided through an AND circuit 122 connected to the input terminal 30. The output of the AND circuit 122 is an interrupt request signal to the CPU. The D latch circuit 137 is input to the inverter 138.

When a read access occurs from the CPU, RDCT0, RDT0 generated by the read control circuit 104
The DCT1 signal is supplied to the capture register 110,
120 as a read signal. Also, R
The DCT0 and RDCT1 signals are applied to set input terminals of RS latch circuits 161 and 163, respectively. R
The clock input terminals of the S latch circuits 161, 163
The output terminals of the RS latch circuits 161 and 163 to which the inverter 160 receiving the system clock is connected are connected to the data input terminals of the D latch circuits 162 and 164, respectively. A system clock is connected to clock input terminals of the D latch circuits 162 and 164. The output terminals of the D latch circuits 162 and 164 are AND
The OR circuit 1 connected to the circuit 166 and the output terminal of the AND circuit 166 is connected to another input terminal system reset.
65. The output terminal of the OR circuit 165 is
The RS latch circuits 133, 137, 161 and 163 are connected to respective reset input terminals.

Next, the operation when the trigger input signal is continuously input will be described below with reference to the configuration diagram of FIG. 1 and the timing chart of FIG. In stage A,
The system reset is "1". The system reset is performed via the OR circuit 165 and the RS latch circuits 133, 13
7, 161 and 163 are input to the reset input terminals.
The outputs of the S latch circuits 133, 137, 161 and 163 become "0". Next, in stage B, the system reset changes from “1” to “0”, and the counter 150 sets “0”.
0H ”starts counting up.

It is assumed that a trigger input signal is input at stage C. The trigger input “1” is input to the AND circuit 112
Is input to At this time, the output of the inverter 135, which is another input terminal of the AND circuit 112, is "1". Therefore, when the system clock becomes "0", the output of the inverter 130 applied as the other input also becomes "1", and the output of the AND circuit 112 becomes "1". The output “1” of the AND circuit 112 is input to the latch clock of each bit of the capture register 110, and latches “01H” of the counter bus.

When the system clock becomes "0",
The trigger input signal is latched by the D latch circuit 131. When the second system clock of the stage C is “1”, the trigger input signal is input to the set side of the RS latch circuit 133, and the output of the RS latch circuit 133 is “1”. ". R
The output “1” of the S latch circuit 133 is input to the AND circuit 136, but the trigger input signal is “0”, so that the AND circuit 136, the D latch circuit 134, and the R
The S latch circuit 137 remains “0”.

On the other hand, when a trigger input signal is input at stage C, the trigger input "1"
2 is input. Since the output of the RS latch circuit 133 connected to the other input terminal of the AND circuit 122 is “0”, the output of the AND circuit 122 is “0”. AN
Since the output of the D circuit 122 serves as a latch clock for the capture register 120, the capture register 120 cannot latch the value on the counter bus 108.

Next, it is assumed that a trigger input signal is input at stage G. The trigger input “1” is input to the AND circuit 112. Since the output of the inverter 135 connected to the other input terminal of the AND circuit 112 is "0", the output of the AND circuit 112 is "0", and the capture register 110 cannot latch the value on the counter bus 108.

On the other hand, the trigger input "1" is
2 is input. The output of the RS latch circuit 133 connected to another input terminal of the AND circuit 122 is “1”, and the output of the inverter 138 connected to another input terminal of another AND circuit 122 is “1”. Therefore, when the system clock becomes “0”, the output of the inverter 130 connected to another input terminal also becomes “1”, and the output of the AND circuit 122 becomes “1”. The output “1” of the AND circuit 122 is input to the latch clock of each bit of the capture register 120, and latches “05H” on the counter bus.

When the CPU accepts the interrupt request signal, the CPU interrupts the processing being executed, reads the content "01H" of the capture register 110 at stage K, and subsequently reads the content "05H" of the capture register 120 at stage O. Subsequently, the CPU obtains the difference “04H” between the content “01H” of the capture register 110 and the content “05H” of the current capture register 110 by calculation.

Since the count clock of the counter 150 is input at fixed time intervals, the pulse generated from the external device is calculated by calculating the product of the difference “04H” of the content of the capture register and the input time interval of the count clock. Can be easily obtained. CPU
Determines the time interval of the pulse determined above,
Control of the external device, for example, control of rotating the motor faster is performed. In stage K, the read control circuit
DCT0 is output and input to the reset and input terminals of the RS latch circuit 161. Therefore, the RS latch circuit 161 is reset to “0” at the fall of the system clock. The output of the RS latch circuit 161 is latched by the D latch circuit 162 at the next rise of the system clock, and “1” is input to the AND circuit 166.

Similarly, at stage O, RDCT 1 is output from the read control circuit, and “1” is input to AND circuit 166 via RS latch circuit 163 and D latch circuit 164. At this time, since the value of the other input terminal 162 of the AND circuit 166 is already “1”,
“1” is output from the AND circuit 166 and the OR circuit 16
5, the RS latch circuits 133, 137, 161,
163 is input to a reset input terminal. So RS
The outputs of the latch circuits 133, 137, 161 and 163 become "0", and when the next trigger is input, latching from the capture register 110 becomes possible as described above.

As described above, when a trigger signal is input to the present capture circuit, the number of capture registers to be latched is limited to one for each input of the trigger signal. However, since the other capture registers are not changed, the pulse time interval can be measured up to the count clock input time interval. Therefore, external devices can be controlled at high speed.

FIG. 3 is a block diagram showing a second embodiment of the microcomputer according to the present invention. FIG.
4 is a timing chart of the operation related to FIG. 3, the same reference numerals as those shown in FIG. 1 indicate the same elements. Reference numerals 510 and 520 denote capture registers, respectively 531, 533, 534, 537, 561 to 56.
4 is a latch circuit, 512, 522, 536, 5
39 and 566 are AND circuits, 535 and 538 are inverters, and 565 is an OR gate.

Next, a second embodiment of the present invention will be described with reference to the block diagram of FIG. 3 and the timing chart of FIG. In FIG. 3, circuits having the same reference numerals and names as those in FIG. 1 perform the same operations as those in FIG. In FIG. 3, the output of the RS latch circuit 137 is connected to the D latch circuit 531 and the RS latch circuit 137.
The signal is input to the set input terminal of the latch circuit 533. RS
The output of the latch circuit 533 is provided by the AND circuit 536 and the D latch circuit 5 whose other input terminals are trigger input signal terminals.
The signal is input to the set input terminal of the RS latch circuit 537 via the line 34.

The other input terminals of the trigger input signal are the inverter 535, the inverter 130 and the RS latch circuit 1.
The signal is applied to a trigger input terminal of a third capture register 510 (CT2) via an AND circuit 512 connected to 33, 137. The output of the AND circuit 512 is an interrupt request signal to the CPU. The output of the D latch circuit 533 is input to the inverter 535.

The other input terminal of the trigger input signal is connected to the inverter 538, the D latch circuit 533, the inverter 130, and the RS latch circuits 133 and 137.
Via the D circuit 522, the fourth capture register 520
(CT3) is applied to the trigger input terminal. AND
The output of the circuit 522 is an interrupt request signal to the CPU. The output of the D latch circuit 537 is input to the inverter 538.

When a read is performed from the CPU and an access occurs, RDCT2 and RD generated by the read control circuit are generated.
The CT3 signal is supplied to the third capture register 51, respectively.
0 is input as a read signal. Also, RDC
The T2 and RDCT3 signals are supplied to the RS latch circuit 56, respectively.
1,563 reset input terminals. RS
The clock input terminals of the latch circuits 561 and 563 are connected to the output of the inverter 160 that receives the system clock. Output terminals of the RS latch circuits 561 and 563 are input to data input terminals of the D latch circuits 562 and 564, respectively.

A system clock is input to clock input terminals of the D latch circuits 562 and 564. The output terminals of the D latch circuits 562 and 564 are connected to the AND circuit 5 whose other input terminals are connected to the D latch circuits 162 and 164.
66. The other input terminal of the output terminal of the AND circuit 566 is connected to the system reset. The signal is input to the OR circuit 565. OR circuit 565
Output terminals are RS latch circuits 133, 137, and 16
1, 163, 561 and 563 are connected to respective reset input terminals.

In FIG. 4, assuming that a trigger input signal is input at stages C, F, G, and N, the first to fourth capture registers 110, 120, 510, and 520 have "01H" and "04H", respectively. , "05H", "0C
H "is latched. At this time, when the CPU accepts the interrupt request, the content is read out from one of the first to fourth capture registers 110, 120, 510, and 520 which generated the interrupt request, and the content of the capture register is read out. By calculating the product of the difference between the above and the input time interval of the count clock, the time interval of the pulse generated from the external device is obtained, and the external device is controlled.

As described above, when a trigger signal is input to the present capture circuit, the number of capture registers to be latched is limited to one for each trigger signal input, and the contents of other capture registers are not changed. Therefore, the time interval of the pulse can be measured up to the input time interval of the count clock, so that the external device can be controlled at high speed. In the above description, R is used as the capture register selection circuit.
Although the S-latch circuit and the D-latch circuit are combined, a similar effect can be obtained by using a shift register or the like, and the object of the present invention can be achieved.

[0034]

As described above, the present invention selects a capture register for latching the contents of a counter when a trigger signal is input to a microcomputer having a conventional capture circuit, and furthermore, the same capture register is continuously used. In order to prohibit latching the contents of the counter, the capture register selection circuit is added. As a result, the hardware can be used effectively, and there is an advantage that the time interval of the pulse that can be measured is not limited. In addition, since the control of the external device can be accelerated, a microcomputer having a wide application field can be used. There are effects that can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a capture unit according to the present invention.

FIG. 2 is a timing chart showing an operation of the capture unit shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the capture unit according to the present invention.

FIG. 4 is a timing chart showing an operation of the capture unit shown in FIG. 3;

FIG. 5 is a block diagram showing a system of a general microcomputer.

FIG. 6 is a block diagram showing one bit of a capture circuit.

FIG. 7 is a block diagram illustrating an example of a conventional capture unit.

FIG. 8 is a timing chart showing an operation of the capture unit shown in FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microcomputer 2 Memory 3 CPU 4 Peripheral device 10 Capture register selection circuit 100 Data bus 101 Address bus 104 Read control circuit 105,165,565 OR gate 110,120,510,520 Capture register 112,122,136,166,512 , 522, 5
36,539,566 AND circuit 130,135,138,151,160,535,5
38 Inverters 131, 133, 134, 137, 161-164, 5
31, 533, 534, 537, 561 to 564 Latch circuit 150 Counter

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G04F 10/04 G06F 1/14

Claims (3)

(57) [Claims] 1. A memory for storing a program or data, and a CP for executing arithmetic processing according to the program.
U, a single or a plurality of counters for updating the content based on a supplied clock, a plurality of capture registers for latching the content of the counter, and the capture register for storing the content of the counter. each trigger signal input specifying timing to latch to highlight capture register for latching the contents of the counter, along with prohibiting latching the contents of the counter the same capture register in succession, the CPU
Read the contents latched in the capture register
And a capture register selection circuit that outputs a capture request signal . Wherein said capture register selection circuit determines a plurality of latch means for latching the respective trigger signal, a trigger determination unit that the respective trigger signals to determine whether there are many th ones, a latch condition 2. The microcomputer according to claim 1, comprising a plurality of latch condition determination means. 3. Each of the latch means is constituted by a combination of a D latch circuit and an RS latch circuit, the trigger judgment means is constituted by an AND circuit, and each of the latch condition judgment means is constituted by an inverter and another AND. 3. The microcomputer according to claim 2, comprising a circuit.