JP3070095B2 - Input/Output Protection Circuit - Google Patents
Input/Output Protection CircuitInfo
- Publication number
- JP3070095B2 JP3070095B2 JP2305346A JP30534690A JP3070095B2 JP 3070095 B2 JP3070095 B2 JP 3070095B2 JP 2305346 A JP2305346 A JP 2305346A JP 30534690 A JP30534690 A JP 30534690A JP 3070095 B2 JP3070095 B2 JP 3070095B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- voltage
- gate
- protection circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路に関し、特に、半導体集積
回路の入出力保護回路に関する。Description: FIELD OF THEINVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to an input/output protection circuit for a semiconductor integrated circuit.
従来の技術 従来におけるこの種の入出力保護回路は、第４図に示
すように、入力端子１と電源VDD間にPch CMOSトランジ
スタ（Tr）12を挿入、そのゲ−トと電源VDDを接続し、
又入力端子１と電源VSS間にNch CMOSトランジスタ（T
r）13を挿入し、そのゲ−トと電源VSSを接続したもの
と、第５図に示すように、入力端子１にポリシリコン又
は拡散によって形成した抵抗３を接続し、この抵抗３の
もう一端に電源VDDとVSSに対しツェナダイオード14を接
続したものと、第６図に示すように、入力端子１と電源
VSS又はVDDの間にショクレーダイオ−ド15を挿入して形
成されていた。PRIOR ART As shown in FIG. 4, a conventional input/output protection circuit of this type has a Pch CMOS transistor (Tr) 12 inserted between an input terminal 1 and a power supply V DD , and its gate is connected to the power supply V DD .
In addition, an Nch CMOS transistor (T
r) 13 is inserted and its gate is connected to the power supply VSS . As shown in FIG. 5, a resistor 3 formed by polysilicon or diffusion is connected to the input terminal 1 and a Zener diode 14 is connected to the other end of this resistor 3 between the power supplies VDD and VSS . As shown in FIG. 6,
A Shockley diode 15 is inserted between VSS and VDD .
発明が解決しようとする課題 このような従来の入力出力保護回路では例えば保護さ
れるゲ−トの酸化膜厚が700Åのとき（ゲ−トブレーク
ダウン電圧は約70V）最大許容ゲ−ト電圧を約20Vに設定
したとすると、Pch、Nch MOS Trを用いた第４図の場合
には、トランジスタのディメンジョンを変えるなどして
パンチスルー電圧を調整しなければならず、又大電流が
流れることからこれらのPch、Nch MOS Tr（第４図の1
2、13、）の大きさも大きくしなければならないという
課題があった。Problems to be Solved by the Invention In such a conventional input/output protection circuit, for example, when the oxide film thickness of the gate to be protected is 700 Å (gate breakdown voltage is about 70 V), if the maximum allowable gate voltage is set to about 20 V, in the case of FIG. 4 using Pch and Nch MOS Tr, the punch-through voltage must be adjusted by changing the transistor dimensions, and since a large current flows, it is necessary to adjust the punch-through voltage ...
2, 13,) also had to be increased in size.
又第５図、第６図に示す様なツェナダイオード（第５
図の14）、ショックレーダイオ−ド（第６図の15）を用
いた場合でもこれらのブレークダウン電圧を拡散層を追
加する等してコントロ−ルしなければならず、拡散プロ
セスが複雑となるという課題があった。 Also, Zener diodes as shown in Figs. 5 and 6 (Fig. 5)
Even when a diode (14 in FIG. 6) or a Shockley diode (15 in FIG. 6) is used, the breakdown voltage must be controlled by adding a diffusion layer, which complicates the diffusion process.
本発明は従来の上記実情に鑑みてなされたものであ
り、従って本発明の目的は、従来の技術に内在する上記
諸課題を解決することを可能とした新規な入出力保護回
路を提供することにある。 The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel input/output protection circuit that makes it possible to solve the above-mentioned problems inherent in the conventional technology.
課題を解決するための手段 上記目的を達成する為に、本発明に係る入出力保護回
路は、入力又は出力端子（第１図の１）と電源（第１図
のVss）との間にPUT（第１図の２）を挿入し、このPUT
のゲ−トを保護入力電圧端子（第１図の９）として設け
ることを特徴としている。更に詳しくは、本発明に係る
入出力保護回路は、保護すべき内部回路に接続された入
力端子又は出力端子と電源との間にアノード及びカソー
ドが接続されたPUTを有し、このPUTのゲートには前記電
源の電圧以上で、前記内部回路のブレークダウン電圧以
下の電位を印加している。In order to achieve the above object, the input/output protection circuit according to the present invention includes a PUT (2 in FIG. 1) inserted between an input or output terminal (1 in FIG. 1) and a power supply (V ss in FIG. 1), and the PUT
The input/output protection circuit according to the present invention is characterized in that the gate of the input/output protection circuit is provided as a protection input voltage terminal (9 in FIG. 1). More specifically, the input/output protection circuit according to the present invention has a PUT with an anode and a cathode connected between a power supply and an input terminal or an output terminal connected to an internal circuit to be protected, and a potential equal to or higher than the voltage of the power supply and equal to or lower than the breakdown voltage of the internal circuit is applied to the gate of this PUT.
実施例 次に本発明をその好ましい一実施例について図面を参
照して具体的に説明する。BEST MODE FOR CARRYING OUT THE PRESENT DISCLOSURE The present invention will now be described in detail with reference to the accompanying drawings, in which: FIG.
第１図は本発明による第１の実施例を示す等価回路図
である。 FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention.
第１図を参照するに、入力端子１にPUT2のアノード側
（又はカソード側）を接続し、カソード側を電源V
SS（又はアノード側を電源VDD）に接続し、ゲ−トを接
続した端子を保護電圧入力端子９として設ける。ゲート
には外部より電源電圧以上で、内部回路のゲ−トブレー
クダウン電圧以下の任意の正電圧（電源VDDに接続の場
合には負電圧）を印加する。 Referring to Figure 1, connect the anode (or cathode) of PUT2 to input terminal 1, and connect the cathode to the power supply V
The terminal to which the SS (or anode side is connected to the power supply V DD ) and the gate is connected is provided as the protection voltage input terminal 9. An arbitrary positive voltage (negative voltage when connected to the power supply V DD ) that is equal to or higher than the power supply voltage and equal to or lower than the gate breakdown voltage of the internal circuit is applied to the gate from outside.
このことにより、もしICの入力端子にゲ−トに印加し
た電圧よりも大きな正（VDD接続の場合には負）電圧が
加えられた場合には入力端子−電源間のPUT2が“ON"
し、内部回路が保護される。 As a result, if a positive voltage (negative in the case of V DD connection) greater than the voltage applied to the gate is applied to the input terminal of the IC, PUT2 between the input terminal and the power supply will be in the "ON" state.
This protects the internal circuits.
又、入力端子に負（VDD接続の場合には正）の電圧が
加えられた場合には、第２図に示された本発明の半導体
チップ断面図の内、Ｐ型拡散層５とＮ型半導体基板４の
PN接合のブレークダウン電圧とＮ型拡散層６とＰ型拡散
層５のPN接合のブレークダウン電圧を足した電圧以上で
ブレークダウンが起き、内部回路が保護される。もしこ
のブレークダウン電圧がゲートブレークダウン電圧より
高い場合には、電源VSSとVDDの両方の電源に対しPUTを
挿入する。 In addition, when a negative voltage (positive in the case of V DD connection) is applied to the input terminal, the P-type diffusion layer 5 and the N-type semiconductor substrate 4 in the cross-sectional view of the semiconductor chip of the present invention shown in FIG.
Breakdown occurs and the internal circuit is protected at a voltage equal to or higher than the sum of the breakdown voltage of the PN junction and the breakdown voltage of the PN junction between the N-type diffusion layer 6 and the P-type diffusion layer 5. If this breakdown voltage is higher than the gate breakdown voltage, a PUT is inserted into both the power supplies V SS and V DD .
第３図は本発明による第２の実施例を示す等価回路図
である。 FIG. 3 is an equivalent circuit diagram showing a second embodiment of the present invention.
第３図を参照するに、入力端子１にPUT2のアノード側
（又はカソード側）を接続し、PUT2のカソード側（アノ
ード側）と電源VSS（又は電源VDD）を接続し、PUT2のゲ
−トを保護電圧入力端子９として設ける。又、PUT2のゲ
−トと入力端子間にポリシリコン又は拡散で形成した抵
抗10を設ける。 3, the anode side (or cathode side) of PUT2 is connected to input terminal 1, the cathode side (anode side) of PUT2 is connected to power supply VSS (or power supply VDD ), and the gate of PUT2 is provided as a protection voltage input terminal 9. In addition, a resistor 10 formed by polysilicon or diffusion is provided between the gate of PUT2 and the input terminal.
この時のPUT2の耐圧は、内部回路のゲートブレークダ
ウン電圧よりも低くなる様に設定し（ゲート酸化膜が70
0Åの場合には、ゲートブレークダウン電圧は約70Vであ
るからPUT2の耐圧は50Vとする）。 The withstand voltage of PUT2 at this time is set to be lower than the gate breakdown voltage of the internal circuit (gate oxide film is 70
In the case of 0 Å, the gate breakdown voltage is about 70 V, so the withstand voltage of PUT2 is set to 50 V.
もし入力端子に高い電圧が印加されてもショックレイ
ダイオードの様に動作し、ゲ−ト酸化膜を保護する。動
作中は、CPU2のゲ−ト（即ち保護電圧入力端子９）に最
大許容ゲ−ト電圧（例えば20V）を印加した場合には例
えば20V以上の入力電圧で保護回路が動作する様にコン
トロ−ルする 発明の効果 以上説明したように、本発明によれば、入出力保護回
路にCPUを用い保護電圧入力端子（第１図の９）を設け
たことにより、保護回路のディメンジョン又はブレーク
ダウン電圧を細かく調整することなしに、最適の最大許
容ゲ−ト電圧を保護電圧入力端子（CPU2のゲ−ト）に印
加するだけで、素子が動作している間は最大許容ゲ−ト
電圧以上の弾圧が入出力端子に印加されても入出力回路
が動作し、内部回路を保護することが出来るという効果
が得られる。 Even if a high voltage is applied to the input terminal, it operates like a Shockley diode and protects the gate oxide film. During operation, if the maximum allowable gate voltage (e.g., 20V) is applied to the gate of CPU2 (i.e., protection voltage input terminal 9), the protection circuit is controlled so that an input voltage of 20V or more will operate. Effects of the Invention As described above, according to the present invention, by using a CPU for the input/output protection circuit and providing a protection voltage input terminal (9 in Fig. 1), it is possible to obtain the effect that the input/output circuit will operate and the internal circuit will be protected even if a voltage exceeding the maximum allowable gate voltage is applied to the input/output terminal while the element is operating, simply by applying the optimum maximum allowable gate voltage to the protection voltage input terminal (gate of CPU2) without finely adjusting the dimensions or breakdown voltage of the protection circuit.
第１図は本発明による第１の実施例を示す等価回路図、
第２図は第１の実施例の半導体チップ断面図、第３図は
本発明による第２の実施例を示す等価回路図、第４図は
従来技術による第１の例としてPch、Nch MOS Trを用い
た場合の等価回路図、第５図は従来技術による第２の例
としてツェナダイオ−ドを用いた場合の等価回路図、第
６図は従来技術による第３の例としてショックレーダイ
オ−ドを用いた場合の等価回路図である。 １……入力端子、２……PUT、３……抵抗、４……Ｎ型
半導体基板、５……Ｐ型拡散層、６……Ｎ型拡散層、７
……N+拡散層、８……酸化膜、９……保護電圧入力端
子、10……抵抗、12……Pch MOS Tr、13……Nch MOS T
r、14……ツェナダイオ−ド、15……ショックレーダイ
オ−ド FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention;
Fig. 2 is a cross-sectional view of a semiconductor chip according to the first embodiment, Fig. 3 is an equivalent circuit diagram showing a second embodiment according to the present invention, Fig. 4 is an equivalent circuit diagram when Pch and Nch MOS Tr are used as a first example according to the prior art, Fig. 5 is an equivalent circuit diagram when Zener diodes are used as a second example according to the prior art, and Fig. 6 is an equivalent circuit diagram when Shockley diodes are used as a third example according to the prior art. 1... Input terminal, 2... PUT, 3... Resistor, 4... N-type semiconductor substrate, 5... P-type diffusion layer, 6... N-type diffusion layer, 7...
……N + diffusion layer, 8……Oxide film, 9……Protection voltage input terminal, 10……Resistor, 12……Pch MOS Tr, 13……Nch MOS T
r, 14...Zener diode, 15...Shockley diode
Claims (2)
又は出力端子と電源との間にアノード及びカソードが接
続されたPUTを有し、該PUTのゲートには前記電源の電圧
以上で、前記内部回路のブレークダウン電圧以下の電位
を印加することを特徴とする入出力保護回路。[Claim 1] An input/output protection circuit comprising a PUT having an anode and a cathode connected between an input terminal or output terminal connected to an internal circuit to be protected and a power supply, and a potential higher than the voltage of the power supply and lower than the breakdown voltage of the internal circuit is applied to the gate of the PUT.
間にポリシリコン又は拡散で形成された抵抗を設けたこ
とを更に特徴とする請求項（１）に記載の入出力保護回
路。2. The input/output protection circuit according to claim 1, further comprising a resistor formed of polysilicon or diffusion between the gate of said PUT and the input or output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2305346A JP3070095B2 (en) | 1990-11-09 | 1990-11-09 | Input/Output Protection Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2305346A JP3070095B2 (en) | 1990-11-09 | 1990-11-09 | Input/Output Protection Circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04177756A JPH04177756A (en) | 1992-06-24 |
| JP3070095B2 true JP3070095B2 (en) | 2000-07-24 |
Family
ID=17944009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2305346A Expired - Lifetime JP3070095B2 (en) | 1990-11-09 | 1990-11-09 | Input/Output Protection Circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3070095B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3644918A (en) | 1969-12-16 | 1972-02-22 | Detection Systems Inc | Integrating circuit using a programmable unijunction transistor |
| US3814987A (en) | 1972-12-21 | 1974-06-04 | Johnson Service Co | Overvoltage protection circuit |
-
1990
- 1990-11-09 JP JP2305346A patent/JP3070095B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3644918A (en) | 1969-12-16 | 1972-02-22 | Detection Systems Inc | Integrating circuit using a programmable unijunction transistor |
| US3814987A (en) | 1972-12-21 | 1974-06-04 | Johnson Service Co | Overvoltage protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04177756A (en) | 1992-06-24 |
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