JP3070754B2 - Semiconductor integrated circuit and layout and wiring method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for automatically inserting a buffer gate for delay adjustment with respect to a latch of a semiconductor integrated circuit and an automatic placement and routing technique that takes into account delay between latches.

[Conventional technology]

As a layout and wiring technique taking delay into consideration, as described in Japanese Patent Application Laid-Open No. 61-234470 as a first technique, a range is set so that the distance between latches is difficult to set, and the latch is installed within the range. A technique for shortening the delay by shortening the wiring length has been reported. As a second technique, as described in Japanese Patent Application Laid-Open No. 62-39024, a technique is described in which, after placement, a line length is predicted by an approximate solution of a Steiner tree, delay calculation is performed, and placement is modified interactively for a violating net. Have been.

[Problems to be solved by the invention]

The first technology and the second technology both relate to a technology for reducing delay by arranging gates close to each other to reduce the wiring length resistance between gates, thereby reducing the delay.

In recent large-scale LSIs, the chip area has been widened, and it is no longer possible to take sufficient delay measures only by considering the arrangement of the gates close to each other.

An object of the present invention is to adjust a delay by automatically inserting a buffer gate between wires to shorten a wire length between gates for a net having a long wire length that cannot be handled by the conventional technology. It is to enable a high-speed LSI layout.

[Means for solving the problem]

In order to achieve the above object, a virtual wiring length is calculated after placement to calculate a path delay, and for a violating net, a gate is inserted to adjust a delay value. As shown in FIG. 1, the inter-latch delay is the sum of delays D = d _{1 for} each gate (net) stage between latch 1 and latch 2.
+ D ₂ + d ₃ can be calculated. The delay of one stage of the gate is determined depending on the driving capability of the gate serving as the source, the load capacity of the gate serving as the sink, the wiring capacity, and the wiring resistance between the source and the sink, and can be expressed by the following equation. d =
_{d CL + d W = d C} + d L + d W (d C: circuit delay ... gate unloaded delay, d _L: increment due to the load to the load delay ... d _C, d _W: Delay due to wiring delay ... wiring) by these components When the net configuration (source gate, fan-out, etc.) is the same, the delay increases and decreases depending on the wiring length. In particular, the wiring delay (d _W ) is d _W = α × R × C = α × (rl) ×
(Cl) = α × r × c × l ² (R: resistance between source and sink, C:
Net load capacity, α: proportionality constant, r: resistance per unit length,
c: capacitance per unit, l: wiring length), and the wiring delay increases in proportion to the square of the wiring length as shown in FIG. However, on the other hand, the circuit load delay (d _CL ) becomes substantially constant when the load capacitance exceeds a certain range, so that the overall delay is in proportion to l ² . As shown in FIG. 3, from these characteristics, when the difference between the total wiring delay of each division when the wiring length is divided as shown in (2) and the wiring delay before division is larger than the circuit delay of one gate, wiring is performed. Is divided and a buffer gate is inserted, so that the delay can be reduced by x. Further, by inserting a plurality of gates as shown in (3), the delay can be increased by y by the total sum of the circuit load delays. The delay can be adjusted by inserting a gate in this manner. As a means for mounting this gate, a method of distributing spare virtual gates in advance on a chip and virtually arranging them on a chip, and incorporating this gate into a logic as a buffer gate if necessary, If necessary, move the gate that was already at that position to a different position within the physically mountable range, and then place the buffer gate and wire it in the logic.One way is to place the latch first. Before routing other gates, calculate the delay with virtual wiring in the middle, place buffer gates within the physically mountable range for the violated net, incorporate it into logic, and then place other gates The way to do is raised. The delay adjustment is enabled by these means.

[Action]

According to the present invention, a target delay between latches can be reduced by inserting a buffer gate at the center between latches for a MAX violation of delay. By arranging and wiring using these features, it is possible to take countermeasures against a violation of a wiring delay that was insufficiently handled by the distance between latches. Further, since the arrangement of the latches is not unnecessarily concentrated, channel congestion can be prevented, and unwired wiring can be reduced. As a mounting technique, by arranging spare gates in advance, it is not necessary to change the arrangement for insertion, and the processing can be simplified. In addition, the method of inserting after the placement can prevent the spare area from being reduced by the spare gate. The LSI thus created can operate at high speed.

In addition, according to the present invention, for a MIN violation of the delay, the delay can be increased by inserting a plurality of buffer gates so that the circuit load delay can be changed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a graph showing the relationship between the distance between the latches and the delay value as described above, and FIG. 3 (1) is a characteristic graph when there is nothing between the latches. (2) is a characteristic graph when one stage of the buffer gate 5 is inserted between the latches.
The x delay value is smaller than the x delay.
The position where the buffer gate 5 is inserted in one stage is limited to a certain range as shown in (4) depending on the characteristics. Beyond this range, the delay value will increase. Another method for increasing the size is to insert a plurality of buffer gates and increase the size as in (3). However, even in the case of (3), the number may become smaller depending on the number and the positional relationship of the buffer gates, so it is necessary to calculate each time. In FIG. 3, the distance 1 between the latches is equal to l ₁ + l ₂ after the buffer gate is inserted, but may not be equal in terms of changing the delay value. As described above, by inserting the buffer gate between the latches, it is possible to adjust the delay value according to the purpose. Next, FIG. 4 shows an example of a flow in which the delay due to the buffer gate insertion is taken into account in the automatic arrangement processing.
First, the arrangement processing of 401 is executed. Next, all the wiring net information is read (402). The read wiring net information determines a wiring net that needs to consider delay (403), and if necessary, based on the wiring result of 401, for example, by the Steiner tree method or the like. The virtual wire length is calculated (404), and the delay of this net is calculated based on this value (405), and it is determined whether the value is a constraint value (406). The wiring nets that need to consider the delay described above mainly include, for example, a clock net or a scan net that requires time timing. The net can be identified by, for example, adding a unique group to a part of the signal name or adding a flag for each net, and determining these. As a result, for the offending net, the buffer gate logic is added to the logical information file (407). However, logic is added only when logical information can be added physically and in implementation. Next, processing for actually arranging the buffer gate to which the logic is added is performed (408). At this time, regarding the number and location of the buffer gates, logic is added and arranged according to the characteristics described above so as to protect the delay. There are several possible arrangements. An example will be described with reference to FIG.

First, a spare gate area irrelevant to logic is set on the cell example 10 on the chip, and placement of general logic gates in this area is prohibited. It is desirable that this area be set evenly on the chip later. However, if there is an area where the latches are arranged concentratedly in a certain area due to the characteristics of the chip, a particularly large area is set in this area. And good. As a result of the arrangement on this chip, for example, when it is found that the delay is exceeded based on the wiring length of the latch 1 and the latch 2, as shown in FIG. -Search for a spare gate near the middle line of the line connecting the pins. In FIG. 5, the spare gate 8 corresponds to this. When the delay value is calculated from the virtual wiring when the corresponding spare gate is inserted as a buffer gate and it can be confirmed that the delay satisfies the constraint value, the spare gate 8 is fed back to the logic information and the The gate is actually placed at the position. In the spare gate area that is not used, no cells are actually arranged, so that power is not wasted. Further, since there is no need to move the cell which has already been inserted for inserting the buffer gate, the processing can be easily performed. In FIG. 5, the buffer gate insertion is one case. However, it is preferable to calculate the delay value from the virtual wiring when two or more buffer gates are inserted, and select the one with the smallest delay. . If the delay value does not meet the reference value, it is sufficient to connect the spare gates between the latches until the spare gates are filled, and at that time, the information may be fed back to the logic and actually placed. Further, when there are many delay violation nets, it is possible to perform optimization such as replacing the spare gate that is already in use with another spare gate within a range where the spare gate can be used. As another optimization method, as shown in FIG. 7, there is D as an optimum buffer insertion position between the latches 1 and 2, and when there is a spare gate 9 beside or near the D, the D is set to the position of the spare gate 9. And the spare gate 9 is arranged at the position D. As a buffer gate insertion method using only this method, a method is also conceivable in which a spare gate area is not set in advance, and an area that is empty in the initial arrangement is used as an insertion area. According to this method, the arrangement possible area increases, and the arrangement efficiency in the initial arrangement is improved. As another buffer gate insertion method,
At the time of the initial placement, the latch is first placed preferentially, and based on the result, delay calculation is performed with the virtual wiring length, and a buffer gate is inserted according to the principle described with reference to FIG. At this time, there is an advantage that the area of the buffer gate can be easily secured because only the latch is arranged on the chip. If other general gates are arranged after the buffer gate is inserted, complicated processing such as arrangement exchange becomes unnecessary. In the example described above, the interval between latches is between two points. However, as shown in FIG. 8, the same processing can be performed for a net having a plurality of latches. However, the insertion position of the buffer gate 15 is not determined by the method shown in FIG. 6; for example, a virtual branch position is assumed by the Steiner tree method or the like, and delay calculation is performed on the virtual wiring to determine a position satisfying the constraint. It is more effective to determine the virtual branch position in accordance with an algorithm for actually performing the wiring process, since an approximate solution is obtained. However, when actually wiring these nets, the shape of the wiring may change and the restrictions may not be observed.Therefore, delay calculation is performed again, and optimization processing such as reinserting the buffer gate and changing the position after wiring is performed. You may need to do it. As another means for adjusting the delay by inserting a buffer gate, for example, as shown in FIG.
Between 901 and 902, a buffer gate 903 having no meaning in the logical configuration is inserted into the logical information. An arrangement process is performed using this logical information. For example, if this arrangement result is as shown in FIG. 10, 901, 902, and 903 in FIG.
01,102,103. Based on this arrangement result, delay calculation is first performed with virtual wiring lengths 104 of 101 and 102. At this time, if there is no violation in this value, the gate of 903 is removed from the logical information, and if there is a violation, the virtual wiring lengths 105 and 106 are obtained from the gates 101, 103 and 102 and delay calculation is performed.
If the restrictions are kept, the logical information is left as it is. In this example, the number of buffer gates is one. For example, a plurality of buffer gates may be inserted, and the delay value may be increased one by one to calculate the delay value and feed back the logic information at the time when the constraint value is observed. According to this method, the buffer gate can be inserted without rearranging the gate, and the delay can be adjusted.

By performing the above-described processing in the automatic placement program, the logic designer can automatically perform the feedback implementation to the logic without performing the logic design in consideration of the delay.

〔The invention's effect〕

According to the present invention, it is possible to adjust the delay without changing the wiring position of the latch in response to the delay violation due to the wiring length, which was insufficient in the conventional technology. In addition, it is possible to alleviate the arrangement congestion, in which a large number of non-wirings are generated because the latches are too tightly arranged between the latches, and there is an effect of reducing the non-wiring. In addition, since these insertion processes can be analyzed by virtual wiring during the placement process and the gates can be automatically incorporated into the logic, it is not necessary for the logic designer to manually consider the logic at the time of logic generation, and automation is possible. By enabling the placement and wiring in consideration of these delays, it is possible to create an LSI that can operate at high speed.

[Brief description of the drawings]

1 is a diagram showing a delay between latches, FIG. 2 is a diagram showing a relationship between a wiring delay and a wiring length, and FIG. 3 is a diagram showing a relationship between a wiring delay and a wiring length when a buffer gate is inserted. FIG. 4 is a flowchart of the buffer gate insertion process in the automatic placement process, FIG. 5 is a chip cell array diagram having a spare gate area, FIG. 6 is a condition diagram for determining the buffer gate insertion position, and FIG. FIG. 8 is a diagram for optimizing a buffer gate insertion position, FIG. 8 is a diagram of an example of buffer gate insertion in a virtual wiring route by the Steiner tree method, FIG. 9 is a diagram showing a logical configuration diagram, and FIG. FIG. 10 is a diagram showing a gate arrangement result diagram. 1,2 ... Latch, 3,4 ... Gate, 5-7 ... Buffer gate, 8,9 ... Spare gate, 11-14 ... Latch, 15 ...
Buffer gate.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yoshihiko Tomoshige 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi, Ltd.Kanagawa Plant (72) Inventor Katsuki Suzuki 1-Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Inside the factory (72) Inventor Kenki Ishii 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Kanagawa Plant (72) Inventor Tetsuo Sasaki 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Kanagawa Plant (72) Inventor Toru Hiyama 1 Horiyamashita, Hadano City, Kanagawa Prefecture Inside the Hitachi, Ltd.Kanagawa Plant (72) Inventor Nagase Eight Daiichi Horiyamashita 1 1 Horiyamashita, Hadano City Hitachi Computer Engineering Within the company (72) Inventor Yukio Kikuchi 6-81, Onoe-cho, Naka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Software Engineering Co., Ltd. (56) References JP-A-64-42146 (JP, A) JP-A-63- 69262 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04

Claims (5)

(57) [Claims] In a method for arranging and wiring elements of a semiconductor integrated circuit, one or more buffer gates are inserted between a preceding element and a subsequent element to reduce a signal delay time (hereinafter referred to as delay) due to a wiring length of each section. In this method, the sum of the reduced wiring length delay and the delay caused by the buffer gate is made smaller than the delay before the buffer gate is inserted. Over and violate (below)
For a net that is called MAX violation), the gate located near the center between the elements is replaced with a buffer gate within the range where the gate can be physically inserted, and inserted into the net. A placement and routing method, wherein a gate is placed in another closest open area so as to comply with a delay reference without reducing the number of logic gates that can be placed on a chip. 2. A method of arranging and wiring elements of a semiconductor integrated circuit, wherein one or more buffer gates are inserted between a preceding element and a subsequent element to reduce a signal delay time (hereinafter referred to as a delay) by a wiring length of each section. In this arrangement, the sum of the reduced wiring length delay and the delay caused by the buffer gate is made smaller than the delay before the buffer gate is inserted. Calculate the delay, and for a net violating MAX, logically insert a buffer gate between the latches within the range where the gate can be physically inserted, place it near the center, and then By placing the remaining logic gates, the buffer gates can be inserted without shifting the already placed gates. Placement and routing method characterized by enforcing standards. 3. A method for arranging and wiring elements of a semiconductor integrated circuit, wherein one or more buffer gates are inserted between a preceding element and a subsequent element to reduce a signal delay time (hereinafter referred to as a delay) due to a wiring length of each section. In this arrangement, the sum of the reduced wiring length delay and the delay caused by the buffer gate is made smaller than the delay before the buffer gate is inserted. Create logical information by inserting one or more stages, perform placement processing based on this logical information, calculate the virtual wiring length based on the placement result, and perform delay calculation. Calculate the delay in the wiring assumed to be MAX, M
If there is no IN violation, the buffer gate logic is removed from the logical information, and if a violation is made, delay calculation taking into account the buffer gate is performed.If the constraint is adhered to, the logical information is left as it is. , Increase the buffer gate one by one, calculate the delay value,
A layout and wiring method, wherein a delay at the time when a constraint is obeyed is fed back to the logical information so that a delay can be adjusted without requiring rearrangement. 4. A placement and routing method according to any one of claims 1 to 3, wherein, when determining the buffer gate insertion position, when the latch net is a multi-pin net, the Steiner tree wiring is virtualized based on the placement result. And determining the center between the respective gates from the virtual wiring, and performing wiring in consideration of wiring such that the gate is located at the center of the wiring path. 5. The placement and routing method according to any one of claims 1 to 4, wherein the placement and routing processes are all automatically connected by a program so that the logic designer considers the delay in the logic design. A placement and routing method characterized in that it is not necessary to consider the insertion of a buffer gate.