JP3071438B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP3071438B2 JP3071438B2 JP2007556A JP755690A JP3071438B2 JP 3071438 B2 JP3071438 B2 JP 3071438B2 JP 2007556 A JP2007556 A JP 2007556A JP 755690 A JP755690 A JP 755690A JP 3071438 B2 JP3071438 B2 JP 3071438B2
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- recess
- bare chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路に関し、特に絶縁基板上にベ
アチップ搭載する構成をもつ混成集積回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit having a configuration in which a bare chip is mounted on an insulating substrate.
近年、装置の小型化への要求から回路の集積が大幅に
進められてきており集積規模が大きくなるにつれICで補
えきれない回路が多く発生する。そのためICの補助回路
として混成集積回路がますます必要性，重要性を増して
くる。混成集積回路は、絶縁基板（例えばセラミック基
板）上に導体膜，抵抗膜などを形成し能動素子であるI
C,トランジスタ，タイオード類，および受動素子である
コンデンサ，コイル，抵抗を搭載し種々の回路機能をも
たせ通信装置，コンピュータ用中央処理装置など数多く
の分野に応用されている。従来の混成集積回路は、絶縁
基板上にICをディスクリート部品あるいはペレット品で
搭載し、受動素子である抵抗およびコンデンサは厚膜・
薄膜で形成し、あるいはチップ部品で搭載する。In recent years, the integration of circuits has been greatly promoted due to the demand for miniaturization of devices, and as the scale of integration increases, many circuits cannot be covered by ICs. As a result, hybrid integrated circuits have become increasingly necessary and important as auxiliary circuits for ICs. A hybrid integrated circuit forms an active element by forming a conductive film, a resistive film, etc. on an insulating substrate (for example, a ceramic substrate).
It is equipped with C, transistors, diodes, and passive elements such as capacitors, coils, and resistors, has various circuit functions, and is applied to many fields such as communication devices and central processing units for computers. In conventional hybrid integrated circuits, ICs are mounted as discrete parts or pellets on an insulating substrate.
Formed in thin film or mounted with chip components.
上述した従来の混成集積回路は、ディスクリート部品
をベアチップ部品にかえて搭載することにより集積化し
たが、ベアチップは、片面搭載しかできず片面は、すべ
てディスクリート部品になるため、基板占有面積が大き
くなり小型化の妨げになる。又、ベアチップ搭載面にデ
ィスクリート部品を搭載する時は、ベアチップ保護コー
ティングの凹凸があるため半田印刷ができないなどの欠
点がある。The above-mentioned conventional hybrid integrated circuit was integrated by mounting discrete components instead of bare chip components, but bare chips can only be mounted on one side and all sides are discrete components, so the board occupation area increases. This hinders miniaturization. In addition, when discrete components are mounted on the bare chip mounting surface, there is a drawback that solder printing cannot be performed due to the unevenness of the bare chip protective coating.
本発明の混成集積回路は、少なくとも基板の片面にく
ぼみを設け、そのくぼみの中に基板面から突出しないよ
うにベアチップを搭載し、このくぼみを設けた側の面に
半田印刷を施し、ディスクリート部品、またはチップ部
品が搭載され、かつ、他方の面にはベアチップが搭載さ
れた構造を有することを特徴とする。The hybrid integrated circuit of the present invention is provided with a recess on at least one side of a substrate, a bare chip is mounted in the recess so as not to protrude from the substrate surface, and solder printing is performed on a surface on which the recess is provided, and a discrete component is provided. Or a chip component is mounted thereon, and a bare chip is mounted on the other surface.
次に本発明について図面を参照して説明する。第１図
は、本発明の一実施例の上面図であり、第２図は、本発
明の一実施例の断面図である。片面に本発明によるくぼ
みをもった絶縁基板９のくぼみに、ペレット７をAgペー
スト４でマウントを行い金線８でボンディングしてプリ
コート樹脂６をくぼみに流し込む。ただし、はみださな
いよう注意する。くぼみのある面のマウント，ボンディ
ング，プリコート作業完了後にくぼみのない面のペレッ
ト７を同様にAgペースト４でマウントしボンディングを
行う。プリコート樹脂６塗布後くぼみのある面に半田ペ
ースト５にて印刷を行い、ミニフラット1,チップコンデ
ンサ2,ミニモールド３を搭載する。くぼみのある面にデ
ィスクリート部品を搭載後にくぼみのない面を半田ペー
スト５を同様に半田印刷してミニフラット1,チップコン
デンサ2,ミニモールド３を搭載する。Next, the present invention will be described with reference to the drawings. FIG. 1 is a top view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view of one embodiment of the present invention. The pellet 7 is mounted on the recess of the insulating substrate 9 having the recess according to the present invention on one side with the Ag paste 4 and bonded with the gold wire 8 to flow the precoat resin 6 into the recess. However, be careful not to protrude. After the mounting, bonding, and precoating of the recessed surface are completed, the pellet 7 on the surface without the recess is similarly mounted with the Ag paste 4 and bonded. After the precoat resin 6 is applied, printing is performed on the recessed surface with the solder paste 5, and the mini flat 1, the chip capacitor 2, and the mini mold 3 are mounted. After mounting the discrete component on the recessed surface, a solder paste 5 is similarly solder-printed on the surface without the recess to mount the mini flat 1, the chip capacitor 2, and the mini mold 3.
以上説明したように本発明は、ベアチップ搭載のバイ
ブリットICで基板片面にくぼみを設けてベアチップをそ
のくぼみに埋めこむことにより、もう一方の面もベアチ
ップ搭載ができ、それによって高密度化，高集積化，小
型化できる効果がある。As described above, according to the present invention, by providing a recess on one side of a substrate using a bi-brit IC mounted with a bare chip and embedding a bare chip in the recess, the other side can also be mounted with a bare chip, thereby increasing the density and increasing the density. There is an effect that integration and miniaturization are possible.
第１図は本発明の一実施例の上面図、第２図は本発明の
一実施例の断面図である。 １……ミニフラット、２……チップコンデンサ、３……
ミニモールド、４……Agペースト、５……半田ペース
ト、６……プリコート樹脂、７……ペレット、８……金
線、９……絶縁基板。FIG. 1 is a top view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view of one embodiment of the present invention. 1 ... mini flat, 2 ... chip capacitor, 3 ...
Mini-mold, 4 ... Ag paste, 5 ... Solder paste, 6 ... Precoat resin, 7 ... Pellets, 8 ... Gold wire, 9 ... Insulating substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田畑 義郎 群馬県吾妻郡中之条町大字伊勢町乙872 光山電気工業株式会社内 (56)参考文献 特開 昭58−28889（ＪＰ，Ａ) 特開 昭64−28855（ＪＰ，Ａ) 特開 昭61−198769（ＪＰ，Ａ) 実開 昭63−170971（ＪＰ，Ｕ) ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yoshiro Tabata 872 Ose, Ise-cho, Nakanojo-machi, Agatsuma-gun, Gunma Prefecture (56) References JP-A-58-28889 (JP, A) JP-A Sho 64-28855 (JP, A) JP-A-61-198769 (JP, A) JP-A-63-170971 (JP, U)
Claims (1)
のくぼみの中に基板面から突出しないようにベアチップ
を搭載し、このくぼみを設けた側の面に半田印刷を施
し、ディスクリート部品、またはチップ部品が搭載さ
れ、かつ、他方の面にはベアチップが搭載された混成集
積回路。An indentation is provided on at least one surface of a substrate, a bare chip is mounted in the indentation so as not to protrude from the substrate surface, and a surface on which the indentation is provided is subjected to solder printing, and a discrete component or chip is provided. A hybrid integrated circuit on which components are mounted and a bare chip is mounted on the other surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007556A JP3071438B2 (en) | 1990-01-16 | 1990-01-16 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007556A JP3071438B2 (en) | 1990-01-16 | 1990-01-16 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03211763A JPH03211763A (en) | 1991-09-17 |
| JP3071438B2 true JP3071438B2 (en) | 2000-07-31 |
Family
ID=11669075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007556A Expired - Fee Related JP3071438B2 (en) | 1990-01-16 | 1990-01-16 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3071438B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2725637B2 (en) * | 1995-05-31 | 1998-03-11 | 日本電気株式会社 | Electronic circuit device and method of manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828889A (en) * | 1981-08-14 | 1983-02-19 | 株式会社日立製作所 | Hybrid integrated circuit board |
| JPS6428855A (en) * | 1987-07-23 | 1989-01-31 | Nec Corp | Package for semiconductor device |
-
1990
- 1990-01-16 JP JP2007556A patent/JP3071438B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03211763A (en) | 1991-09-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |