JP3073221B2 - Image area identification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to an image area identification apparatus applied to a digital copying machine, a facsimile, a scanner, and the like, and is particularly characterized in that each area of an input image is automatically identified whether or not each area has been subjected to halftone processing. The present invention relates to an image area identification device.

[0002]

[Prior art]

For example, in a digital copying machine, an original image is read in a minute area, that is, for each pixel using a CCD (Charge Coupled Device) image sensor or the like, and an analog electric signal obtained at the output of the image sensor is converted into an A / D ( (Analog / Digital) conversion, the digital signal obtained is subjected to various processes, and the signal is applied to a recording device to obtain a copy image.

By the way, in a recording device used for this type of device,
Since it is difficult to change the density level for each recording pixel,
In general, recording / non-recording of binary or multilevel recording is performed. However, since a document sometimes includes a halftone image such as a photograph, it is necessary to reproduce the halftone image. As a method of expressing a halftone using a recording apparatus that performs binary or multi-level recording, a dither method, a density pattern method, a sub-matrix method, an error diffusion method, and the like have been conventionally proposed, and these methods are used. For example, a halftone image can be reproduced.

However, when performing halftone processing, a relatively favorable copy image can be obtained when the original image density changes slowly as in a photograph, but the original image density changes binary as a character. In such a case, the outline of the copy image is blurred and the characters are difficult to read, and stains on the background of the document appear in the copy image, so that the copy quality is significantly reduced.

For a document image such as a character, without performing halftone processing,
If a simple binary or multi-level processing is performed, a preferable copy is obtained. Therefore, if a switch for specifying the presence or absence of the halftone processing is provided, a preferable copy mode can be selected by the judgment of the operator according to the type of the document.

However, there are quite a few cases where halftone images such as photographs and binary images such as characters are mixed in one document, such as pamphlets. In such a case, if the binary or multi-value mode is selected, the quality of the photograph is reduced, and if the halftone mode is selected, the quality of the characters is reduced.

Incidentally, this type of digital copying apparatus has another disadvantage. In other words, when an image is read in small pixel units using a line sensor or the like, if the density change on the document has periodicity, interference between the cycle (pitch) and the array pitch (sampling cycle) of the image reading sensor will occur. And
Moire may occur on the recorded image. For example, in the case where halftone printing is performed on a document as well, the density change on the image has periodicity, and thus moire occurs due to interference between the cycle of the density change and the sampling cycle of the reading sensor.

For example, if the resolution of the image reading sensor is 400 dpi, halftone printing at a density close to the resolution, ie, 133 lines (about 10.5 pixels / mm) to 200 lines (about 16 pixels / mm) When the density is in the range, moire is likely to occur in the read signal. Of course, moiré occurs even at other densities, but particularly at the above densities, the variation in signal is large due to the occurrence.

The dot printing itself is a kind of pseudo halftone expression, and the density change in pixel units is a binary value of 1/0 (recording / non-recording). In halftone printing, the average density when the entire pixel set is viewed is changed in multiple stages due to the pitch change of the halftone dots and the change in the size of the halftone dots, thereby expressing the halftone density. Therefore, if the original image of halftone printing is copied without considering the problem of moiré, it is necessary to reproduce the halftone image on the recorded image by performing binary processing on the signal, and to make a preferable copy. Can be. However, in practice, moiré occurs as described above for a document image printed in halftone dots at a specific density, and the copy quality is significantly reduced.

On the other hand, when the image reading signal is changed to a binary or multi-level signal by performing halftone processing, an average change in the density of a plurality of pixels, a change in a threshold level, and the like are performed in the process of processing. Moire does not occur in the copied image, or the influence is reduced. In this case, the density of the copy image is represented by a halftone by a halftone dot, but the halftone dot on the copy is not a direct reproduction of the halftone dot on the original, but is a halftone dot generated by halftone processing unique to a copying machine. It is.

Therefore, when an image printed by halftone printing or an image copied by halftone processing by a digital copying machine is a document, binary recording is performed in pixel units, but a copy mode for performing halftone processing is set. It is preferable to select.

Further, as described above, a halftone process such as a simple binary or multivalued text portion and a dither method may be performed for a halftone dot portion. For this reason, a region division method may be considered. For example,
As disclosed in JP-A-63-279665, if a halftone area is detected and halftone processing is applied to the halftone area and simple binarization is performed for the other halftone areas, characters and halftone photographic portions are output as good images. Can be

In the halftone dot area detection system disclosed in Japanese Patent Application Laid-Open No. 63-279665, a two-dimensional array pattern of input image information is compared with a predetermined pattern to detect recorded dots and non-recorded dots. And whether the input image information is a halftone dot pattern based on the detection result.

In the halftone-processed image, recording dots (for example, black pixels) and non-recording dots (for example, white pixels) are alternately and repeatedly arranged at predetermined bits and intervals. Accordingly, a state in which a recording pixel existing at a certain position and a non-recording pixel existing therearound are in a predetermined arrangement pattern, or a non-recording pixel existing at a certain position and a recording pixel existing therearound are a predetermined arrangement pattern If the state of the array pattern appears repeatedly, it can be considered that the pixel has been subjected to halftone processing. That is, the target pixel is sequentially moved, and for each target pixel, the image information of the two-dimensional region including the target pixel and its surrounding pixels is compared with a predetermined recording dot detection pattern and a non-recording dot detection pattern. It is possible to identify whether or not the input image is a dot pattern.

However, when a halftone-processed image is actually read by an image scanner, the image pattern of the read signal greatly changes according to the density of the image, and an error often occurs in halftone dot identification. . That is, in halftone printing, the density is represented by the size of the area of the halftone dot in a predetermined small area. Therefore, when the image density changes, the shape of the halftone dot changes greatly. In particular, if the dot density is near 50%, the recording dots (for example, black pixels) or non-recording dots (for example, white pixels) that constitute the halftone dot may be connected to each other and become continuous. In such a case, neither black dots nor white dots can be detected in many cases.

When the threshold level for binarizing the image information into the recording pixel level and the non-recording pixel level is adjusted, the dot density becomes
Identification errors in the case of 50% can be reduced. However, in that case, the identification error increases when the dot density is higher or lower than 50%.

Therefore, at least two types of thresholds are set, and a circuit for detecting a recording dot and a circuit for detecting a non-recording dot refer to image information binarized by different thresholds, A halftone dot pattern is identified based on both the detection result of the recording dot and the detection result of the non-recording dot.

In the case of a halftone image, a signal read by an image scanner is generally as shown in FIG. From this, it can be seen that the peak height, valley depth, and duty of the signal change according to the density.

Here, focusing on a signal having a density level of 50%, it can be seen that the peak height and the valley depth of the signal change depending on the position of the image.

When a signal having a density of 50% is binarized by the threshold value TH1, the peak is larger than TH1 and the valley is smaller than TH1 in the first part Pa, and therefore, the peak is recorded in the binarized signal. Pixels and valleys appear as non-recording pixels, and in the later part Pb, both peaks and valleys
Since it is larger than TH1, non-recorded pixels do not appear in the binarized signal. That is, when binarized by TH1, the first part P
In a, a halftone dot (recording dot) can be detected from the arrangement pattern of the recording pixels and the non-recording pixels, but a halftone dot cannot be detected from the subsequent portion Pb.

In the case where this signal is binarized by the threshold value TH2, in the first part Pa, since neither the peak nor the valley is smaller than TH2, no recording pixel appears in the binarized signal, Later part
In Pb, since the peak is larger than TH2 and the valley is smaller than TH1, the peak appears as a recording pixel and the valley as a non-recording pixel in the binarized signal. Therefore, when binarized by TH2, the first part Pa
However, in the subsequent portion Pb, a halftone dot (non-print dot) can be detected from the arrangement pattern of the recording pixels and the non-record pixels.

That is, if the threshold value TH1 is used to detect a halftone dot composed of recorded dots and the threshold value TH2 is used to detect a halftone dot composed of non-recorded dots, the density becomes 5%.
Even for 0% halftone pixels, either halftone dots of recorded dots or non-recorded dots are detected. When the density is as low as 20%, the halftone dot of the recording dot is detected by the threshold value TH1. When the density is as high as 80%, the halftone of the non-printing dot is detected by the threshold value TH2. A point is detected.

[0023]

[Problems to be solved by the invention]

However, in the above-described conventional technology, characters, line drawings, and the like having a density near the binarization threshold level are liable to cause breaks in lines, such as binarization, and easily become nuclei of halftone dots. Further, since a plurality of threshold levels are provided, there is a disadvantage that the circuit becomes complicated.

If one or more halftone dots exist in the predetermined area n × m matrix area, the n × m matrix is regarded as a halftone dot block. 1 in
When the number is more than one, for example, a part of a character or a stain on the background is detected as one dot, and the dot is often erroneously determined as a halftone dot region.

Further, for each unit of a halftone block (when one or more halftone dots exist), two main scans and two sub scans are used, and 2 ×
When three or more halftone dots are set in the halftone block area of 2
Although the halftone block of No. 2 was used as a halftone area, as described above, a part of a character or dirt on the background may be detected as one dot, which may be erroneously determined as a halftone area. there were.

Further, in the prior art, when a recorded dot portion and a non-recorded dot of a halftone dot portion do not appear as a dot due to moire of a halftone dot, the halftone dot cannot be regarded as a halftone dot. weak. For example, there is a drawback that erroneous detection often occurs because an isolated point noise having a low density can be easily regarded as a halftone dot.

Conventionally, when a halftone original having the same pitch and size is read in the main and sub-scanning directions, the reading in the main scanning direction and the sub-scanning direction depends on the reading method and reading characteristics of the system. The concentration width (MTF) generally differs. Further, depending on the shape of the halftone dot discrimination pattern, a problem such as a region including a 45 ° line or the like is likely to be erroneously recognized.

The present invention solves the above-mentioned drawbacks of the related art, can improve the detection rate of a halftone dot area, and can reduce the rate of erroneously detecting an area that is not a halftone dot area as a halftone dot area. It is an object to provide an image region identification device.

[0029]

[Means for Solving the Problems]

The present invention provides a plurality of density comparing means for comparing whether the difference between the density of the pixel of interest and the density of the plurality of peripheral pixels is equal to or greater than a predetermined value different depending on each position of the plurality of peripheral pixels, If the difference between the density of the pixel of interest and the density of the plurality of peripheral pixels based on the comparison results of the plurality of density comparison units is equal to or greater than a predetermined value that is different depending on each position of the plurality of peripheral pixels, the pixel of interest is determined. A dot pixel detecting means for detecting the pixel as a dot pixel.

According to the present invention, the difference between the density of the target pixel and the densities of the plurality of peripheral pixels is compared with a predetermined value, and if all the differences are equal to or larger than the predetermined value, the target pixel is detected as a halftone pixel. In the configuration, an area other than a halftone area including a 45 ° oblique line due to a difference in MTF characteristics between the main scanning direction and the sub-scanning direction, such that a predetermined value is changed according to each position of a plurality of peripheral pixels. Can be reduced as a halftone dot region.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a configuration of a mechanism of a digital copying machine of one type embodying the present invention. Referring to FIG. 2, this copying machine includes a scanner 1 disposed above the apparatus and a printer 2 disposed below the apparatus.

Reference numeral 26 denotes a contact glass on which an original is placed. The scanner 1 reads an image of a document placed on the contact glass 26 while scanning the document. The sub-scanning is mechanical, and the carriage provided in the scanner moves in the horizontal direction in FIG. 2 by driving the electric motor MT. The reflected light from the manuscript
An image is formed on the fixed image reading sensor 10 via various mirrors and lenses. The image reading sensor 10 is a CCD line sensor. In FIG.
Read cells are arranged in one row. In this example, when the copy magnification is 1.0, the resolution is 16 pixels per 1 mm after the original. The main scanning is electrically performed by a CCD shift register provided inside the image reading sensor 10. The main scanning direction is a direction in which read cells are arranged, that is, a direction perpendicular to the plane of FIG. A signal obtained by reading the original image through the scanner 1 is sent to the printer 2 after being subjected to various processes. The printer 2 performs binary recording according to the signal.

The printer 2 includes a laser writing unit 25, a photosensitive drum 3, a charging charger 24, a developing device 12, a transfer charger 1
4. Separate charger 15, fixing device 23, etc. are provided.
The printer 2 does not differ from the conventional laser printer in particular, so only the operation will be briefly described.

The photosensitive drum 3 rotates clockwise in FIG. Then, the surface is uniformly charged to a high potential by the urging of the charging charger 24. The charged surface is irradiated with a laser beam modulated by a binary signal corresponding to an image to be recorded. The laser beam repeatedly scans the photosensitive drum 3 in the main scanning direction by mechanical scanning. The potential of the charged surface of the photosensitive drum 3 changes when it is irradiated with laser light. Therefore, a change in the laser beam, that is, a potential distribution according to the image to be recorded occurs on the surface of the photosensitive drum 3. This potential distribution is an electrostatic latent image. When the portion where the electrostatic latent image is formed passes through the developing device 12, toner adheres according to the potential, and the electrostatic latent image is developed into a toner image, that is, a visible image. This visible image is stored in the paper feed cassette 4 or 5
And is transferred onto the transfer paper sent to the photosensitive drum 3 from the printer, and is transferred to the transfer paper by the urging of the transfer charger 14. The transfer sheet on which the image has been transferred is discharged to a discharge tray 22 through a fixing device 23.

FIG. 3 shows a configuration of an electric circuit of the digital copying machine shown in FIG. Referring to FIG. 3, the scanner 1 includes an image reading sensor.
10, scanning control unit 20, amplifier 30, A / D (analog / digital) converter 40, halftone processing unit 55, binarization processing unit 65, area determination unit 70, operation control unit 80, output control unit 90 , Motor driver MD and so on.

The scanning control unit 20 exchanges signals with the printer 2, performs main scanning control, sub-scanning control, and generates various timing signals. Various timing signals are generated in synchronization with the scanning timing. Various status signals, a print start signal, a copy magnification signal, and the like are sent from the printer 2 to the operation control unit 20. The scanning control unit 20 sends a scanning synchronization signal, a status signal, and the like to the printer 2. By driving the motor MT, the scanner 1 is mechanically scanned to perform sub-scanning.

The image reading sensor 10 includes a large number of reading cells, a CCD shift register, and the like, like a general CCD line sensor. When the scanning control unit 20 outputs a sub-scanning synchronization signal, signals accumulated in a large number of reading cells of the image reading sensor 10
Each bit of the D shift register is transferred at once. After that, the signal of the CCD shift register is shifted in synchronization with the main scanning pulse signal, and the image signal held in the register appears at its output terminal for each pixel as a serial signal (a in FIG. 3: Hereinafter, signals generated from image signals are shown in parentheses).

The amplifier 30 performs amplification of the image signal (a), noise removal, and the like. The A / D converter 40 converts an analog image signal into a 6-bit digital signal. Although not shown in the drawing, the digital signal obtained by the A / D converter 40 is subjected to various types of conventionally known image processing such as shading correction, background removal, black-and-white conversion, and the like. Bits, ie
It is output as a digital image signal (b) of 64 gradations. This digital image signal (b) is applied to a median filter 50,
It is applied to the MTF correction unit 60.

The digital image signal (c) processed by the median filter 50 is applied to a halftone processing unit 55. The halftone processing unit 55 is a circuit that converts the 6-bit digital image signal (c) into a binary signal (e) containing halftone information by a sub-matrix method.

A circuit for performing the halftone processing by the sub-matrix method is known, and in this embodiment, a special circuit is not used, and thus a specific configuration and operation are omitted. Note that, other than the sub-matrix method, halftone processing using a dither method or a density pattern method may be performed.

The median filter 50 is necessary because it has the effect of smoothing the image information in the n × m matrix and reducing the moiré of the halftone image as described above. Further, a circuit relating to the median filter 50 is also known, and in this embodiment, a special circuit is not used, and thus a specific configuration and operation are omitted.

Further, the digital image signal (d) processed by the MTF correction unit 60 is applied to a binarization processing unit 65 and an area determination unit 70. The binarization processing unit 65 compares the MTF-corrected input image signal with a predetermined fixed threshold level, and outputs a binary signal (f) according to the magnitude of the level. Therefore, the process performed here is a simple binarization process, and the signal (f) does not include information on the intermediate density of the original image.

The halftone processing unit 55 and the binarization processing unit 65 assume the case of printer output or white / black binary, so the description has been made as described above. Is a multi-value printer such as a ternary or quaternary printer,
At 55, a multi-valued dither method is used, and at the binarization processing section 65, multi-value output is performed by simple multi-value conversion having multiple stages of threshold levels. Note that the multi-value dither method and the simple multi-value conversion are not important points in the present invention, and can be implemented by a known technique, and thus the specific configuration and operation are omitted.

As will be described later, the area determination unit 70 is a circuit for determining whether or not document image halftone information is included, and outputs a binary signal (g) corresponding to the determination result to the output control unit 90. I do.

The operation control unit 80 gives the output control unit 90 a mode signal (i) corresponding to the operation of the mode key on the operation board.

The output control unit 90 outputs a binary signal output from the halftone processing unit 55 in accordance with the mode signal (i) supplied from the operation control unit 80 and the binary signal (g) supplied from the area determination unit 70. The image signal (e), the binary image signal (f) output by the binarization processing unit 65 or a signal of a predetermined level (white level) is selectively output. This signal (a) is given to the printer 2 as a recording signal. The printer 2 modulates the laser light according to the binary signal and performs recording.

FIG. 1 shows a configuration of the area determination unit 70 shown in FIG. This figure is also a dot area detection block diagram.

The input image data Da in FIG. 1 is the same as the correction data (d) from the MTF correction unit 60 in FIG.

The reason why the MTF correction signal is input to the area determination unit 70 is as shown in FIG.
This is because halftone dots may not be resolved due to the phase difference between the CCD pitch and the halftone dot if the input data remains as shown in FIG.

That is, at the density of 20% in FIG. 4, there are halftone dots with high density and halftone with low density in the halftone density of the input document, and at 50% density, halftone dots appear in the intermediate density portion. However, there are cases where the density ratio of halftone dots is large and small, and the density is 80%
In some cases, the density of the white nucleus of the halftone dot may be low or high.

As will be described later, in the present embodiment, the determination is made based on whether or not a black nucleus or a white nucleus of the halftone dot exists in setting a criterion for determining whether or not the halftone dot exists. The halftone dot density information is a very important point.

Therefore, the first feature of the present embodiment is that a predetermined MTF is corrected for input data.

In other words, as described above, it is assumed that there is not much difference between the core density and the peripheral density of the halftone dot caused by the phase difference between the input halftone dot pitch and the read pit of the CCD 10, and the MTF is corrected. As shown in the data after the MTF in FIG. 4B, by expanding the density difference between the core density of the halftone dot and the peripheral density, the halftone dot detection described later is facilitated, and the detection accuracy is improved.

FIG. 5 shows an example of MTF correction, in which pixels corresponding to a 3 × 3 matrix are corrected at the time of main and sub-scanning using weight coefficients as shown in FIG.

Note that this coefficient is merely an example, and other coefficients may be used, and can be changed by a mode magnification or the like.

FIG. 6 shows a block diagram for setting the MTF coefficients shown in FIG. In the figure, reference numerals 61a and 61c denote FIFO (first-in first-out) memories, which are used for delaying one line in the main scanning direction and two lines.
The delay of the line is realized, and together with the current line, three line data are present on the same time axis. The delay in the main scanning direction of each line is realized by F / Fs (flip flops) 61b, 61d, 61e, and 61f.

With this configuration, image data corresponding to the coefficients of the matrix shown in FIG. 5 can exist on the same time axis.

That is, the image data corresponding to M1 in FIG. 5 is FIG. 6b, the image data corresponding to M2 is FIG. 6a, the image data corresponding to M3 is FIG. 6c, and the image data corresponding to M4 is Is FIG. 6e, and the image data corresponding to M5 is FIG. 6d.

The logic circuit 61g realizes the sum a + b of the data of a and b, the logic circuit 61h realizes the sum d + e of the data of d and e, and the logic circuit 61i realizes the sum (a + b + d + e) of (a + b) and (d + e). , A logic circuit 61k realizes a sum 3 × c of c and 1-bit shifted and doubled 2c, and furthermore, (a + b + d +
e) through an inverting circuit 61j, and-(a + b +) in a logic circuit 61k.
d + e) is input by one bit shift to-(a + b + d +
e) By taking the sum of / 2 and 3 × c, 3 × c− (a + b + d
+ E) / 2 (logic circuit 611) to obtain M
TF correction is realized. This 3 × c− (a + b + d +
e) / 2 is the d output of the MTF correction unit 60 in FIG.

The area determination section 70 described later describes a density pattern matching method based on a density difference between the density of the target pixel and the density of peripheral pixels based on the MTF correction signal d.
No. 65, input image information is binarized at a certain threshold, and input image information based on the binarized signal is also converted to MTF.
, The density amplitude of the halftone dot is widened as described above, and the density difference can be easily detected. In addition, in binarization, there is an effect that black dots and white dots are easily output.

The halftone dot area detection will be described with reference to FIG. Since the details of each block will be described later, the outline will be described here.

First, in order to determine whether a pixel is a halftone dot, it is necessary to have an area of image data on the same time axis.

Here, X is used to indicate the main scanning direction of the scanner 2.
And the Y signal is used to indicate the sub-scanning direction. Therefore, the Y-direction delay circuit 71 and the X-direction delay circuit 72
Thus, a certain area is present on the same time axis.

The next-stage white level detection circuit 73 and black level detection circuit
74 detects a white nucleus or a black nucleus of a halftone dot.In order to determine whether or not the pixel of interest is a halftone nucleus, a density difference from surrounding pixels is detected. If there is, the nucleus of a white or black halftone dot is determined, and a determination is made by the pattern matching circuit 75 as to whether or not the state of the halftone dot nucleus matches a prescribed pattern.

When one or more halftone dots are present in the determined n × m area, a halftone block detection circuit (1) 76 that makes the n × m area a halftone block, When there are two or more halftone dots in the area, a halftone block detection circuit (2) 77 is provided for making the nxm area a halftone block, and two or more halftone dots among a plurality of halftone dot blocks are provided. When point detection block, one or more halftone dot detection block, and halftone dot non-existence block exist at a certain ratio,
A halftone dot area detection circuit 78 for converting the above halftone dot blocks into halftone dot areas is provided.

The Y-direction delay circuit 71 will be described.

As shown in FIG. 7, the Y-direction delay circuit 71
It consists of 04. Note that this circuit is an example, and the circuit differs depending on the maximum size of a pattern used for pattern matching. FIG. 8 shows the timing. Hereinafter, the Y-direction delay circuit 71 will be described using these.

First, control symbols for controlling the timing relationship will be described with reference to FIG. In the figure, A represents a document, and a control symbol is a signal FG indicating an effective document width in the sub-scanning direction (Y direction).
ATE, signal LGA indicating the effective document width in the main scanning direction (X direction)
TE, a signal LSYNC for synchronizing reading in the main scanning direction, and a reference signal CL (not shown) for the entire system.
Consists of K. That is, in the figure, the document information is read line by line in the main scanning direction in synchronization with LSYNC, and FGATE, LGATE
Are valid data when both are “H”. Then, the read image data is output from the CCD 10 one pixel at a time in synchronization with the CLK.

In FIG. 8, after FGATE goes “H”, the image data read in synchronization with the first LSYNC is synchronized with CLK while the period in which LGATE is “H” is the first line of effective image data D1. Then, the data is stored in the memory 101 one pixel at a time. And the next SLYNC
The second line of image data D2 obtained in synchronization with the memory 101 is also stored in the memory 101.
The image data D1 of the first line stored in the memory 102 is stored as image data delayed by one line in the memory 102 one pixel at a time in synchronization with the CLK.

Hereinafter, the image data is scanned by scanning the third line, the fourth line, etc.
When D3, D4,... Are obtained, the outputs are delayed in the memories 103 and 104, and when the fifth line is read, the nuclear outputs of the memories 101 to 104 are as follows: the output of the memory 104 is D1, the output of the memory 103 is D2, and the memory 102 Is D3, the output of the memory 101 is D4, and this is combined with the currently read image data D5 of the fifth line.
Line image data is obtained at the same time.

Next, the X-direction delay circuit 72 will be described.

The X-direction delay circuit 72 comprises five blocks as shown in FIG. 10, and each block is composed of five flip-flop groups (111 to 115, 116 to 120, 121 to 125, 126 to 130, 131 to 1).
35). Note that this circuit is an example, and the circuit differs depending on the maximum size of a pattern used for pattern matching. Each block includes five lines of image data Db1 to Db5 obtained by the Y-direction delay circuit 71, respectively.
And performs the same operation, so the image data
Only the block that processes Db1 will be described. Figure 1
1 indicates the operation timing of the circuit.

Hereinafter, the X-direction delay circuit 72 will be described with reference to these drawings.

In FIG. 11, when the image data of the fifth line is read, the image data D 1 of the first line is output from the memory 104 one pixel at a time in synchronization with the CLK. The image data D1-1 of the first pixel on the first line is a flip-flop 111.
Is input to the flip-flop 111, and the value is stored. And the image data of the second pixel
When D1-2 is input, the flip-flop 111 stores the value. At this time, the image data D1-1 of the first pixel already stored is delayed by one pixel in synchronization with the CLK. The data is stored in the flip-flop 112 as data.

Hereinafter, the image data D1-3, D1− of the third pixel, the fourth pixel,.
4 are delayed by the flip-flops 113 to 115, and when the image data of the sixth pixel is input, the outputs of the flip-flops 111 to 115 become the output of the flip-flop 115. D1-1, the output of flip-flop 114 is D1-2, the output of flip-flop 113 is D1-3, the output of flip-flop 112 is D1-4, and the output of flip-flop 111 is D1-5. And image data D1-6 of the sixth pixel currently input, image data for six pixels in the same line is obtained at the same time.

Accordingly, when the five blocks are combined, as shown in FIG. 12, image data Dc1 to Dc of 5 lines × 6 pixels, a total of 30 pixels,
c30 is obtained at the same time.

The X-direction delay circuit 72 provides image data Dc1 to Dc30 of 5 lines × 6 pixels, that is, a total of 30 pixels. Of these, pattern matching is performed using several pixels to detect halftone dots.

FIGS. 13 (a) to 13 (e) show examples of patterns used for pattern matching.
Reference numeral 15 is a pixel of interest at present, and a pixel surrounded by a solid-line rectangle is a peripheral pixel. For example, in the pattern of FIG. 7A, the target pixel is Dc15, and the peripheral pixels are Dc2 to Dc5, Dc7, Dc12, Dc13, Dc18, Dc19, Dc24, and Dc26 to Dc29.
14 pixels. Then, the pattern matching indicates that the relationship between the target pixel and the peripheral pixels is as follows: (i) when the density of the target pixel is higher than the density of all the peripheral pixels by a certain fixed density or more, (ii) when the density of the target pixel is all the peripheral pixels If the density is lower than the density by more than a certain density, it is considered that the pattern matches, and the target pixel is detected as a halftone dot. The above-mentioned certain density is hereinafter referred to as a weight.

FIG. 16 shows a halftone dot having a density of 20% and 80% and a density distribution when one-dimensionally viewed at a portion A in order to simplify each halftone dot.
In the case of the above (i), the portion 1 in FIG. 16, that is, the halftone dot itself is detected as a halftone dot, and in the above (ii), the portion of FIG. The enclosed portion is detected as a halftone dot.

As described above, a halftone dot has a white nucleus when the density is high, that is, when the area ratio of black of a certain area is high, and when the density is low, that is, when the area ratio of white is high, the halftone dot has a black color. There may be a nucleus.

Here, in performing the dot detection, as shown in FIG. 14, the input data of the dot image is binarized at a plurality of threshold levels, and each of the binarized patterns is matched with the dot pattern and the matching pattern. As shown in FIG. 15, in the pattern matching for detecting halftone dots depending on whether or not the characters are present, characters and line drawing information around the binary threshold level are mechanically affected by unevenness in density of the image itself, unevenness in conveyance, and the like. Due to noise, illumination, and the above-described CCD 10 pitch unevenness, character and line image density information are not uniform, density unevenness of an input image occurs, and data after binarization has black breaks. If the black break matches the dot pattern, erroneous detection will occur.

That is, in the present embodiment, the above-described defect is corrected. Even if some density unevenness occurs, the density difference level is sufficiently small as compared with the halftone dot. The above defect can be compensated for by the density difference pattern matching provided between the target pixel and the peripheral pixel, and erroneous detection can be reduced.

Further, since this density difference does not change depending on the density (area ratio) of the halftone dots, there is an effect that the configuration of the circuit itself is relatively easy.

Hereinafter, the case of the pattern shown in FIG. 13A will be described for the white level detection circuit 73 and the black level detection circuit 74.

In the case of the above (i), the black level detection circuit 74
In the case (ii), the white level detection circuit 73 weights the peripheral pixel with the target pixel, and determines the magnitude relationship between the weighted target pixel (weighted target pixel) and the peripheral pixel.

FIG. 17 shows a black level detection circuit 74 using the pattern of FIG. The black level detection circuit 74 has a subtractor 161A
161N and comparators 162 to 175. Note that this circuit is an example, and the configuration changes depending on a pattern or the like.
The subtractor 161A weights the peripheral pixels of the target pixel. That is, the weighted pixel data Dcob15 is generated by subtracting the weight data Dob1 from Dc15, and is output to the comparator 162. Then, a signal De1 is obtained according to the magnitude relationship between the densities of the weighted target pixel data Dcob15 and the peripheral pixel data Dc2. Similarly, signals De2 to De14 are obtained. Note that the weight data D
The values of ob1 to Dob14 can be set arbitrarily. Thus, the black level is detected by processing the peripheral pixels Dc2 to Dc14 with different weights for the target pixel Dc15.

Here, the signals De1 to De14 are (weighted target pixel data)
It becomes “H” when> (peripheral pixel data), and becomes “L” otherwise.

Next, FIG. 18 shows a white level detection circuit 73 using the pattern of FIG. 13A. The white level detection circuit 73 is an adder
It comprises 141A-141N and comparators 142-155. Note that this circuit is an example, and the configuration changes depending on a pattern or the like. The adder 141A weights surrounding pixels of the target pixel. That is, the data Dow1 is added by weight from the signal Dc15 to generate weighted target pixel data Dcow15, and the signal Dd1 is obtained according to the magnitude relation of the density of the peripheral pixel data Dc2. Similarly, signals Dd2 to Dd14 are obtained. The values of the weight data Dow1 to Dow14 can be set arbitrarily. Therefore, the surrounding pixel Dc2 is compared with the target pixel Dc15.
DDc14 are processed with different weights to detect the white level.

Here, the signals Dd1 to Dd14 become “H” when (weighted note pixel data) <(peripheral pixel data), contrary to the black level detection circuit 74, and become “L” otherwise.

The pattern matching may use not only a single pattern but also a plurality of patterns. In this case, a black level detection circuit 74 and a white level detection circuit 73 similar to FIGS. Can be realized by arranging them in parallel as shown in FIG. 19 as an example.

Next, the pattern matching circuit will be described.

FIG. 20 shows an example of a pattern matching circuit using the pattern of FIG. The pattern matching circuit 75 includes AND gates 181 and 182 and an OR gate 183. Note that this circuit is an example, and the configuration changes depending on a pattern or the like. The signals Dd1 to Dd14 obtained from the white level detection circuit 73 become “H” when (weighted note pixel data) <(peripheral pixel data), and become “L” otherwise. Therefore, when the signals Dd1 to Dd14 are input to the AND gate 181 and the signals Dd1 to Dd14 are all "H", that is, when the density of the target pixel is lower than a certain weight with respect to all the peripheral pixels, the pattern matches. Therefore, the target pixel is determined as a halftone dot, and the signal Daw is set to “H”. Conversely, the signals Dd1 to Dd14
If at least one of them is "L", it does not match the pattern, so the target pixel is determined to be a non-dot, and the signal Daw is set to "L". Similarly, the signals De1 to De14 obtained from the black level detection circuit 74 are input to the AND gate 182, and the signals De1 to De14 are inputted.
When all 14 are “H”, the target pixel has a higher density than a certain weight with respect to all the peripheral pixels, so it matches the pattern. Therefore, the target pixel is determined as a halftone dot, and the signal Dab is set to “H”. Conversely, the signals De1 to De14
If at least one of them is "L", it does not match the pattern, so the pixel of interest is determined to be a non-dot, and the signal Dab
To “L”. Then, the signals Daw and Dab are input to the OR gate 183, and one of the signals Daw and Dab is set to “H”.
In other words, if the pattern matches one of the patterns and the target pixel is detected as a halftone dot, the target pixel is finally set to a halftone dot, and the signal Df is set to "H". Also signal Da
When w and Dab are both “L”, the middle pixel is finally set to a non-dot, and the signal Df is set to “L”.

When performing pattern matching using a plurality of patterns, as an example, a plurality of black level detection circuits 74a to 74c and a plurality of white level detection circuits 73a to 73c as shown in FIG.
An AND gate corresponding to is provided, and it is determined whether or not the pixel matches the pattern (whether the pixel of interest is a halftone dot or a non-halftone dot), and the output is input to an OR gate. If the target pixel is determined to be a halftone dot, the target pixel is finally determined to be a halftone dot, and if the target pixel is detected as a non-halftone dot in any of the patterns, the target pixel is finally determined to be a halftone dot. It can be realized by determining that the pixel is a non-dot.

The dot block detection circuit (1) 76 and the dot block detection circuit (2) 77 will be described.

In the halftone block detection circuit (1) 76 and halftone block detection circuit (2) 77, a block (halftone block 1) in which one halftone pixel exists in a block consisting of a plurality of pixels,
Similarly, a block (halftone block 2) having a plurality of pixels is detected.

In the related art, when such a halftone block is formed, if at least one halftone pixel exists in the block, the block has been formed as a halftone block. In this case, as described above, if even one pixel is erroneously recognized as a halftone pixel due to noise or the like, the entire block is erroneously recognized as a halftone block, as described above.

FIG. 21 shows a halftone dot image having 100 lines and a density of 50% at the aforementioned 400 dpi.
5 shows image data when reading is performed. In the figure, the hatched area indicates a halftone dot, and the upper and lower left and upper 1 to 16 on the image data.
Numbers correspond to each pixel. As is apparent from this figure, when a block of an appropriate size, for example, 8 × 8 pixels is a block, there are 4 to 5 halftone dots, so that a plurality of halftone pixels are included in the block. If present,
If the block is a halftone block, the above-mentioned disadvantages can be prevented. However, if halftone pixels are difficult to detect due to the effects of moire or the like, and if there are a plurality of pixels in a block, and that block is a halftone block, the halftone image part In this embodiment, there is a defect that a halftone pixel exists even in a block, and a plurality of halftone pixels exist in a block. , Are detected as halftone dot blocks 2 and used for the subsequent processing.

FIG. 22 shows the configuration of the halftone block (1) 76 and the halftone block detection circuit (2) 77. The halftone dot detection circuit (1) 76 is a halftone dot detection circuit (1) 20 in the main scanning direction.
In step 1, whether or not a halftone pixel exists in the main scanning direction of the block is detected.
According to 203, when there is at least one line where a halftone pixel exists in the sub-scanning direction of the block, the block is detected as the halftone block 1.

The halftone dot detection circuit (2) 77 detects whether or not a halftone pixel exists in the main scanning direction of the block by the halftone dot detection circuit (1) 201 in the main scanning direction, and performs the sub-scanning direction. When a plurality of predetermined lines including halftone pixels exist, the halftone block detection circuit (2) 204 detects the block as halftone block 2. The main scanning direction halftone dot block detection circuit (2) 202 detects whether or not a plurality of predetermined halftone pixels exist during the main scanning of the block. According to 205, when at least one line having a plurality of predetermined halftone pixels in the sub-scanning direction of a block exists, the block is detected as a halftone block 2.
And one of the blocks is a dot block 2
, The block is detected as a halftone block 2.

The details of each part will be described in detail below.
A description will be given of a case where a halftone dot block 2 is set when there are two or more halftone pixels in a block with eight pixels in the scanning direction.

The halftone dot detection circuit (1) 201 in the main scanning direction will be described.

The main scanning direction halftone block detection circuit (1) 201
Octal counter 210, flip prop 2
11 to 213, AND gates 214 and 215, OR gate 216 and NAND
It is composed of a gate 217. Note that this circuit is an example, and the circuit differs depending on the size of the block.

FIG. 25 shows an example of the operation timing of this circuit. The signals 1 to 7 in the figure correspond to the positions 1 to 7 in FIG. The numbers above CLK in FIG. 25 correspond to pixels.

The halftone dot detection circuit (1) 201 in the main scanning direction will be described below with reference to these drawings.

The main scanning direction halftone block detection circuit (1) 201 detects whether or not a halftone pixel exists in eight pixels in the main scanning direction of a block. Each output of the QA to QC of the octal counter 210 changes its output sequentially as shown in FIG. 25 every time the reference signal CLK is input. By inputting this to the AND gate 214, the flip-flop 211 Outputs 1 and 2 become "H" or "L" every 8 clocks. Here, for example, when the second pixel is determined to be a halftone dot and the signal Df is “H”,
OR gate 216 regardless of the state of output 5 of D gate 215
Becomes "H", this signal is latched at the next rising edge of CLK, and the output 4 of the flip-flop 212 becomes "H". By inputting the signals 4 and 2 to the AND gate 215, the output 5 of the AND gate 215 becomes "H" and this signal 5 is input to the OR gate 216.
, The signal 3 becomes "H" and the signal 4 also becomes "H". Then, at the ninth pixel, the signal 2 becomes "L", so that the signal 3 when the signal Df is "L" becomes "L", this signal is latched at the next rising edge of the CLK, and the signal 4 becomes "L". L ". By inputting the signal 1 and CLK to the NAMD gate 217, the output 6 of the NAND gate 217 becomes as shown in FIG. 25. By inputting this signal 6 to the clock of the flip-flop 213, the signal 6 rises. 4 is latched, the output 7 of the flip-flop 213 becomes "H" when the signal 4 is "H", that is, when a halftone dot exists in eight pixels, and conversely, when the signal 4 is "L", It becomes "L" when a halftone dot does not exist in eight pixels.

Hereinafter, an example of the timing when two halftone pixels exist in eight pixels from the ninth pixel to the sixteenth pixel, and the timing when no halftone pixels exist in the seventeenth to twenty-fourth pixels Is shown.

The halftone dot detection circuit (2) 202 in the main scanning direction will be described.

The main scanning direction halftone block detection circuit (2) 202
, Octal counters 220 and 221, flip flops 222 to 224, delays 225 and 226, and AND gates 227 and 22
8. It is composed of OR gates 229 and 230 and NAND gate 213. Note that this circuit is an example, and the circuit differs depending on the size of the block. FIG. 26 shows an example of the operation timing of this circuit. The signals 1 to 10 in FIG. 26 correspond to the positions 1 to 10 in FIG. In addition, CLK in FIG.
The numbers above indicate pixels.

Hereinafter, the halftone dot block (2) 202 in the main scanning direction will be described with reference to these drawings.

In the main scanning direction halftone block (2) 202, it is detected whether or not two or more halftone pixels exist in eight main scanning direction pixels of the block. Each output of octal counter QA ~ QC is
Each time the reference signal CLK is input, the output changes sequentially as shown in FIG. 26. By inputting these to the AND gate 227, the outputs 1 and 2 of the flip-flop 222 become "H" or "H" every eight clocks. L ". Here, for example, the third pixel and the sixth pixel
If the pixel D is determined to be a halftone dot and the signal Df is "H", an inverted signal of the signal Df and CLK is input to the AND gate 228, so that the output 6 of the AND gate 228 becomes "H". In the case of "", the inverted signal of CLK is output. When this signal 6 is input to the clock of the octal counter 211, when the first signal 6 becomes "H", the QB and QC outputs of the octal counter 221 are both "L". The output 7 of the OR gate 230 obtained by inputting to the gate 230 also becomes “L”, but when the signal 6 becomes “H” for the second time, the QB output of the octal counter 221 becomes “H”. Therefore, the signal 7 becomes "H". Since this signal 7 is latched at the next rising edge of the CLK, the output 8 of the flip-flop 223 also becomes "H".
Becomes Thereafter, the QB output is kept at "H" until the octal counter 221 is cleared, so that the signal 8 also keeps at "H". By inputting the signal 1 and CLK to the NAND gate 231, the output 9 of the NAND gate 231 becomes as shown in FIG. 26. By inputting this signal 9 to the clock of the flip-flop 224, the signal 9 rises. Since the signal 8 is latched, the output 10 of the flip-flop 224 becomes "H" when the signal 8 is "H", that is, when two or more halftone pixels out of eight pixels are present, and the signal 8 becomes "L". ", That is, when there is only one halftone pixel out of eight pixels,
Or, when there is no halftone dot pixel, it becomes “L”. 8
The ternary counter 221 is cleared by inputting the signal 1 to the delay 225 and inputting the obtained signal 3 and signal 2 to the OR gate 229. The output 4 of the OR gate 229 is further input to the delay 226, and the signal 5 is delayed and input to the clear terminal (CR) of the octal counter 221.

Hereinafter, the ninth pixel to the sixteenth pixel show timing examples in the case where one halftone pixel exists, and in the case where there is no halftone pixel from the 17th pixel to the 24th pixel.

The sub-scanning direction halftone block detection circuit (1) (reference numeral 203 or 205; hereinafter, referred to as 203) will be described.

The halftone dot detection circuit (1) 203 in the sub-scanning direction
As shown in the figure, octal counter 240, memory 241, OR gate
242, an AND gate 243 and a NAND gate 244. This circuit is an example, and the circuit differs depending on the block size.

FIG. 28 shows an example of operation timing of this circuit. The signals 1 to 5 in FIG. 28 correspond to the signals at the respective positions 1 to 5 in FIG. The numbers above 1/8 CLK in FIG. 28 correspond to blocks. The halftone dot block detection circuit (1) 203 in the sub-scanning direction will be described with reference to these drawings.

In the sub-scanning halftone block detection circuit (1) 203, the halftone dot in the main scanning 8 pixels of the block is determined by the halftone dot block (1) 201 or the halftone block (2) 202 in the main scanning direction. Pixels are present or absent, or halftone pixels are 2
After detecting whether there is more than one pixel or not, if there is a detection result indicating that a halftone pixel exists in at least one of the eight sub-scanning lines of the block, the block is detected as halftone block 1; When there is a detection result indicating that two or more halftone pixels exist in even one line, the block is detected as halftone block 2.

First, the detection of the halftone dot block 1 will be described. The octal counter 240 sequentially counts up each time LSYNC is input. Then, this QA ~ QC output is output to NAND gate 24
By inputting to 4, a signal 4 is obtained. First, when the output of the octal counter 240 is 7, the outputs of QA to QC go "H", so that the signal 4 goes "L". The signal 1 (= Dg) of the detection result of the halftone dot block detection circuit (1) 203 in the main scanning direction
1) However, if the halftone pixel exists in the first and fourth blocks and becomes “H”, the signal 4 is “L” regardless of the state of the output 3 of the memory 241. The output 5 of the AND gate 243 becomes "L". And signal 1 and signal 5 are O
Input to R gate 242 to obtain signal 2. Next, proceeding to the next line, when the output of the counter 240 is 0, the signal 4 becomes “H”. If the second block and the fourth block of the signal 1 are now “H”, the output 3 of the memory 241 is a signal obtained by latching the output signal 2 of the OR gate 242 at 1/8 CLK on the previous line. The signal in which the first block and the fourth block are “H” in the signal 1 of the line is held. Since the signal 4 is "H", the signal 5 is a signal in which the signal 3 is output as it is, and therefore, the output 2 from the OR gate 242 is an "H" signal in the first, second and fourth blocks.

In the same manner, when the output of the counter is 6, the signal 4
Becomes “H”. And signal 1 is now the third block is 7
If it becomes "H" for the first time including the line, since the signal 4 is "H", the signal 5 is the signal 3 held in the memory 241.
Becomes the output signal as it is, so that the signal 2 is 1
The fourth to fourth blocks are "H" signals. And this signal 2
Is latched at 1/8 CLK and becomes the output 3 from the memory 241 in the next line, so that the signal 1 is "H" even in one of the eight lines in the sub-scanning direction of the block. When the detection result indicates that a halftone pixel exists, the signal is kept as it is, and the block is set as a halftone block 1 to output a signal of "H".

Conversely, when all the signals in the eight lines are “L”, that is, the detection result indicates that there is no halftone pixel, the signal is kept as it is, and the signal of “L” is output as a non-halftone block. I do. Then, when the output of the counter 240 becomes 7 again, the signal 4 becomes "L".
Output 3 of 241 is no longer held and is cleared.

Regarding the detection of the halftone dot block 2, the operation is the same as the detection of the halftone dot block 1 only by changing the signal 1 to Dh1.

The halftone dot block detection circuit (2) 204 in the sub-scanning direction will be described.

As shown in FIG. 29, the sub-scanning halftone dot block detection circuit (2) 204 includes a memory 250, an AND gate block 251 and an O gate block 251.
It is composed of an R gate 252. In addition, the AND gate block 251 includes a plurality of AND gates 260 to 287 as shown in FIG. Note that these circuits are merely examples, and may have other configurations.

FIG. 30 shows the operation timing of this circuit up to the output of the memory 250, and FIG. 32 shows the AND gate block 2
An example of the operation from 51 to the output of the OR gate 252 will be described.

The sub-scanning direction halftone dot block detection circuit (2) 204 will be described below with reference to these figures.

A signal Dg1 that is detected by the main scanning direction halftone dot block detection circuit (1) 201 as to whether or not a halftone pixel exists in eight pixels in the main scanning direction is input to DIN1 of the memory 250, and DO
When the output of UT1 is fed back to DIN2 and input in the same manner, the output of DOUT2 is fed back to the input of DIN3, the output of DOUT3 is fed back to the input of DIN4, and so on. Point block detection circuit (1) 20
First, the detection signal Dg1-1 of the first line from 1 is input to DIN1, and then the detection signal Dg1-2 of the second line is input.
Since the output of OUT1 is input to DIN2, Dg1-1 is output from DOUT2 with a delay of one line.

Hereinafter, the detection signals Dg1− of the third line, the fourth line,.
, Dg1-4,... Are sequentially input, and the detection signal Dg1−
When 8 is input, the output signals Dg11 to Dg18 of DOUT1 to 8 become detection signals Dg1-1 to Dg1-8 of the first to eighth lines, and signals for eight lines in the sub-scanning direction of the block are obtained. Become. Next, when the signals Dg11 to Dg18 are input to the AND gate block 251, the AND gate block 251 inputs the signals AN of the two signals Dg11 to Dg18 as shown in FIG.
D, the signal Dg11 is 1, as shown in FIG.
In the 3,4,7,11,12th block, the signal Dg12 is 2,3,4,6,8,9,12
In the block, “H” when halftone dot pixel exists in 8 pixels in the main scan
Assuming that there is no halftone pixel in the signals Dg13 to Dg18 and the signal is always “L”, the output signals Dh11 to Dh38 from the AND gate block 251 are the signals Dg12 and Dg11, Dg12 and 3, 4, 12
Since "H" in both blocks indicates that at least two or more halftone pixels exist in the third, fourth, and twelve blocks, the third, fourth, and twelfth blocks are replaced by the halftone dot block 2.
As “H”. Other signals are not detected as halftone block 2 because there are no blocks that are both "H" in two lines, and are "L". And signal Dh11 ~
When Dh38 is input to the OR gate 252, since the third, fourth, and twelfth blocks of the signal Dh12 are "H", the third, fourth, and twelfth blocks are detected as the halftone dot block 2, and "H" is output.

FIGS. 33 to 36 show FIG. 37 based on the one-point halftone block information DG and the two-point halftone block information DH obtained from the above-described circuit.
DG and DH of 6 blocks (hereinafter referred to as area) shown in
FIG. 4 is a block diagram showing a specific example of a circuit for determining whether a circuit is a halftone dot area. 38 and 39 are timing charts showing the operation of the circuit for determining whether or not the area is the dot area.

Hereinafter, description will be made based on these drawings.

33 to 36, 300 and 330 are FIFORAMs (first-in first-out rams), 301 and 302 are multi-input DF / Fs, 303 to 317 and 319 to 325 are multi-input AND elements, and 318 and 3
26,327,329,333 are multi-input OR element, 328 is AND element, 331 is O
The R element 332 is a shift register.

In FIG. 38, LGATE, 1/8 LGATE, 1/8
CLK, IN-DG, IN-DH (one-point or two-point halftone block information input to DG, DH in FIG. 33) are input. IN ・ D of upper 5 signals (LAGTE, 1 / 8LGATE, IN ・ DG, IN ・ DH, 1 / 8CLK)
Signals showing the DATGn and DATHn portions of G, IN and DH in detail are the lower signals. IN • DG is one-dot halftone block information data, 1,2,3 ... 10,11,12,
13 ... n, that is, DATGn-1, DATGn-2, DATGn-3, DATGn
−4,..., DATGn-10, DATGn-11, DATGn-12,.
IN ・ DH (two-point dot block information data) is also DATHn
-1, DATHn-2, DATHn-3, DATHn-4, ... DATHn-10, DATHn
−11, DATHn−12, DATHn−13. The read / write CLK of the FIFORAM 300 is 1/8 CLK, and the write reset signal and the read reset signal are 1/8 LGATE. That is,
If the data input from the DIN1 terminal is DATGn-1,
The value written when the previous 1/8 LGATE became "H" at the same time, that is, the data [DATG (n-8) -1] of the 8th line from the nth line is synchronized with 1/8 CLK. Then, reading is performed sequentially.

Accordingly, signals at timings DG23, DH23, DG13, and DH13 can be obtained. DG23, DH23, DG13, DH13 are multi-input DF / F30
By using 1/8 CLK as the clock, DG22, DH22, DG12, DH12
Obtain a signal at a certain timing. DG22, DH22, DG12, D
H12 is also DG21, DH21, DG1 by multi-input DF / F302.
Get 1, DH11. Thus, one-point and two-point halftone information DG and DH of each block in the area shown in FIG. 37 are output at the same time and input to the next halftone area determination circuit. This is because of the timing shown in FIG.
/ 8LGATE calculation after 8LGATE becomes “H”, 3
When the second DATGn-3 and DATHn-3 are input, 1 / 8LGAT is 8 lines before the nth line from DG23 and DH23.
The third DATG (n-8) -3, DATH since E became "H"
From (n-8) -3, DG22 and DH22, DATG (n-8) -2.DATH which is 1/8 CLK one time earlier (the second since 1/8 LGATE became "H")
Similarly, from (n-8) -2, DG21 and DH21, the first DATG (n-8) -1, DATH (n-8) -1, DG13 and DH13 after 1/8 LGATE becomes "H". From 1 / 8L 16 lines before the nth line
The third DATG (n-16) -3 since GATE became "H",
DATG (n-16) -3, DATG (n-16) -2, DATH (n-1)
6) -2, DG11 and DH11 give DATG (n-16) -1, DATH (n-1
6) It is understood from the fact that -1 and are obtained.

FIG. 34 and FIG. 35 show FIG. 37 obtained at the same time in FIG.
FIG. 4 is a block diagram showing a circuit that determines an area as a halftone dot area if a certain condition is satisfied based on one-point and two-point halftone information DG, DH of each block in the area.

The above-mentioned certain conditions are as follows in the area of FIG.

1) Four pieces of two-point dot information DH are “H” and one-point dot information DH
Is one or more “H”.

2) When five or more two-point dot information DH is “H”.

If any of 1) and 2) is satisfied, the area is set as a dot area. The above conditions are examples, and DH, DG
Of course can be varied by the system.

As described above, a plurality of halftone dot detection signals exist in the halftone dot block. In other words, the halftone dot detection unit may detect six halftone blocks as DH, that is, two-point halftone detection. However, moire occurs in a halftone original due to the phase difference from the reading pitch of the CCD 10. Due to this moiré, a plurality of halftone dots may not be detected even though the halftone block is an actual halftone image.

Further, for example, a part of a character or a stain on the background may be detected as one dot, and may be erroneously determined as a halftone dot area.

Therefore, as described above, if one or more halftone dot blocks are used for only halftone dot detection, the number of erroneous determinations increases. Further, if only two or more halftone dot blocks are used for halftone dot detection, a halftone dot area is detected by the above moiré. become unable. Therefore, the above-mentioned drawback is improved by a combination of a one-point halftone dot and a two-point halftone dot detection block, and in combination with a block having no halftone dot detection.

The multi-input AND elements 303 to 317 in FIG.
From 1 to DH13 and DH21 to DH23, all four combinations are selected, and it is indicated whether the two-point halftone dot information of the above condition 1) becomes "H" and the information is represented by the circuit at the next stage. Tell And
B41 to B49 and B410 to B415 serve as inputs of the multi-input OR element 327, and information on whether any one of them becomes "H" is output from the AND element 328.
The multi-input OR element 318 informs the multi-input OR element 329 of whether or not there is one or more "H" in the halftone dot information DG11 to DG13, DG21 to DG23 to one input and the other input. ing. Therefore, the output of the AND element 328 satisfies the condition 1).

Next, the multi-input AND elements 320 to 325 correspond to the two-point halftone dot information DH11.
DH13 and DH21 to DH23, all five combinations are selected and output to the multi-input OR element 326, and the multi-input OR element 329 is informed whether at least one of them has "H". The multi-input AND element 319 has two-point dot information DH11 to DH13 and DH21 to DH2.
The multi-input OR element 329 is notified that all three are “H”. The above applies to condition 2).

Therefore, from the multi-input OR element 329, the condition 1) or 2)
Is “H” if is true, “L” otherwise
Is output.

FIG. 36 shows a case where the area of FIG. 37 is a halftone area (AMI
When the signal is "H") all its data, 8 (pixels)
FIG. 3 is a block diagram of a circuit that uses × 8 (lines) as a halftone dot area. Here, description will be made with reference to the timing chart of FIG.

[0144] Based on 1 / 8CLK, 1 / 8LGATE, LGATE, image data DAT
Assume that IN is as shown in FIG. Where DATn-1
Represents the first image data in units of 8 pixels, counted from the rising edge of LGATE on the nth line. Further AMIn
Is the dot area information detected by the above-described circuit on the n-th line, AMI (n-8) is the (n-8) -th line, and AMI (n-1)
6) is the information of the dot area on the (n-16) th line, and it is assumed that the signals at the timings shown in FIG. 39 have been obtained.

The FIFORAM 300 has a read / write CLK of 1/8 CLK, a write / reset signal of 1/8 LGATE, and a read / reset signal of LG.
By using ATE, the dot area information written when 1/8 LGATE is “H” is replaced by 1/8 CLK when LGATE becomes “H”. Read sequentially while synchronizing.

In FIG. 39, AMIn represents image data DATn−1 and DAT
“H” when (n + 1) −3, AMI (n−8), AMI (n
-16) are all "L" within the range of the image data shown in FIG. From the DOUT1 and DOUT2 terminals of the FIFORAM 330, only the portion corresponding to the image data DATn-1 is "H", and the signal "L" is output thereafter. The OR element 331 outputs a signal called OR output, which is transmitted to the shift register 332, and further outputs the OR element 331 and the shift register 332
The signal B is obtained by taking the OR of the outputs Q1 and Q2 (latch once and latch twice) by the multi-input OR element 333.

This is the image data, DATn-1, DATn-2, DATn-3, DAT
In the area of (n−8) −1, DAT (n−8) −2, DAT (n−8) −3, the halftone area information of only the block of DATn−1 is “H”. Is set to "H".

For example, in the final stage, the image data is similarly delayed by the delay caused by the FIFORAM, the multi-input DF / F used in the present embodiment, and the halftone area information is used as a control signal. Characters and halftones can be separated from the processed image data and the halftone processed image data by using a selector or the like. In the description of the specific embodiment of the present invention, the area shown in FIG. 37 is defined as a halftone dot determination area, but the size of the area can be changed according to the input / output characteristics of the apparatus, the characteristics of the target document, and the like. , So as to reduce the judgment error,
It can be easily applied based on this embodiment. Also, the conditions for determining the halftone dot area can be changed by the above-described use, and the determination error can be reduced.

[0149]

【The invention's effect】

As described above, the difference between the density of the target pixel and the densities of the plurality of peripheral pixels is compared with a predetermined value, and when all the differences are equal to or more than the predetermined value, the target pixel is detected as a halftone pixel. In the above, since the predetermined value is made different depending on each position of the plurality of peripheral pixels, the detection rate of the halftone area can be improved, and the rate of erroneously detecting an area that is not a halftone area as a halftone area can be improved. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire halftone dot detection circuit according to one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a digital copying machine.

FIG. 3 is an electrical configuration diagram of the scanner.

FIG. 4 is a waveform diagram of input data and corrected data.

FIG. 5 is an explanatory diagram of an example of MTF correction.

FIG. 6 is a block diagram showing a circuit configuration of MTF coefficient setting.

FIG. 7 is a diagram of a Y-direction delay circuit.

FIG. 8 is a timing chart of a Y-direction delay circuit.

FIG. 9 is an explanatory diagram of a control signal for controlling a timing relationship.

FIG. 10 is an X-direction delay circuit diagram.

FIG. 11 is a timing chart of the X-direction delay circuit.

FIG. 12 is an explanatory diagram showing image data obtained by an X-direction delay circuit.

FIG. 13 is an explanatory diagram showing a pattern used for pattern matching.

FIG. 14 is a signal waveform diagram of a halftone image read by an image scanner.

FIG. 15 is an explanatory diagram of a conventional pattern matching method.

FIG. 16 is an explanatory diagram showing a halftone dot and its density distribution.

FIG. 17 is a block diagram of a black level detection circuit.

FIG. 18 is a block diagram of a white level detection circuit.

FIG. 19 is a diagram illustrating an example in which a black level detection circuit and a white level detection circuit are arranged in parallel.

FIG. 20 is a block diagram illustrating an example of a pattern matching circuit.

FIG. 21 is an explanatory diagram showing image data when a halftone image having 100 lines and a density of 50% is read at 400 dpi.

FIG. 22 is a block diagram illustrating an example of a dot block detection circuit.

FIG. 23 is a block diagram showing an example of a halftone dot block detection circuit in the main scanning direction.

FIG. 24 is a block diagram illustrating an example of a halftone dot block detection circuit in the main scanning direction.

FIG. 25 is a timing chart of the circuit shown in FIG. 23;

FIG. 26 is a timing chart of the circuit shown in FIG. 24;

FIG. 27 is a block diagram showing an example of a halftone dot block detection circuit (1) in the sub-scanning direction.

FIG. 28 is a timing chart of the circuit shown in FIG. 27;

FIG. 29 is a block diagram illustrating an example of a halftone dot block detection circuit (2) in the sub-scanning direction.

30 is an operation timing chart of the memory of FIG. 29.

FIG. 31 is a circuit diagram illustrating an example of an AND gate block in FIG. 29;

FIG. 32 is a timing chart of the circuit shown in FIG. 31;

FIG. 33 is a block diagram illustrating an example of a circuit that determines a halftone dot area.

FIG. 34 is a block diagram illustrating an example of a circuit that determines a halftone dot area.

FIG. 35 is a block diagram illustrating an example of a circuit that determines a halftone dot area.

FIG. 36 is a block diagram illustrating an example of a circuit that determines a halftone dot area.

FIG. 37 is a diagram showing six blocks (areas).

FIG. 38 is a timing chart of the halftone dot area determination circuit.

FIG. 39 is a timing chart of the dot area determination circuit.

[Explanation of symbols]

 71 Y direction delay circuit 72 X direction delay circuit 73 White level detection circuit 74 Black level detection circuit 75 Pattern matching circuit 76 Halftone block detection circuit (1) 77 Network Point block detection circuit (2) 78 ... Dot area detection circuit

Continuation of front page (56) References JP-A-2-11587 (JP, A) JP-A-61-59569 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1 / 40-1/409 H04N 1/46 H04N 1/60 G06T 1/00-7/00

Claims (1)

(57) [Claims] A plurality of density comparing means for comparing whether or not the difference between the density of the target pixel and the density of the plurality of peripheral pixels is equal to or greater than a predetermined value different depending on the position of each of the plurality of peripheral pixels; A pixel of interest when the difference between the density of the pixel of interest and the density of the plurality of peripheral pixels based on the comparison results of the plurality of density comparison units is equal to or greater than a predetermined value that is different depending on each position of the plurality of peripheral pixels; And a halftone pixel detecting means for detecting as a halftone pixel.