JP3073763B2 - Input level display method for recorder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for displaying an input level in a recorder, and more specifically, a bar graph of an input signal level on a display unit such as a CRT or a liquid crystal display. The present invention relates to an input level display method for displaying.

[Conventional technology]

FIG. 6 shows an input level monitor 1 as a conventional example. The input level monitor 1 includes, for example, a plurality of LEs.
D1a is arranged linearly, and is provided for each of the input channels 2a and 2b as shown in the figure. In this input level monitor 1, the portion corresponding to the input level is
LED1a turns on. Therefore, for example, when an input waveform is written on recording paper, an appropriate range or the like can be selected while checking the level.

[Problems to be solved by the invention]

However, the conventional input level monitor 1 has a LE
This requires hardware such as a display component such as D1a and its drive circuit, which is not preferable in terms of cost. In addition, the cost burden increases as the number of channels increases.

[Means for solving the problem]

The present invention has been made in view of the above-described conventional circumstances, and its structural features include an A / D converter for converting an analog input signal into a digital signal, a display unit for displaying an input waveform thereof, and an A / D converter. In a recorder including a converter and a control device (CPU) for controlling the display unit,
Two memories are provided for the input channels, and a V-RAM to which data stored in each memory is transferred is provided. The CPU alternately switches the two memories at predetermined time intervals and repeats write clearing. At the same time, when writing,
The specific data for level display is written to the address to which the digital data from the A / D converter is added, and after a predetermined time, the specific data in the memory is transferred to the V-RAM, and the input waveform signal is input to the display unit. The purpose is to display levels in a bar graph.

[Action]

First, specific data for displaying the level of an input signal is written to one memory. That is, when the CPU receives the digital data from the A / D converter, the digital data is added to the head address of the memory, and the value is used as a write address. Data is written so that all bits are set to "1". In this manner, data is written for a predetermined time, and when the writing is completed, the data in the same memory is transferred to the V-RAM, and the data is written to the other memory in the same manner as described above. By repeating this, the input level is displayed in a bar graph on both sides of, for example, a CRT.

〔Example〕

FIG. 1 illustrates a schematic block diagram of a recorder to which the present invention is applied. According to this, this memory meter is an A / D that converts an analog input signal to a digital signal.
A converter 10, a CPU 11 as a control device, and an operation unit 12 including a keyboard for setting various operation conditions,
For example, the display unit 13 composed of a liquid crystal panel and its driving circuit
14 and V- for displaying the input level on the display unit 13.
RAM15.

In the CPU 11, a ROM 11a in which a system program and the like are written, and a RAM 11b used as a work memory, etc.
In this embodiment, two work memories are provided for one input channel. FIG. 2 shows the two work memories with reference numerals A and B. The work memories A and B are stored in the RAM 11
A predetermined area may be used in b, or it may be provided as a dedicated RAM.

Next, a display example of the input level will be described with reference to the flowcharts of FIGS. In this example, the resolution of the A / D converter 10 is 8 bits, and in connection with this, 256 bytes are used for the work memories A and B.

First, in step M1 of the main routine in FIG. 3, the work memories A and B are cleared to "0".
Next, the sampling speed of the A / D converter 10 is set by the CPU 11 in step M2. Then, in step M3, of the work memories A and B, the memory for writing data is set to "1". In this case, W is used as the variable, and when W ← 1, memory A is selected. On the other hand, when the variable W is 2, the other memory B is selected. Thereafter, in step M4, an interrupt from the A / D converter 10 is permitted. As a result, the subroutine of FIG. 4 is executed, and the A / D converter 10
The / D data is read, and the A / D data is temporarily written to a predetermined register in the CPU 11. Then, in step S2, the A / D data is added to the head address of the work memory A, and the value is used as a write address, and specific data for level display, for example, FFH, is written to the corresponding address. Here, if the start address is A000H and the A / D data is 80H, FFH is written to the address of A080H. This data writing is repeated a predetermined number of times by waiting for a certain time in step M5. In this embodiment, the A / D converter 1
Since the sampling time of 0 is 100 μS and the wait time of step M5 is 100 ms, 1000 A
/ D data is written to one work memory A. At step M6 after the time-up, a work memory for transferring data to the V-RAM 15 is designated, and the variable W is set to a new value. That is, the variable of the memory to be transferred is M, and M ← W. In this case, since W is set to 1 in step M3, the work memory A is designated as the memory to be transferred. Further, a work memory to which data is to be written is selected by W ← 1 + (Mmod2). (Mmod2) is the remainder when M is divided by 2.
Therefore, if M is 1, W = 2, and if M is 2, W = 1. Here, since M is set to 1,
The variable W becomes 2, and the other work memory B is selected as a memory to be written. Then, the data in the work memory A is transferred to the V-RAM 15 in the next step M7, and the work memory A is cleared to "0" in the following step M8. Then, it is determined in step M9 whether the stop key has been operated. If NO, the process returns to step M5, and if YES, the process ends.

As described above, by using the two work memories A and B alternately and transferring the data to the V-RAM 15, the level of the input signal is displayed on the screen of the display unit 13 in the form of a bar graph. You. FIG. 5 shows a display example when there are four input channels.

Note that the display resolution of the display unit 13 is set to, for example, 1 /
In the case of 2, it is sufficient to prepare two 128-byte work memories. Also, A / D data is set to 1/2
The data is written to a predetermined register in the CPU 11.
Furthermore, in step S2, as specific data for level display
Although FFH is written, it is not limited to this.

〔The invention's effect〕

As described above, according to the present invention, the memory and the V
-With the simple structure of simply adding RAM, the level of an input signal can be displayed using a display screen such as a CRT or a liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a recorder applied to the present invention, FIG. 2 is a schematic diagram showing two working memories used in the embodiment, FIG. FIG. 4 is a flowchart for explaining the operation of the present invention, FIG. 5 is an explanatory diagram showing an example of level display on a display screen, and FIG. 6 is an explanatory diagram for explaining a conventional example. In the figure, 10 is an A / D converter, 11 is a CPU, 12 is an operation unit, 13 is a display unit, 14 is a display drive circuit, and 15 is a V-RAM.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01D 7/00 301 G01R 13/02 G09G 5/00 510 G09G 5/00 550 G09G 5/36 510

Claims (1)

(57) [Claims] An A / D converter for converting an analog input signal into a digital signal, a display unit for displaying an input waveform thereof, and a control device (CPU) for controlling the A / D converter and the display unit. In this recorder, two memories are provided for one input channel, and a V-RAM to which data stored in each memory is transferred is provided. The CPU stores the two memories at predetermined time intervals. Write alternately, repeat writing and clearing, and at the time of writing, write specific data for level display to an address obtained by adding the digital data from the A / D converter to the top address of the memory,
After a predetermined time, the specific data in the memory is stored in the V-RA
M. The input level of the input waveform signal is displayed on the display unit in a bar graph form on the display unit.