JP3074963B2 - Signal switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal switching circuit, and more particularly to a signal switching circuit comprising a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional signal switching circuit is shown in FIGS. In FIGS. 2, 3, and 4, npn transistors Q8 and Q12, to which signals of two systems are input to bases through input terminals 1 and 2, respectively, have collectors connected to a power supply (Vcc) and transistors Q9 and Q9, respectively. Q11 and differential pairs 1 and 2 are configured. The differential pairs 1 and 2 are indicated by SW1 and SW2 in the figure. In the differential pairs 1 and 2, the transistors Q9 and Q11 on the opposite side of the signal input are connected to each other by a short-circuited base / collector, and this connection point is connected to the terminal 3 as a signal point.

[0003] Transistors Q1 to Q7, resistors R1 to R6
Are output from the reference voltage generating circuit constituted by ## EQU1 ## as V1 and V2 as reference voltages of the current mirror circuit. Of these, V2 is input to the base and a pnp transistor Q10 having a resistor R7 connected between the emitter and the power supply. Is connected to the output point and supplies a constant current to the output point.
By supplying an operating current alternately to the common emitters of the differential pairs 1 and 2 connected in this manner, a signal input to the differential pair on the side to which the current is supplied to the common emitter is output. Is transmitted to The means for alternately supplying a current to the common emitter is different in each of FIGS. 2, 3 and 4. First, the operation of the parts so far will be described.

In FIG. 5, transistors Qa1 and Qa1
The differential pair constituted by a2 corresponds to the above-described differential pair 1, and similarly, the transistors Qb1 and Qb2
The constant current source C corresponds to a current mirror circuit including the transistor Q10, and the constant current sources A and B
Is supplied with operating current.

A DC voltage Va is applied to the base of a transistor Qa1 which is a signal input terminal, and a transistor Qb1
Vb is input to the base of. Constant current sources A, B,
When the output current of C is I1, I2, and I0, respectively, when the constant current source A or B is on, I1 and I2
2 is set equal to twice I0.

Considering a state where the constant current source A is on and the constant current source B is off, since no operating current is supplied, the differential pair 2 is cut off, and the differential pair 2 as viewed from the output point is high.・
Impedance, and all I0 are transistors Qa2
Emitter current. Since I1 is drawn from the common emitter of the differential pair 1 by the constant current source A, the transistor Qa1 has an emitter current I3 = I1−I0 = 2 · I
0-I0 = I0 flows. Both emitter currents are I0
Therefore, if the transistors Qa1 and Qa2 are of the same type, the respective base-emitter voltages are also equal. That is, the voltage at the output terminal becomes equal to the signal input Va. Even if I1 ≠ 2 · I0 or the transistors Qa1 and Qa2 are not the same type of transistor, the offset voltage ΔV corresponding to the ratio of the emitter current normalized per unit emitter area of the transistors Qa1 and Qa2 is added to the input Va. Voltage is output. Here, ΔV is shown as follows.

ΔV = (kT / q) · ln {(AEa1 / AEa2) · (I0 / I3)} where k: Boltzmann constant, T: absolute temperature, q: electron charge, AEa1: emitter of transistor Qa1 Area, AEa2: emitter area of transistor Qa2.

On the contrary, even when the constant current source A is off and the constant current source B is on, the voltage of the output terminal becomes equal to the signal input Vb or the offset voltage ΔV.
Is applied to the input Vb. Here, ΔV is represented by the following equation.

ΔV = (kT / q) · ln {(AEb1 / AEb2) · (I0 / I3)} where AEb1 is the emitter area of the transistor Qb1,
AEb2: emitter area of transistor Qb2.

As described above, in the portion described above with reference to FIGS. 2, 3, and 4, that is, in the circuit having the configuration of FIG. 5, the differential pairs 1 and 2 function as switches by switching the operating current. One of the two inputs can be selected and output.

Next, the configuration of the control current generating means for switching the differential pairs 1 and 2 will be described.

In FIG. 2, the output V1 of the above-described reference voltage generating circuit is connected to the base and a resistor R is connected between the emitter and the ground.
The npn-type transistor Q52 to which 50 is connected forms a current mirror circuit. Differential pair 1 is connected to the collectors of transistors Q50 and Q51 forming differential pair 3, respectively.
And 2 are connected, the common emitter is connected to the collector of the transistor Q52, which is the constant current output terminal of the current mirror circuit, and the bases are connected to the control terminals 5 and 4, respectively.

In FIG. 3, current mirror circuits for supplying operating currents to the differential pairs 1 and 2 are separately provided, the output V1 of the above-mentioned reference voltage generating circuit is input to the base, and the common emitter of the differential pair 1 is connected to the collector. An npn-type transistor Q20, a resistor R20 connected between the emitter of the transistor Q20 and the ground, a transistor Q21 similarly inputting V1 to the base and connecting the common emitter of the differential pair 2 to the collector, It is composed of a resistor R21 connected between the emitter of the transistor Q21 and the ground.

A pn with a control terminal 5 connected to the base
The control terminal 4 is similarly connected to the base of the p-type transistor Q40.
To form a differential pair 4 with the transistor Q41
A constant current source 6 connected between the common emitter and the power supply
, A resistor R40 connected between the collector of the transistor Q40 and the ground, a resistor R41 connected between the collector of the transistor Q41 and the ground, and the differential pair 4 to form a comparison circuit. The collector of the transistor Q40, which is the output of the comparison circuit, and the contact point of the resistor R40 are connected to the power supply, the collector of which is connected to the base of the transistor Q23 forming the differential pair 5 with the transistor Q20,
Similarly, the collector of the transistor Q41 and the contact point of the transistor R41 are connected to the power supply with the collector connected to the transistor Q2.
1 and the base of a transistor Q22 forming the differential pair 6.

FIG. 4 differs from FIG. 3 in the configuration of the output section of the comparison circuit. The collector and base of the npn transistor Q42, whose collector and base are short-circuited, are connected to the transistor Q4.
0 is connected to the collector of the transistor Q2 and becomes an output point.
3 base. A resistor R40 is connected between the emitter of transistor Q42 and ground. Similarly,
The collector / base of the transistor Q43 is connected to the collector of the transistor Q41 to be an output point, and is connected to the base of the transistor Q22. R41 is connected between the emitter of transistor Q43 and ground. Others are the same as FIG.

The operation will be described. In FIG. 2, the constant current output from the transistor Q52 is
The current switch composed of Q51 distributes the differential pair to the differential pair 1 or 2. Normally, as long as characteristics such as operation speed are allowed, pn
Lateral transistors are often used for p-type transistors.
Even in the configuration of FIG. 2, if a lateral pnp transistor is used, the largest cause of an error in the path for determining and transmitting the constant current supplied to the differential pair 1 and 2 is the Early effect of the transistor Q10. . However, since the base of the transistor Q10 is driven with low impedance and the Early effect affects only one stage of the transistor Q10, the current injected into the differential pairs 1 and 2 from the output side and the current from the common emitter are subtracted. The current to be applied is determined faithfully with relatively high accuracy. For this reason, this configuration is often used.

However, four stages of transistors are vertically stacked within the range of the power supply voltage, and a wide dynamic range is secured as the power supply voltage is required to be further reduced in order to reduce the power consumption of the semiconductor integrated circuit. It is an obstacle in doing so.

Therefore, in the example of FIG. 3, the two-stage configuration in which the constant current output is switched by a current switch using a differential pair is stopped, and the transistors Q20 and Q constituting a constant current source are stopped.
21 and a differential pair, and switches the current mirror circuit itself. As a result, the number of vertically stacked transistors is reduced by one step, and a margin of approximately 0.8 V in voltage can be obtained. The advantage remains that the current injected into the differential pairs 1 and 2 from the output and the current drawn from the common emitter are determined with relatively high accuracy.

The example of FIG. 4 is basically the same as that of FIG. 3, except that the output voltage of a comparison circuit that switches a current mirror circuit that supplies a constant current to the differential pairs 1 and 2 is connected in series with a diode and a resistor. Since this occurs at the load, the operating current of the comparison circuit can be reduced as compared with FIG.

[0020]

The conventional signal switching circuit described above differs from the transistors Q20 and Q21 forming the constant current sources as shown in FIGS. 3 and 4 in order to secure a wide dynamic range at a constant power supply voltage. The moving mirrors 5 and 6 are assembled to switch the current mirror circuit itself.

In the operating current of the differential pair 1 and 2 switched in this manner, the time and timing required for the rising and falling of the switching depend on the output voltage waveform of the comparison circuit which is the switching control voltage. .

For this reason, if the configuration shown in FIG. 4 is used in order to save the power consumption of the comparison circuit, a time difference occurs in the switching of the operating currents of the differential pairs 1 and 2, and the signal output changes at the switching timing. There was a problem that a whisker might be generated. This will be described with reference to FIG.

In FIG. 6, when switching the differential pairs 5 and 6 described above, the differential pair 1 is applied to the base voltage waveform of the transistors Q22 and Q23 to which the control voltage is applied.
2 and 2 show operating current waveforms. V in the figure
U and VL indicate upper or lower boundary potentials at which the differential pairs 5 and 6 start to switch from the completely switched state to the opposite state, and the switching of the current flowing through the differential pair depends on the applied voltage. It is approximated that it changes linearly.

For example, when the output section of the comparison circuit is configured as shown in FIG. 4, a diode-connected transistor Q4
2, the collector-base voltage waveform of Q43 becomes blunt because the time constant with the parasitic capacitance increases at the falling edge when the voltage is reversed. That is, the transistor Q22,
The falling of the base voltage waveform of Q23 is delayed with respect to the rising as shown in FIG. Then, a shift also occurs in the switching of the operating currents I1 and I2 supplied to the differential pairs 1 and 2, and a period where I1 + I2 <I0 occurs.

During this period, the transistor Q10 that has injected a constant current into the signal output points of the differential pairs 1 and 2 is saturated. Assuming that the saturation resistance of the transistor Q10 is rsc, Vo = Vcc− (rsc + R7) ×
The output point potential stops up to the potential determined by (I1 + I2), and the output signal has an upward whisker at the switching timing.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a signal switching circuit in which an upward beard is not generated.

[0027]

According to the structure of the present invention, a first transistor in which a first signal is input to a base and a first power supply is connected to a collector, and the collector and the base are short-circuited to each other, the first signal is connected to the first transistor. A first differential pair comprising a transistor and a second transistor forming a differential pair; a third transistor having a second signal input to a base and a first power supply connected to a collector; a collector and a base Are short-circuited to each other to form a differential pair with the third transistor.
And a second differential pair comprising transistors of the first and second transistors, wherein a contact point connected between the collector and base of the second and fourth transistors which are short-circuited is an output point, and the output point and the first A first constant current source is connected between the first differential pair and the second differential pair, and a second constant current source is connected between the common emitter of the first differential pair and the second differential pair and the second power source. 3
Are connected to each other, and the second and third constant current sources alternately supply operating currents to the first and second differential pairs, respectively. 2
In the signal switching circuit in which the signal on the side to which the operating current is supplied to the differential pair among the two signal inputs is transmitted to the output point, the second constant current source is connected to the base by the third A fifth transistor connected to a reference power supply and having a collector as a constant current output; a sixth transistor forming a third differential pair with the fifth transistor and having a collector connected to the first power supply; , A first resistor connected between the common emitter of the third differential pair and the second power supply, and the third constant current source is connected to the base by the third constant current source. A seventh transistor to which a reference power supply is connected and whose collector outputs a constant current; an eighth transistor which forms a fourth differential pair with the seventh transistor and whose collector is connected to the first power supply; The common emitter of the fourth differential pair and the common emitter of the fourth differential pair Of which is constituted by a second resistor connected between a power supply, is input switch an externally applied control signal and the fourth reference power source to the ratio較回path, this ratio較回paths mutually phase Are inverted, the first and second outputs are the first
And the input of the second waveform conversion circuit, respectively, and the respective outputs of the first and second waveform conversion circuits are connected to the bases of the sixth and eighth transistors, respectively, and the respective outputs to these bases Is a control signal whose rise is delayed as compared with the fall, and the current of the first constant current source is prevented from becoming larger than the sum of the currents of the second and third constant current sources. I do.

[0028]

FIG. 1 is a circuit diagram showing a signal switching circuit according to one embodiment of the present invention.

Referring to FIG. 1, in this embodiment, npn-type transistors Q8 and Q12, to which signals of two systems are inputted to a base through input terminals 1 and 2, respectively, have collectors connected to a power supply and Q9 and Q11, respectively. The differential pairs 1 and 2 are configured.

The differential pairs 1 and 2 are connected to switches SW1 and S
Indicated by W2. In the differential pairs 1 and 2, the transistors Q9 and Q11 on the opposite side of the signal input are connected to each other by a short-circuited base and collector, and this connection point is connected to the terminal 3 as a signal output point.

Transistors Q1 to Q7, resistors R1 to R6
V1 and V2 are output as reference voltages of the current mirror circuit. Of these, V2 is input to the base, and the pnp transistor Q10 of which the resistor R7 is connected between the emitter and the power supply is connected to the base. A collector is connected to the output point and supplies a constant current to the output point.

Current mirror circuits for supplying operating currents to the differential pairs 1 and 2 are separately provided, the output V1 of the above-mentioned reference voltage generating circuit is input to the base, and the common emitter of the differential pair 1 is connected to the collector. npn transistor Q20
A resistor R20 connected between the emitter of the transistor Q20 and the ground; a transistor Q21 similarly inputting V1 to the base and connecting the common emitter of the differential pair 2 to the collector; and an emitter of the transistor Q21 and the ground. And a resistor R21 connected between them.

A pn with a control terminal 5 connected to the base
The control terminal 4 is similarly connected to the base of the p-type transistor Q40.
Form a differential pair 4 with the constant current source 6 connected between the shared emitter and the current, and a resistor R connected between the collector of the transistor Q40 and the ground.
40, a resistor R41 connected between the collector of the transistor Q41 and the ground, and the differential pair 4 constitute a comparison circuit.

The collector of the transistor Q40, which is the output of the comparison circuit, and the contact of the resistor R40 are connected to a pnp-type transistor whose collector is grounded and whose constant current source 8 and capacitor C30 are connected in parallel between the emitter and the power supply. Q3
0, and the emitter of the transistor Q30 is further connected to the base of the transistor Q23 which forms the differential pair 5 with the collector connected to the power supply, and similarly, the collector of the transistor Q41 and the resistor R41 Is connected to the base of a pnp transistor Q31 in which the collector is grounded and the constant current source 7 and the capacitor C31 are connected in parallel between the emitter and the power supply. The emitter of the transistor Q31 further has the collector connected to the power supply. Connected to the base of the transistor Q22 forming the differential pair 6 with the transistor Q21 described above. Next, the operation will be described.

Since the load of the comparison circuit is a linear resistance,
Transistors Q30 and Q31 which are inputs of the waveform conversion circuit
Are applied with a control voltage waveform having substantially the same rise and fall times. Since the transistors Q30 and Q31 are in the forward direction when the control voltage falls,
Capacitors C30 and C31 can be driven with low impedance. However, when the control voltage rises, the transistors Q30 and Q31 are cut off, and the capacitors C30 and C3 are turned off by the currents output from the constant current sources 8 and 7.
1 will be charged. At this time, the time t required for charging is expressed by the following equation.

T = (CV) / I where C = C30 = C31, V... Amplitude of control voltage, I ...
Output current of constant current sources 7 and 8.

[0037] That is, the control voltage waveform output from each of the emitters of the transistors Q30, Q31 to the transistor Q23, Q22, delayed as compared with the decreases its rise up.

Hereinafter, description will be made with reference to FIG. In FIG. 7, when switching the differential pairs 5 and 6 described above,
FIG. 5 shows an operation current waveform supplied to the differential pairs 1 and 2 with respect to a base voltage waveform of the transistors Q22 and Q23 to which a control voltage is applied. In the figure, VU and VL indicate upper or lower boundary potentials at which the differential pairs 5 and 6 start to switch from the completely switched state to the opposite state,
The switching of the current flowing through the differential pair was approximated to change linearly with the applied voltage.

As described above, the transistors Q22, Q2
A control voltage whose rising is delayed compared to its falling is applied to the base of No. 3. Then, as shown in the drawing, the operating currents I1 and I2 supplied to the differential pairs 1 and 2 have more overlapping periods, and there is no period where I1 + I2 <I0. This prevents the transistor Q10 that has injected the constant current into the signal output points of the differential pairs 1 and 2 from saturating. The other operations are the same as those in the conventional example, and will not be described.

[0040]

As described above, the present invention provides a differential pair 1 and 2 which can function as a switch by switching an operating current and can select and output one of two inputs. By providing a control signal waveform conversion circuit and increasing the period in which the operating currents applied to these two differential pairs are switched and overlap each other, the effect of eliminating the problem that a beard occurs at the switching timing of the signal output can be eliminated. is there.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a signal switching circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first example of a conventional signal switching circuit.

FIG. 3 is a circuit diagram showing a second example of a conventional signal switching circuit.

FIG. 4 is a circuit diagram showing a third example of a conventional signal switching circuit.

FIG. 5 is a circuit diagram showing the principle for explaining the operation.

FIG. 6 is a waveform diagram showing the operation of each unit in the related art.

FIG. 7 is a waveform chart showing the operation of each unit in FIG. 1;

[Explanation of symbols]

Q1-Q12, Q20-Q23, Q30, Q31, Q4
0 to Q43, Q50 to Q52, Qa1, Qa2, Qb
1, Qb2 transistors R1-R7, R20, R21, R40, R41, R50
Resistors C30, C31 Capacitors 1, 2 Signal input terminals 3 Signal output terminals 4, 5 Switching control terminals 6, 7, 8, A, B, C Constant current sources Va, Vb Input power supply Vo Output voltage Vcc power supply

Claims (2)

(57) [Claims] A first transistor having a first signal input to a base and a first power supply connected to a collector; and a second transistor forming a differential pair with the first transistor, wherein the collector and the base are short-circuited to each other. The first transistor
And a third transistor in which the second signal is input to the base and the first power supply is connected to the collector, and a third transistor in which the collector and the base are short-circuited to each other to form a differential pair with the third transistor. And a second differential pair comprising four transistors, wherein a contact point connected between the mutually shorted collector and base of the second and fourth transistors is used as an output point, and the output point and the second A first constant current source is connected between the first power supply and the first power supply, and a common emitter of the first differential pair and the second differential pair and a second power supply.
The second and third constant current sources are connected respectively,
And the third constant current source alternately supplies an operating current to the first and second differential pairs, respectively, so that a differential pair of the first and second signal inputs is provided. A signal switching circuit configured to transmit a signal on the side to which the operating current is supplied to the output point,
A fifth transistor connected to a base and having a third reference power supply connected to the collector to output a constant current; and a third differential pair with the fifth transistor, wherein the collector is the first transistor. A sixth transistor connected to a power supply, and a first resistor connected between the common emitter of the third differential pair and the second power supply. A current source configured to connect the third reference power supply to a base and to provide a constant current output to the collector; and a seventh transistor and a fourth differential pair, wherein the collector is the first power supply. And a second resistor connected between the common emitter of the fourth differential pair and the second power supply, and an externally applied switching control and a signal and a fourth reference power source are input to a ratio較回path, this The mutually phase of較回path is reversed 1
And a second output are respectively provided to inputs of first and second waveform conversion circuits, and respective outputs of the first and second waveform conversion circuits are connected to respective bases of the sixth and eighth transistors, respectively. Each of the outputs to the bases is a control signal whose rise is delayed as compared with the fall, and the current of the first constant current source is calculated from the sum of the currents of the second and third constant current sources. A signal switching circuit characterized in that it does not become large. Wherein said first waveform converting circuit is a conductivity type different from the transistors constituting the third and fourth differential pairs, the first output is input to the base from the previous SL ratio較回path A first emitter follower circuit comprising a ninth transistor having the second power supply connected to a collector; and a fourth emitter follower circuit connected between the emitter of the ninth transistor and the first power supply. The second waveform conversion circuit includes a constant current source and a first capacitor connected in parallel with the fourth constant current source, and the second waveform conversion circuit includes a transistor that forms the third and fourth differential pairs. second consisting of different conductivity type, the tenth transistor of the previous SL ratio second output from較回path is input to the base said second power supply is connected to the collector and
Emitter follower circuit, a fifth constant current source respectively connected between the emitter of the tenth transistor and the first power supply, and a fifth constant current source connected in parallel with the fifth constant current source.
Signal switching circuit according to claim 1, wherein which is constituted by a second capacitor that is.