JP3075488B2 - Buffer circuit and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit and a semiconductor integrated circuit including the same, for example, a buffer circuit for reducing the development cost and the development period of a semiconductor integrated circuit.
The present invention relates to a technology that is effective when applied to an SIC (Application Specific Integrated Circuit).

[0002]

2. Description of the Related Art A conventional buffer circuit includes an output buffer and an input buffer, and the number of external terminals is reduced by sharing the same external terminal between the output buffer and the input buffer. is there. In such a buffer circuit, the operation of the input buffer is stopped when data is externally output through the output buffer, and the output buffer is set high when data is externally input through the input buffer. Control is required to bring the output impedance state. For example, two N-channel MOSFETs connected in series to form a main drive circuit for driving a load
And an output buffer having two CMOS inverters arranged corresponding to the two N-channel MOSFETs as a circuit for driving the N-channel MOSFET. To achieve the high output impedance state, the operation of the CMOS inverter is stopped by a control element coupled to the CMOS inverter, and two N-channel MOSFETs forming the main drive circuit are provided.
Can be enabled by turning off the switch. Control elements that enable such control include a transistor connected in series to a P-channel MOSFET forming the CMOS inverter and a transistor connected in parallel to an N-channel MOSFET forming the CMOS inverter. Multiple elements are included.

As examples of documents describing a buffer circuit, there are JP-A-57-7957 and JP-A-55-146965.

[0004]

The inventors of the present invention have studied the conventional buffer circuits. As described above, two N-channel type buffers are connected in series to form a main drive circuit for driving a load. MOSFE
When an output buffer is formed having T and two CMOS inverters arranged corresponding to the two N-channel MOSFETs as a circuit for driving the N-channel MOSFET, such an output buffer is formed. The operation of the buffer circuit is caused by the presence of a control element for setting the circuit into a high output impedance state, and the number of constituent elements of the buffer circuit is increased by the presence of such a control element. Something has been found.

An object of the present invention is to improve an operation delay caused by a control element for setting an output buffer to a high output impedance state.

It is another object of the present invention to reduce the number of control elements for setting an output buffer to a high output impedance state.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, two transistors which are connected in series to form a main drive circuit for driving a load, a first pre-drive circuit and a first pre-drive circuit which are respectively arranged for driving the transistors and correspond to the transistors. When a buffer circuit is formed including a second pre-drive circuit and a state control circuit that enables active / inactive state control based on a logic state of a control signal, the buffer circuit is connected in series to the first pre-drive circuit. A control element and a control element connected in series to the second pre-drive circuit are connected in parallel to each other so as to be shared by the first pre-drive circuit and the second pre-drive circuit. Similarly, two transistors which are connected in series to form a main drive circuit for driving a load, a first pre-drive circuit and a second pre-drive circuit respectively corresponding to the transistors for driving the transistors. When a buffer circuit is formed including a 2 pre-drive circuit and a state control circuit that enables active / inactive state control according to a logical state of a control signal, the first pre-drive circuit and the second pre-drive circuit are formed. A control element connected in series with the circuit is shared by the first pre-drive circuit and the second pre-drive circuit. Further, a semiconductor integrated circuit including such a buffer circuit is formed. In a specific mode, the pre-drive circuit is a P-channel type M
A CMOS inverter formed by connecting an OSFET and an N-channel MOSFET in series can be provided. In this case, the control element is disposed between the P-channel MOSFET constituting the CMOS inverter and the high-potential-side power supply. Transistor.
And an input buffer test mode including an input buffer sharing an external terminal with the main drive circuit and enabling an operation test of the input buffer by setting the main drive circuit to a high output impedance state. The transistor disposed between the P-channel MOSFET constituting the CMOS inverter and the high-potential-side power supply is turned off when a test signal for an operation test of the input buffer is asserted. Type MOSFET and a second P-channel type MOSFET which is turned on when an enable signal is asserted.

[0010]

According to the above means, the control element connected in series to the first pre-drive circuit and the control element connected in series to the second pre-drive circuit are connected in parallel to each other. Sharing by the first pre-drive circuit and the second pre-drive circuit is equivalent to increasing the gate width of the control element, and enables an increase in current. This works to reduce the operation delay caused by the control element. Further, the fact that the control element connected in series to the first predrive circuit and the second predrive circuit is shared by the first predrive circuit and the second predrive circuit means that the number of control elements is reduced. Acts to reduce.

[0011]

FIG. 3 shows a network processor including an input / output buffer according to an embodiment of the present invention, and a communication control system to which the network processor is applied.

In FIG. 1, reference numeral 1 denotes a network processor according to the present embodiment, which comprises, for example, a network processing module 2 and a shared memory control module 3
In one semiconductor substrate such as silicon.
The network processing module 2 is a standard macro cell or a standard cell in the ASIC or the standard cell system. Before describing the details of the network processor 1, a communication control system will be briefly described.

Reference numeral 10 denotes a system bus.
The PU 11, the main memory 12, the network processor 1 of this embodiment, and the like are connected. The network processor 1 is also interfaced with a local bus 13 and a shared memory 14 in addition to the system bus 10. For example, a local memory 15 and an ISDN controller 16 are coupled to the local bus 13. The shared memory 14 is a buffer memory shared by the network processing module 2 and the host CPU 11, and is used, for example, as a temporary storage area for reception data and transmission data by a serial communication interface included in the network processing module 2. Shared memory control module 3
Performs arbitration control as to whether the shared memory 14 is accessed by the network processing module 2 or by the host CPU 11. Although not particularly limited, the network processing module 2 has a function as a general-purpose microcomputer having a serial communication interface function, and has a CPU
20 and two serial communication interfaces controlled thereby (hereinafter simply referred to as SC).
20, 21 and their respective SCIs 20, 2
1. Direct memory access controllers (hereinafter simply referred to as DMACs) 22, 2 provided corresponding to
3 and timers 24 and 25, and an input / output circuit 2 for exchanging information with the outside of the module 2.
6 are provided, which are connected to an internal bus 27.

Although the shared memory control module 3 is not particularly limited, the network processing module 2
An input / output circuit 30 for exchanging information with the system bus 10 and an input / output circuit 31 for exchanging information with the system bus 10, and the input / output circuit 30 or 31 is selectively connected to the shared memory 14. A bus switch circuit 32 for controlling connection to the network processing module 2
An arbitration circuit 33 that performs arbitration control in accordance with an access request from the system bus and an access request from the system bus 10 is provided. The network processing module 2 and the shared memory control module 3 included in the network processor 1 can be configured as separate chips, and in that case, they are commonly connected to the local bus 13 due to the functions of the respective circuit modules 2 and 3. Will be. Therefore, the network processing module 2 and the shared memory control module 3 in the network processor 1 of the present embodiment are directly and commonly connected to a predetermined external terminal group 40 such as bonding pads and bump electrodes via the respective input / output circuits 26 and 30. Interface with the local bus 13. The bus switch circuit 32
Can be interfaced with the shared memory 14 via a predetermined external terminal group 41, and the input / output circuit 31 can be interfaced with the system bus 10 via a predetermined external terminal group 42.

FIG. 4 schematically shows a layout configuration example of the network processor 1. In FIG. 4, reference numeral 50 denotes a semiconductor substrate, the periphery of which is an arrangement area (hereinafter, also simply referred to as a peripheral area) 51 for an input / output buffer, a bonding pad, and the like, and the center thereof is a circuit cell formation area 52
Assigned as. In the network processing module 2, a circuit portion excluding the input / output circuit 26 is included in the cell formation region 52, and the input / output circuit 26 is
Formed. Here, the input / output circuit 26 is composed of a plurality of input / output buffers. For example, FIG. 4 typically shows one input / output buffer 26A. In the shared memory control module 3, the circuit portion excluding the input / output circuits 30 and 31 is included in the cell forming area 52, and the input / output circuits 30 and 3
1 is formed in the peripheral region 51. Here I / O circuit 3
Each of 0 and 31 is composed of a plurality of input / output buffers. For example, FIG. 4 shows one input / output buffer 30A included in the input / output circuit 30 and one input / output buffer 31A included in the input / output circuit 31. Are representatively shown. The input / output buffers 26A and 30A are connected to the external terminal group 40.
Are directly connected in common to a predetermined external terminal 40A included in. Although not shown in FIG. 4, the input / output circuit 26,
Other corresponding input / output buffers included in 30 are directly connected in common to predetermined external terminals.

Next, details of all input / output buffers included in the network processor 1 will be described. Since the input / output buffers included in the network processor 1 can have basically the same configuration, the configuration of the input / output buffer 31A will be described in detail in the following description.

FIG. 5 shows a configuration example of a main part of the input / output buffer 31A.

The input / output buffer 31A shown in FIG.
An output buffer 60 and an input buffer 61 are included. The output buffer 60 includes, but is not limited to, two transistors 75 and 76 connected in series to form a main drive circuit MD for driving a load. Although not particularly limited, the two transistors 75 and 76 are N-channel MOSFETs, and the serially connected portion is an output terminal of the output buffer 60 and is coupled to the external terminal 42. MOSFET 75 is coupled to high potential power supply Vdd, and MOSFET 76 is coupled to low potential power supply Vss. And these two MOS
The FETs 75 and 76 can be driven by pre-drive circuits PD1 and PD2 disposed in front of the FETs 75 and 76, respectively.

Although not particularly limited, the pre-drive circuit PD1 includes a CM in which a P-channel MOSFET 65 and an N-channel MOSFET 66 are connected in series.
This is an OS inverter. Also, the pre-drive circuit PD
2 is a P channel type MOSFE, although not particularly limited.
A CMOS inverter is formed by connecting T71 and N-channel MOSFET 72 in series. The data DATA to be externally output is directly transmitted to the gates of the two MOSFETs 71 and 72 forming the pre-drive circuit PD2, while the gates of the two MOSFETs 65 and 66 forming the pre-drive circuit PD1 receive the data D
ATA is transmitted after being inverted by the inverter 62, whereby the pre-drive circuits PD1, PD2
Are operated complementarily. That is, the pre-drive circuit P
When D1 is at a high level output, the predrive circuit PD2 is at a low level output, and when D1 is at a low level output, the predrive circuit PD2 is at a high level output.

P forming the pre-drive circuit PD1
An enable signal EN * for making the output buffer 60 operable is provided to the channel type MOSFET 65.
-Channel MOSFET 6 whose operation is controlled by
4 and a P-channel MOSFET 63 whose operation is controlled by a test signal TEST for enabling an operation test of the input buffer 61 are connected in series. This P-channel MOSFET 63 is coupled to the high potential power supply Vdd. Further, an N-channel MOSFET 68 whose operation is controlled by the enable signal EN * and an N-channel MOSFET 67 whose operation is controlled by the test signal TEST are connected in parallel to the N-channel MOSFET 66 forming the pre-drive circuit PD1. Is done. These MOSFETs 66, 67, 68
It is coupled to the low potential side power supply Vss.

Similarly, the P-channel MOSFET 71 forming the pre-drive circuit PD2 includes a P-channel MOSFET 70 whose operation is controlled by the enable signal EN * and a P-channel MOSFET 69 whose operation is controlled by the test signal TEST. Are connected in series. This P-channel MOSFET 69
Is coupled to the high potential side power supply Vdd. Further, an N-channel type MOSF forming the pre-drive circuit PD2
The ET 72 is connected in parallel with an N-channel MOSFET 74 whose operation is controlled by the enable signal EN * and an N-channel MOSFET 73 whose operation is controlled by the test signal TEST. This MOSF
The ETs 72, 73, 74 are coupled to the lower potential power supply Vss.

In the above configuration, the test signal TEST
Are negated to a low level and the enable signal EN * is asserted to a low level, the P-channel MOSFETs 63, 64, 69, 70 are turned on, and the N-channel MOSFETs 67, 68, 7 are turned on.
3, 74 are turned off. In such a state, the pre-drive circuits (CMOS inverters) PD1 and PD2 are operated in response to the logical state of the data DATA, whereby the main drive circuit (N-channel MOSF) is operated.
ET75, 76) Since the MD is driven, the data DAT
A is in an external output enabled state. At this time, the input buffer 61 is inactive.

Next, when the enable signal EN * is negated to the high level while the test signal TEST is negated to the low level, the P-channel MOS
The FETs 64 and 70 are turned off, and the N-channel type M
Since OSFETs 68 and 74 are turned on, predrive circuits PD1 and PD2 are inactivated. In such a state, the N-channel MOSFETs 75, 76
Is turned off, and the output buffer 60 is set to a high output impedance state. When the input buffer 61 is enabled in this state, the external terminal 4
2, data can be taken in from the outside.

When the test signal TEST is asserted to a high level, Vil of the input buffer 61
(Input low level voltage), Vih (input high level voltage) test mode, and the predrive circuits PD1 and PD2 are deactivated as in the case where the enable signal EN * is negated to the high level. N
The channel type MOSFETs 75 and 76 are turned off, and the output buffer 60 is set to a high output impedance state. In this state, the operation test of the input buffer 61 is enabled by supplying predetermined test data from the outside.

Here, the MOSFETs 63 and 69 and the MO
The SFETs 64 and 70 are simultaneously turned on / off in response to the test signal TEST and the enable signal EN *, respectively. Further, while the data DATA is transmitted directly to the MOSFET 71, the MOSFET 65 is inverted by the inverter 62. Therefore, the MOSFETs 65 and 71 are always turned on complementarily, and are not turned on at the same time. Therefore, in this embodiment, as shown by the broken line in FIG.
The series connection point of 63, 64 and the series connection point of MOSFET 69, 70 are connected, and MOSFET 64, 65
Is connected to the series connection point of the MOSFETs 70 and 71, in other words, the pre-driver circuit P
MOSFETs 63 and 64 and MOSFETs 69 and 7 connected in series as D1 and PD2 operation control elements.
0 in parallel with the MOSFET 6
3, 64, 69, and 70 are shared by the pre-driver circuit PD1 and the pre-driver circuit PD2. Such a connection is made possible by the aluminum wiring layer. As described above, the MOSFETs 65 and 71 are always turned on complementarily and they are not turned on at the same time.
The parallel connection of the MOSFETs as described above does not affect the circuit operation at all. As a result of such a configuration, the circuit configuration shown in FIG. 5 is equivalently shown in FIG. 1, and the P-channel type MOS shown in FIG.
The FETs 63, 69 and 69, 70 are equivalent to one P-channel MOSFET 80 and one P-channel MOSFET 90, respectively, as shown in FIG. Then, in that case, the MO shown in FIG.
Assuming that the gate widths of the SFETs 63, 64, 69 and 70 are W, the MOSFETs 80 and 90 equivalently shown in FIG.
Have a gate width of 2W. That is, the gate width is doubled. And in that case, MOSFETs 65 and 7
1 is always turned on complementarily.
5 and 71, it is possible to flow more current than in the case of FIG. As a result, MOSFET 65,
Since the load driving capability of the MOSFET 71 is increased,
The rise of the voltage waveform when the gate level of the gate 76 or 76 is changed from low to high is sharpened, whereby the switching speed of the output buffer 60 is improved.

FIG. 2 shows a simulation result of the input / output buffer of this embodiment.

As shown in FIG. 2, when the load capacity of the input / output buffer is 15 PF, the delay time before the improvement is 0.90.
5 ns after improvement (MOSFETs 63 and 6
4 and MOSFETs 69 and 70 are connected in parallel), the delay time is 0.845 ns. Similarly, when the load capacity is 15 PF, the delay time before the improvement is 1.457 ns, whereas the delay time after the improvement is 1.307 ns. When the load capacity is 150 PF, the delay time before the improvement is The delay time after improvement is 2.488 ns compared to 2.671 ns. That is, the operation speed of the output buffer after the improvement is about 0.1 ns to 0.2 ns as compared to before the improvement.
Speed up.

According to the above embodiment, the following effects can be obtained.

(1) A MOSF connected in series as an element for controlling the operation of the pre-driver circuits PD1 and PD2
By connecting the ETs 63, 64 and the MOSFETs 69, 70 in parallel, the MOSFETs 63, 64, 69,
70, the pre-driver circuit PD1 and the pre-driver circuit P
D2 and D2, the pre-driver circuit PD1 and the pre-driver circuit P1 can be shared without increasing the occupied area.
Since the gate width of the MOSFET serving as the control element of D2 is equivalently enlarged and a larger amount of current can flow, the operation speed of the output buffer 60 is improved.

(2) In order to realize the Vil (input low-level voltage) and Vih (input high-level voltage) test modes of the input buffer 61, a P-channel MOSFET is used.
When 63 and 69 are provided, the number of serial elements of the control element increases, so that the effect (1) is particularly remarkable.

(3) A MOSF connected in series as an element for controlling the operation of the pre-driver circuits PD1 and PD2
The buffer circuit having the configuration shown in FIG. 1 is equivalently obtained by connecting the ETs 63 and 64 and the MOSFETs 69 and 70 in parallel. On the other hand, when the circuit configuration shown in FIG. P-channel type MO as control element connected in series to circuits PD1 and PD2
Since the number of SFETs is two as shown by 80 and 90 in FIG. 1, the number of the control elements is halved from the case shown in FIG. Reduction can be achieved. In this case, by increasing the gate widths of the P-channel MOSFETs 80 and 90, the current flowing through the control element can be increased as described above, and the operation speed can be improved. The gate widths of the MOSFETs 80 and 90 are changed to the P-channel type MOSFETs 63 and
When the number is equal to that of 64, 69, and 70, the occupation area of the output buffer 60 and the input / output buffer 31A including the same can be reduced by the reduced number of control elements.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. No.

For example, in the above embodiment, the input buffer 6
In order to realize the Vil (input low-level voltage) and Vih (input high-level voltage) test modes of 1, a description has been given of a case in which the P-channel MOSFETs 63 and 69 are provided. , The P-channel MOSFETs 64 and 70 as control elements operated by the enable signal EN * are connected in parallel to share the MOSFETs 64 and 70 with the pre-drive circuits PD1 and PD2.
Since the gate width of the MOSFET is equivalently increased and more current can flow, the switching speed of the output buffer 60 can be improved by increasing the load driving capability.

The MOSFET described in this specification
Is M for gate-insulated field-effect transistor
It should be understood to include ISFET.

In the above description, the case where the invention made by the present inventor is mainly applied to a network processor, which is the field of application, has been described.
The present invention is not limited to this, and can be widely applied to various types of semiconductor integrated circuits such as general-purpose processors and microcomputers, as well as RAMs (random access memories) and ROMs (read only memories). .

The present invention can be applied on condition that at least an output buffer for driving a load is included.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a control element connected in series to the first pre-drive circuit and a control element connected in series to the second pre-drive circuit are connected in parallel to each other, and the first pre-drive circuit and the second By being shared by the pre-drive circuit, the current flowing through the control element is increased, and the operation delay caused by the control element is reduced, so that the operation speed of the buffer circuit can be improved. Further, the control elements connected in series to the first predrive circuit and the second predrive circuit are shared by the first predrive circuit and the second predrive circuit, thereby reducing the number of control elements. be able to.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a main part of an input / output buffer according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a simulation result of the circuit of the present embodiment.

FIG. 3 is a configuration block diagram of a network processor including the input / output buffer and a communication control system to which the network processor is applied;

FIG. 4 is a schematic explanatory diagram of a layout configuration example of the network processor.

FIG. 5 is an electrical connection diagram of a main part of an input / output buffer which is a premise of the equivalent circuit shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 network processor 2 network processing module 26 input / output circuit 30 input / output circuit 31 input / output circuit 26A input / output buffer 30A input / output buffer 31A input / output buffer PD1 predrive circuit PD2 predrive circuit MD main drive circuit 60 output buffer 61 input buffer 62 Inverter 63 P-channel MOSFET 64 P-channel MOSFET 65 P-channel MOSFET 66 N-channel MOSFET 67 N-channel MOSFET 68 N-channel MOSFET 69 P-channel MOSFET 70 P-channel MOSFET 71 P-channel MOSFET 72 N-channel MOSFET MOSFET 73 N-channel MOSFET 74 N-channel MOSFET T 75 N-channel MOSFET 76 N-channel MOSFET 80 P-channel MOSFET 90 P-channel MOSFET

Claims (6)

(57) [Claims] 1. Two transistors that are connected in series to form a main drive circuit for driving a load, a first pre-drive circuit and a first pre-drive circuit that are respectively arranged for driving the transistors and correspond to the transistors. In a buffer circuit including a second pre-drive circuit and a state control circuit that enables active / inactive state control based on a logical state of a control signal, the state control circuit is connected in series to the first pre-drive circuit. A first control element and a second control element connected in series to the second pre-drive circuit, and the control elements are connected in parallel with each other to form the first and second pre-drive circuits. A buffer circuit characterized by being shared by 2. Two transistors which are connected in series to form a main drive circuit for driving a load, a first pre-drive circuit and a first pre-drive circuit which are respectively arranged for driving the transistors and correspond to the transistors. In a buffer circuit including a second pre-drive circuit and a state control circuit that enables active / inactive state control based on a logic state of a control signal, the state control circuit includes the first pre-drive circuit and the second pre-drive circuit. A buffer circuit having a control element connected in series to a predrive circuit, wherein the control element is shared by the first predrive circuit and the second predrive circuit. 3. The first pre-drive circuit and the second pre-drive circuit each include a P-channel MOSFET.
And an N-channel MOSFET connected in series
A MOS inverter, and the control element includes the CM
P-channel type MOSFET that constitutes OS inverter
3. The buffer circuit according to claim 1, wherein the transistor is a transistor disposed between the power supply and the high-potential-side power supply. 4. 4. An input buffer test mode including an input buffer sharing an external terminal together with the main drive circuit and enabling an operation test of the input buffer by setting the main drive circuit in a high output impedance state. At this time, the transistor disposed between the P-channel MOSFET constituting the CMOS inverter and the high-potential-side power supply is turned off by the assertion of the test signal for the operation test of the input buffer. A P-channel MOSFET;
4. The buffer circuit according to claim 3, wherein the buffer circuit is a second P-channel MOSFET that is turned on when the enable signal is asserted. 5. The two transistors forming the main drive circuit are both N-channel MOSFETs, and a serial connection of the two N-channel MOSFETs is an output terminal of the main drive circuit. , 2, 3 or 4. 6. A semiconductor integrated circuit including the buffer circuit according to claim 1, 2, 3, 4, or 5.