JP3075799B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a semiconductor device, particularly an active matrix liquid crystal display thin film transistor using a polycrystalline silicon in the manufacture of: a process for producing a (Thin Film Transistor hereinafter referred to as TFT).

[0002]

2. Description of the Related Art There are several methods for manufacturing a TFT. First, a method using an inverted stagger technique will be described. FIG. 6 shows the characteristic manufacturing flow. First, a gate layer 2 is formed on an insulating substrate 1 and patterned.
Then, the gate layer 2 is covered with the gate insulating layer 3. next,
An undoped thin-film polycrystalline silicon layer 4 is formed and patterned into a predetermined shape.

Next, a doped polycrystalline silicon layer and a metal layer are sequentially laminated, patterned into a predetermined shape, and joined to an undoped thin-film polycrystalline silicon layer 4.
A doped polycrystalline silicon layer 5 serving as a source / drain region of the TFT and a metal layer 6 serving as a source / drain electrode of the TFT are obtained in contact with the doped polycrystalline silicon layer 5. Next, a passivation insulating layer 7 is formed on the entire surface of the substrate. After that, by exposing the substrate to the hydrogen plasma 8, the hydrogen atoms generated in the plasma permeate the passivation insulating layer 7 and diffuse into the layer below. Some of the hydrogen atoms reach the undoped thin-film polycrystalline silicon layer 4 and saturate, for example, dangling bonds (covalently bonded crystals, which are unsaturated bonds due to lattice defects near the crystal surface or the like). 4 will be improved.

Next, a method of manufacturing a TFT using the coplanar technology will be described with reference to FIG. In this method, first, an undoped thin-film polycrystalline silicon layer 4 is formed on an insulating substrate 1, and this is patterned into a predetermined shape. Next, a layer to be the gate insulating film 3 and a layer to be the gate layer 2 are sequentially stacked, and these layers are patterned so as to remain in a portion to be a channel region of the TFT. Next, ions are implanted into the undoped thin-film polycrystalline silicon layer 4 using the remaining gate insulating film 3 and gate layer 2 as a mask, and the doped polycrystalline silicon layer 5 serving as a source / drain region of the TFT is self-aligned. obtain. Next, a passivation insulating layer 7 is formed over the entire surface of the substrate and patterned,
A portion of the doped polycrystalline silicon layer 5 is exposed, and a metal layer 6 is formed and patterned to form a TF that is in contact with the partially exposed doped polycrystalline silicon layer 5.
T source / drain electrodes are obtained. Thereafter, by exposing this substrate to hydrogen plasma, hydrogen atoms are diffused into the undoped thin-film polycrystalline silicon layer 4 to improve the properties of the undoped thin-film polycrystalline silicon layer 4.

Further, a method of manufacturing a TFT using the stagger technique will be described with reference to FIG. In this method, first, a doped polycrystalline silicon layer 5 is formed on a substrate 1 and patterned into a predetermined shape to form source / drain regions of a TFT. Next, an undoped thin-film polycrystalline silicon layer 4 is deposited and patterned to form a TFT.
Channel region. Next, a gate insulating film 3 and a semiconductor layer serving as a gate layer are deposited on the entire surface of the substrate, and the semiconductor layer serving as the gate layer is patterned so as to remain only above the channel region of the TFT to form the gate layer 2. Next, a passivation insulating layer 7 is deposited on the entire surface of the substrate, and the passivation insulating layer 7 and the gate insulating layer 3 are patterned into a predetermined shape, and the doped polycrystalline silicon layer 5 serving as a source / drain region of the TFT is formed. Partially exposed. Then, a metal layer 6 is deposited and patterned to obtain a source / drain electrode which is in contact with the partially exposed doped polycrystalline silicon layer 5. Thereafter, the substrate is exposed to hydrogen plasma 8 to diffuse hydrogen atoms to the undoped thin - film polycrystalline silicon layer 4, thereby improving the properties of the undoped thin - film polycrystalline silicon layer 4.

[0006]

The conventional method for manufacturing a semiconductor device is configured as described above. From the viewpoint of manufacturing, it is desirable that the hydrogen plasma treatment be performed in a short time.
Therefore, it is desirable to use high density plasma.
This can be realized by using a high-power rf plasma or a plasma device such as an electron cyclotron resonance microwave plasma.

However, during the plasma process because of the nature improve undoped thin polycrystalline silicon layer, a passivation insulating layer becomes be directly exposed to the hydrogen plasma, the treatment using the high-density hydrogen plasma as described above In this case, the passivation insulating layer may be damaged by, for example, ions or radiation in the plasma.

[0008] The existence of such a defect in the passivation insulating layer cannot be implied. This is because when a pixel of a liquid crystal image display device is controlled using the above-described TFT, the passivation insulating layer of the TFT is used as a dielectric of the capacitor. Is stopped and a charged state is obtained. In particular, in the case of a TFT formed by using the inverse stagger method, it is well known that the presence of charges in the passivation insulating layer has a bad influence on the performance of the TFT, and in particular, the leakage current is increased.

[0009] The present invention has been made to solve the above problems, it is possible to prevent the damage of the passivation insulating layer during plasma processing due to the nature improve undoped thin polycrystalline silicon layer With
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of supplying sufficient hydrogen to an undoped thin-film polycrystalline silicon layer.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an insulating protective film on a predetermined portion of an undoped thin-film polycrystalline silicon layer; With a doped polycrystalline silicon layer, and a step of plasma-treating the substrate covered with the doped polycrystalline silicon layer to improve the crystalline state of the undoped thin-film polycrystalline silicon layer.

[0011]

[Action] In the present invention, after forming the insulating protective film on the undoped thin polycrystalline silicon layer, the entire surface of the substrate de
In this state, high-energy ions, electrons, photons, X-rays, etc. are prevented from entering, and the lower insulating protective film is doped.
And the polycrystalline silicon layer protects the insulating protective film from damage. Further, since the doped polycrystalline silicon layer has a high permeability for hydrogen atoms, hydrogen atoms can be sufficiently diffused into the undoped thin-film polycrystalline silicon layer.

[0012]

Embodiments of the present invention will be described below. First, the principle used in the present invention will be described with reference to FIGS. FIG. 4 shows SiO ₂ as an insulating film on crystalline silicon 10.
11 has been formed by thermal growth, SiO ₂ 1
5 shows a case where there is no protective film, and FIG. 5 shows a case where SiO ₂ 11 is formed on crystalline silicon 10 and a doped polycrystalline silicon layer 13 is further formed. For example, as shown in FIG. 4 (b), an electrode 12 is provided on the semiconductor thus constituted, and a metal / insulator / semiconductor structure ( Metal / Insulation / Semico ) composed of crystalline silicon 10, SiO ₂ 11 and aluminum 12 is formed.
nductor: MIS structure) capacitor
The characteristic is evaluated by obtaining a −V curve. This CV curve shows that the SiO ₂ 11 was placed in an electron cyclotron resonance microwave plasma reaction chamber at a pressure of 0.35 mTorr,
W after exposure to hydrogen plasma for 10 minutes at a flow rate of 15 sccm.

When there is no protective film as shown in FIG.
The change in the height of the CV curve occurs at a negative voltage of about -18V. This indicates that a defect is formed in the insulating film (SiO ₂ 11) during the plasma treatment, and that there is a positive charge due to the charge charged to the defect.

On the other hand, in the structure shown in FIG. 5A, the doped polycrystalline silicon
Since the entire surface of the insulating film (SiO ₂ 11) is covered with 3, the change in the height of the CV curve occurs at only −4 V as shown in FIG. This is because the amount of the introduced positive charges in the insulating film after the hydrogen plasma treatment, doping
2 shows that the insulating layer is reduced by covering the insulating layer with the polycrystalline silicon layer 13. The same results as described above were obtained in the hydrogen plasma treatment performed under different conditions.

Next, a specific example using the above principle will be described. That is, FIG. 1 is a view showing a method of manufacturing a semiconductor device according to one embodiment of the present invention. The above-described principle is applied to an inverted staggered thin film transistor, and a doped polycrystalline silicon layer 5 becomes a protective film in hydrogen plasma processing. In the figure, the same reference numerals as those in FIG. 6 denote the same or corresponding parts, and 17 denotes a part excluding the vicinity of the source / drain regions on the gate insulating layer 3 and undoped polycrystalline above the gate layer 2. A passivation insulating layer 15 formed above the silicon layer 4; a doped polycrystalline silicon layer 15 formed on the entire surface so as to cover the entire passivation insulating layer 17; 3 shows a silicon layer.

Next, the manufacturing method will be described. First, as shown in FIG. 1A, a semiconductor layer serving as a gate layer is formed on an insulating substrate 1 and patterned to obtain a gate layer 2. Next, the gate layer 2 is covered with the gate insulating layer 3. Next, an undoped thin-film polycrystalline silicon layer 4 is formed and patterned into a predetermined shape. And S
depositing a passivation insulating layer 17 of iO ₂ ,
This is located outside the region where the source / drain electrodes are formed,
Then, patterning is performed so as to remain only above the undoped thin-film polycrystalline silicon layer 4 above the gate layer 2, and a doped polycrystalline silicon layer 15 is further deposited thereon. The layer thickness of the doped polycrystalline silicon layer 15 is such that damage by plasma, for example, high-energy photons, X-rays, ions, and electrons are absorbed, the passivation insulating layer 17 is protected from damage by hydrogen plasma, and hydrogen atoms are
A value is set so that the light passes through the doped polycrystalline silicon layer 15 and is diffused downward (15a) .

By exposing the substrate to hydrogen plasma 8, hydrogen atoms are diffused into the undoped thin-film polycrystalline silicon layer 4, and the properties of the layer 4 are improved. Next, gold
A metal layer 6 is formed, and the metal layer 6 and the doped polycrystalline silicon layer 15 are patterned (15a) to obtain source / drain electrodes.

As described above, according to the present embodiment, the passivation insulating layer 17 of the thin film transistor is completely covered with the doped polycrystalline silicon layer 5 during the hydrogen plasma treatment, and the doped polycrystalline silicon layer 5 is exposed to the hydrogen plasma. Layer 5 is the underlying passivation insulating layer 17
Is protected from damage by the plasma, so that no adverse effect due to the leak current of the TFT is observed. This means
This is proved by the transfer characteristics of the thin film transistor before and after the hydrogen plasma treatment shown in FIG. In this figure, the gate width / gate length of the TFT is 132/90, the voltage between the source and the drain is 15 V, and the hydrogen plasma processing is performed at a pressure of 0.degree.
This shows the results when the operation was performed at 35 mTorr, 400 W, and an outflow rate of 15 sccm for 10 minutes. As can be seen from the figure, the threshold characteristics of the device were significantly improved by the hydrogen plasma treatment, and no increase in the leak current was observed. This indicates that hydrogen atoms diffused into the undoped thin-film polycrystalline silicon layer 4 to improve its properties, and that the passivation insulating layer 17 was not damaged.

In this method, since the existing doped polycrystalline silicon layer can be used as a protective film for the passivation insulating layer, the manufacturing process does not become complicated.

Next, a second embodiment of the present invention will be described. In this embodiment, the principle of the present invention is applied to a coplanar or staggered TFT. In this embodiment, unlike the above-described inverted staggered TFT, an existing doped polycrystalline silicon layer is used as a protective film. I can't.

Therefore, in this embodiment, as shown in FIG. 3 (a), after forming the passivation insulating layer 7 on a predetermined portion, a doped polycrystalline silicon layer 13 is newly formed on the entire surface of the substrate. A process using hydrogen plasma 8 is performed. Then, a metal layer 6 is deposited, and the metal layer 6 and the doped polycrystalline silicon layer 13 are patterned to form source / drain electrodes.

By doing so, the manufacturing process is slightly increased, but the same effect as in the above embodiment can be expected.

In each of the above embodiments, a method of manufacturing a thin film transistor having a single gate has been described. However, it is needless to say that the present invention can be applied to a case of manufacturing a thin film transistor having a plurality of gates.

In the above embodiment, the case of performing the plasma processing using the hydrogen plasma containing only pure hydrogen gas has been described. However, the present invention is also applicable to the case of performing the hydrogen plasma processing including another gas such as nitrogen or argon. It goes without saying that you can do it.

[0025]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, after an insulating protective film is formed on an undoped thin-film polycrystalline silicon layer, the entire surface of the substrate is doped polycrystalline. Since it is covered with a silicon layer and is subjected to plasma processing in this state, the lower insulating protective film is protected by the doped polycrystalline silicon layer, damage to the insulating protective film is reduced, and therefore, a good channel is provided. There is an effect that a TFT having no leak current can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing flow of a semiconductor device (inverted stagger type polycrystalline silicon thin film transistor) according to one embodiment of the present invention.

FIG. 2 is a diagram for explaining operating characteristics of a semiconductor device (inverted staggered polycrystalline silicon thin film transistor) according to one embodiment of the present invention.

FIG. 3 is a view showing a manufacturing flow of a semiconductor device (coplanar polycrystalline silicon thin film transistor) according to another embodiment of the present invention.

FIG. 4 is a diagram for explaining the characteristics of the semiconductor device of the present invention, and shows a C-C
The figure which shows a V measurement result.

FIG. 5 is a diagram for explaining characteristics of the semiconductor device of the present invention, and illustrates CV by hydrogen plasma using a protective film.
The figure which shows a measurement result.

FIG. 6 is a diagram showing a manufacturing flow of a conventional semiconductor device (inverted staggered polycrystalline silicon thin film transistor).

FIG. 7 is a view showing a manufacturing flow of a conventional semiconductor device (coplanar polycrystalline silicon thin film transistor).

FIG. 8 is a view showing a manufacturing flow of a conventional semiconductor device (a staggered polycrystalline silicon thin film transistor).

[Explanation of symbols]

REFERENCE SIGNS LIST 1 insulating substrate 2 gate layer 3 gate insulating layer 4 undoped thin-film polycrystalline silicon layer 5, 13, 15 doped polycrystalline silicon layer 6 metal layer 7, 17 passivation insulating layer 8 hydrogen plasma 10 crystalline Si 11 thermally grown SiO ₂

Claims (1)

(57) [Claims] An undoped thin-film polycrystalline silicon layer serving as a transistor channel is formed on an insulating substrate.
A method of manufacturing a semiconductor device in which an insulating protective film is formed and a plasma process is performed, wherein a step of forming an insulating protective film in a predetermined region on an undoped thin-film polycrystalline silicon layer formed on an insulating substrate; Covering the entire surface of the substrate on which is formed with a doped polycrystalline silicon layer; and plasma-treating the substrate covered with the doped polycrystalline silicon layer to improve the crystalline state of the undoped thin-film polycrystalline silicon. A method for manufacturing a semiconductor device, comprising: