JP3076082B2 - Shielded gate type static induction transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic induction transistor (SIT). More specifically, a shielded gate type that shields the gate area and improves triode characteristics
About SIT.

[0002]

2. Description of the Related Art A conventional SIT has, for example, a structure as shown in a sectional view of FIG. That is, in the figure, reference numeral 11 denotes a semiconductor substrate formed of n ⁻ -type silicon crystal having an impurity concentration of 10 ¹³ to 10 ¹⁴ cm ⁻³ , and 2 denotes a semiconductor substrate 1 in which a donor impurity is further mixed at a high concentration. drain region formed on the n ⁺ -type, 3 a source region formed in the n ⁺ -type are also mixed with donor impurities at a high concentration, 4 are mixed in a high concentration an acceptor impurity such as boron around the source region 3 A gate region formed in the p ⁺ type, 6 is a channel region formed between the drain region 2 and the source region 3, 7 is a protective film formed on the surface of the semiconductor substrate 11, and 8 is formed on the drain region 2 side. The drain electrodes 9 and 10 are a source electrode and a gate electrode formed by punching out the protective film 7, respectively.

In this conventional SIT, when a voltage is applied between the drain electrode 8 and the source electrode 9 and a bias voltage is applied between the source electrode 8 and the gate electrode 9, a depletion layer spreads in the channel region 6 according to the bias voltage. Thus, the current between the drain electrode 8 and the source electrode 9 is controlled. When this bias voltage is set to 0 V, the depletion layer in the channel region 6 disappears, and a current flows between the drain electrode 8 and the source electrode 9 according to the voltage between both electrodes. In this manner, the voltage-current characteristics between the drain electrode 8 and the source electrode 9 change according to the bias voltage of the gate electrode 10, and exhibit characteristics like a triode vacuum tube.

[0004]

However, in this type of conventional SIT, the semiconductor substrate on which the channel region 6 is formed is formed.
11 has a high impurity concentration of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^-3 ,
Even if a reverse bias is applied to the gate to reduce the current to 0, the depletion layer does not easily spread. Therefore, in order to make the current completely zero immediately, the reverse bias must be increased or the distance between gates must be reduced. When the reverse bias is increased, the operation efficiency of the transistor is reduced, and when the distance between the gates is reduced, the source region must be reduced, which is difficult in manufacturing and limits the amount of current. In order to increase the limited amount of current, it was inevitable to take a method of producing many elements on one substrate and operating them in parallel.

[0005] Further, the SIT for simply lowering the impurity concentration of the semiconductor substrate forming the channel region has not been put to practical use because a sufficient current cannot be obtained even when the gate bias voltage is set to 0 V and the transistor is turned on.

The present invention has been made in view of such a situation. When the bias voltage of the gate is set to 0V and the gate is turned on, a necessary current is obtained.
SI with limited current and good triode characteristics of vacuum tubes
The purpose is to provide T.

[0007]

SUMMARY OF THE INVENTION A shielded gate type SI according to the present invention
T is a semiconductor substrate formed of one conductivity type having a low impurity concentration, a drain region formed of the one conductivity type having a high impurity concentration in the semiconductor substrate, and a semiconductor substrate having a high impurity concentration which is opposed to the drain region. A source region formed of the one conductivity type having an impurity concentration and forming a channel region between the drain region and the channel formed of the other conductivity type having a high impurity concentration around the channel region of the semiconductor substrate; A static induction transistor comprising a gate region for adjusting a depletion layer in a region, wherein the transistor is formed at least on the channel region side of the gate region with the one conductivity type having an impurity concentration higher than an impurity concentration of the semiconductor substrate. A shielding region is provided , and the width of the shielding region is equal to the width of a depletion layer due to a diffusion potential.
The width of the shielded area and the impurities in the shielded area
The concentration is expressed by the following formula: L _HY = W _DEP = [2 e _s / q · N _HY · V _bi ] (where L _HY is the width of the shielding region, and W _DEP is the diffusion potential.
Depletion layer width, N _HY impurity concentration of the shielding region, e _s is the semiconductor
The dielectric constant of the substrate, q is the unit charge, V _bi is the gate region and
It represents the diffusion potential of the shielding area. ) To achieve the triode characteristics by an ideal electrostatic induction operation.

[0008]

According to the shielded gate type SIT according to the present invention, the impurity concentration of the semiconductor substrate forming the channel region is made extremely low and close to the intrinsic concentration, and the impurity concentration of the semiconductor substrate is provided on the channel region side of the gate region. Since a higher concentration shielding region is formed, when the bias voltage is 0 V, a depletion layer is formed only in the shielding region, no depletion layer is formed in the channel region, and the current between the drain electrode and the source electrode is reduced. The current is not affected at all, and a sufficient current can be obtained.

On the other hand, when the reverse bias is applied, the impurity concentration in the channel region is set to a very low concentration. Therefore, the depletion layer rapidly spreads to this region with this minute voltage, and the current can be limited.

The operation of forming a depletion layer by the shielding region will be described in more detail. The effect of this shielding area is p
Based on the operation of the ⁺ −n−n ⁻⁻ n ⁺ hyperabrupt junction diode. That is, FIG. 4 shows the type of the impurity added to the junction of the super step junction diode, whether the impurity is n-type or p-type, the impurity concentration distribution, and the electron concentration distribution. In the figure, the horizontal axis represents the distance from the end of the p ⁺ semiconductor layer of the super step junction diode, and the vertical axis represents the impurity concentration and the electron concentration. In the figure, p ⁺ , n, n ⁻ , and n ⁺ are a p ⁺ layer in which the acceptor of the diode is added at a high concentration, for example, about 10 ¹⁸ cm ⁻³ or more, and an appropriate amount of dona, for example, about 2 × 10 ¹⁵ cm ^−3. A doped n-type layer, an n ⁻ layer with a low impurity concentration, and an n ⁺ layer to which a donor is added at a high concentration of, for example, about 10 ¹⁸ cm ⁻³ or more are shown. This n ⁻ layer has an impurity concentration of 4 × 10 ¹¹ cm ^{− The} n layer is formed to have a thickness determined in relation to the impurity concentration so that a depletion layer exists only in the n region under a zero bias state. The figure shows that the bias voltage applied to the junction is zero.
It shows the electron concentration distribution in the diode in the case of V, -1V, -2V, -3V, -4V. Here, a minus sign attached to the voltage value means that a bias was applied in the reverse direction of the junction. It can be seen from the figure that the depletion layer exists only in the n-region in the zero bias state, and that when the reverse bias is applied, the depletion layer rapidly spreads to the n ⁻ region and the electron concentration drops sharply.

Of course, FIG. 4 is an example for explaining the principle of the super-step junction, and the degree of change in the impurity concentration distribution and the electron concentration distribution with respect to the applied voltage of the actually used super-step junction is slightly different from this example. However, it goes without saying that the same effect can be obtained.

As can be seen from FIG. 4, in the n ⁻ region, the electron concentration in the zero bias state is higher than the impurity concentration in the n ⁻ region. This excess is stored electrons supplied from the n ⁺ region. This electron concentration does not decrease even if the impurity concentration of the n ⁻ region becomes lower than this. In the present invention, such accumulated electrons are positively used when the element is conducting.

By applying this principle to the SIT, the spread of the depletion layer in the shielded gate type SIT in the on state of the zero bias element is limited to the n region which is the shield region,
Extremely small compared to conventional junction gate SIT. Therefore, the channel current at this time can flow without being restricted by almost any depletion layer. Therefore, the on-resistance of the device is substantially reduced when there is no shielding area, that is, as compared with the standard junction gate SIT.

On the other hand, when a small reverse bias is applied to the gate electrode, the depletion layer spreads not only in the n region but also in the n ⁻ region. At this time, since the n ⁻ region uses a high-purity silicon crystal layer close to the intrinsic carrier concentration of about 4 × 10 ¹¹ cm ⁻³ ,
The depletion layer between the gate regions and between the gate region and the drain region becomes very large. Of course, the impurity concentration of the n ⁻ region may be different from this.

Therefore, by introducing a shield gate structure into an SIT having a channel region with a low impurity concentration,
On-resistance is reduced, and sufficient current blocking can be achieved when a reverse bias is applied to the gate electrode. Further, almost the entire channel region is depleted by a slight reverse bias, so that the remaining channel resistance can be sufficiently reduced and the exponential function operation in a low current region can be facilitated.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional explanatory view of a grooved shield gate type SIT according to an embodiment of the present invention. 1 high purity, i.e., p-type is low semiconductor substrate impurity concentration, may be any of n-type n in the present embodiment in the drawing ^- described type. This impurity concentration is desirably 10 ¹³ cm ⁻³ or less. This is because if the impurity concentration is higher than 10 ¹³ cm ⁻³ , even if reverse bias is applied, the depletion layer does not spread sufficiently and current control cannot be performed. As the semiconductor substrate, a compound semiconductor such as GaAs, InP, or GaP can be used in addition to silicon (Si) which is usually used. Reference numeral 5 denotes a shielding region provided around the gate region 4, which is formed of the same conductivity type as that of the semiconductor substrate 1 and of n-type having a high impurity concentration. In the same figure, L _HY is the distance between the gate region 4 and the channel region 6 of the shielding region 5, L _SD is the length of the channel region 6 interposed between the drain region 2 and the source region 3, and L _GR is the source region 3 the inner surface and the distance between the upper surface of the gate region 4, L _G is the length of the gate region 4, 2G is distance or shielding region between the shielding area 5 as the distance between the gate region 4, also 2D is shown in Fig. 1 5 N exists between
^- represents the width of the area. Gate area 4 in shielded gate SIT
And the shielding area 5 work together as a gate of the SIT, so the distance 2D between the shielding area 5 and the shielding gate SIT
Can be regarded as an effective gate gap. Hereinafter, this 2D is referred to as an effective gate gap.

The semiconductor crystal substrate 1 according to this embodiment has n
^A method for manufacturing a trench type shield gate type SIT will be described. 2 and 3 are cross-sectional explanatory views showing the manufacturing process.

First, as shown in step a of FIG.
An n ⁺ layer serving as a drain region 2 is formed on one surface of an n ⁻ type semiconductor substrate 1 having a low impurity concentration of Si. In this formation method, since the semiconductor substrate 1 has a very low concentration, it can be formed effectively by performing a solute supply method as disclosed in JP-A-63-81916 for epitaxial growth.
Of course, the n ⁻ region and the n ⁺ region can be formed by other methods. For example, an n ⁻ substrate and an n ⁺ substrate may be bonded to each other, or an n ⁻ layer may be formed on the n ⁺ substrate by a low-temperature vapor deposition method. The thickness of the drain region 2 is preferably small in order to reduce the thermal resistance to heat generated inside the element during operation,
On the other hand, since it is necessary to support the active region of the element, an appropriate value is set in consideration of the element size, heat loss, and element manufacturing process. Usually, this is formed to a thickness of about 50 to 500 μm. Here, phosphorus (P) or arsenic (As) is used as an impurity added to form the n ⁺ -type.

Next, as shown in step b of FIG. 2, the other surface of the semiconductor substrate 1 is polished so that the thickness becomes an appropriate value within the range of 5 to 30 μm, and the surface is mirror-finished. Thereafter, as shown in step c of FIG. 2, the surface of the semiconductor substrate 1 finished to a mirror surface is subjected to silicon dioxide (SiO ₂ ) by thermal oxidation or the like.
Then, using this as a mask, P is selectively diffused to a high concentration of about 1 μm to form an n ⁺ -type source region 3. This source region 3 may be formed after the step of forming the next gate region 4 instead of this step.

Next, as shown in step d of FIG. 2, a groove 22 of about 2.5 μm is dug by reactive etching or the like. Here, the groove can be formed by plasma etching or solution etching, but the reactive etching method is suitable for forming an accurate groove structure. Then, as shown in step e of FIG.
A thin SiO ₂ film 23 is deposited on the entire surface by the method. This Si
Since the O ₂ film 23 is thin and can be formed in a short time, it may be formed by a thermal oxidation method. Next, as shown in step f of FIG.
P ions are selectively implanted into the groove 22 via the SiO ₂ film 23 to form an n layer in the shield region 5. Here, As may be used instead of P. As a condition for driving,
It is preferable to adjust the acceleration voltage and the ion dose so that the projection range is 2.5 μm and the concentration is 5 × 10 ¹⁵ cm ⁻³ . This n-layer can be formed not only by ion implantation but also by diffusion of low-concentration P or As or low-temperature vapor growth of a Si layer to which a predetermined amount of P or As is added.

Next, as shown in step g of FIG.
After removing the upper SiO ₂ film 23, a photoresist 24 is applied to the entire surface, and B (boron) is implanted using the photoresist 24 as a mask to form a p ⁺ layer of the gate region 4. Here, as a mask for implantation, the SiO ₂ film 23 is removed and photoresist is removed.
Although the coating 24 is used, the SiO ₂ film 23 can be used as a mask as it is. In addition, unlike the implantation of P, it is desirable to adjust the acceleration voltage and the ion dose so that the projection range is as short as possible and the concentration is as high as about 10 ²⁰ cm ⁻³ . Thus, the thickness of the n-layer is set to about 0.94 μm. Of course, similarly to the case of forming the n-layer in the step f in FIG. 3, instead of implanting B, low-temperature growth of a Si thin film doped with B at a high concentration or short-time diffusion of a high concentration B can be used. Needless to say.

Finally, electrodes 8, 9, and 10 are formed in the drain region 2, the source region 3, and the gate region 4, respectively, as shown in step h of FIG. The source electrode 9 and the gate electrode
10 can be formed by forming the SiO ₂ film 7 again on the surface of the semiconductor substrate, opening windows at respective electrode formation portions, and depositing Al (aluminum).

The n of the drain region 2 and the source region 3 described above
^{The +} region may be formed of GaAs or SiC, which is a semiconductor having a wider band gap than Si, or Ge or GeSi, which is a semiconductor having a narrower band gap than Si, instead of mixing impurities described above with Si. The p ⁺ region of the region 4 can be formed of SiC having a wider band gap than Si.

[0024] n as the semiconductor substrate 1 in the above examples ^- but using a mold, p is an opposite conductivity type ^- can also be used for the semiconductor substrate, p-type in this case above example n It goes without saying that the n-type can be formed similarly to the p-type instead of the p-type. Of course, a different fabrication process can be used.

In the above description, the case where the number of channel regions is one has been described as an example. However, an element structure in which gate regions are arranged in a grid or combs and a plurality of channel regions are constructed is adopted. You can also. Further, in the above-described embodiment, the example of the groove type SIT has been described. However, it goes without saying that the present invention can be similarly applied to a surface gate type or a gate buried type SIT other than the groove type. Of course, it is also possible to integrate with a plurality of other elements on the same substrate.

Next, the operation of the shield gate type SIT according to the present invention will be described with reference to FIGS. In the drawing, 1 to 10 represent the same portions as those in FIG. 1, and K represents a spreading portion of the depletion layer. FIG. 5 shows a state when the bias voltage of the gate electrode 10 is set to 0 V, and FIG. 6 shows a state when a small reverse bias voltage is applied to the gate electrode 10. The formation of the depletion layer K is thus formed in an ideal state by the change in the minute bias voltage. In order to operate the shielded gate type SIT of the present invention ideally, the depletion layer is formed in the ON state of the device. Thin n of shielding gate
It is necessary to satisfy the two conditions that the depletion layer rapidly spreads to the high-resistance n ⁻ region due to a small gate reverse bias existing only in the layer. These two conditions are such that if the channel region 6 is formed with a low impurity concentration, the width L _HY of the shielding region 5 and the shielding region 5 are set so that L _HY in FIG. 1 becomes equal to the depletion layer width W _DEP due to the diffusion potential. Can be achieved by determining the impurity concentration N _HY . This L _HY
And N _HY are determined, and the other is approximately determined by the following equation (1).

L _HY = W _DEP = [2 ^e s / q · N _HY · V _bi ] (1) where e _s is the dielectric constant of the semiconductor substrate 1, q is the unit charge,
V _bi represents the diffusion potential of the gate region 4 and the shield region 5.

FIG. 7 shows the relationship between L _HY and N _HY . In the figure, the solid line indicates the state of L _HY = W _DEP , and the area A above this line is L _HY > W _DEP and satisfies the above two conditions, but the area B below is L _HY <W _DEP . It becomes W _DEP and does not satisfy the above conditions. In the figure, L _HY = 0.54 μm and the impurity concentrations are 6 × 10 ¹⁴ , 1 × 10 ¹⁵ , 2 × 10 ¹⁵ ,
Points 4 × 10 ¹⁵ and 6 × 10 ¹⁵ cm ⁻³ are respectively denoted by a, b, c,
This is indicated by d and e. FIG. 8 shows the electron concentration distribution between gates when L _HY = 0.54 μm and N _{HY is changed} to the aforementioned concentrations of a, b, c, d, and e. That is, in the figure, the horizontal axis shows the distance between the gate regions with the center at 0, and the vertical axis shows the electron concentration. It can be seen from the figure that the depletion layer penetrates into the n ⁻ region when the impurity concentrations corresponding to a and b are 6 × 10 ¹⁴ and 1 × 10 ¹⁵ cm ⁻³ . Further, the impurity concentrations corresponding to d and e are 4 × 10 ¹⁵ and 6 × 10 ¹⁵ cm.
^In the case of ⁻³ , the depletion layer exists only in the thin region of 0.54 μm, and it can be seen that the n ⁻ region is not depleted at all. Therefore, it can be seen that the area A derived by the equation (1) satisfies the condition.

On the other hand, considering that the conditions must be satisfied at the same time, it can be seen that the optimum L _HY and N _HY exist in the region A near the solid line in FIG. Hereinafter, the present invention will be described in more detail with reference to specific examples.

Example 1 1 kΩ-cm (4 × 10 ¹¹ cm ⁻³ ) of n ⁻ was used as the semiconductor substrate 1.
1 × 10 ¹⁹ cm by solute supply method on silicon high purity substrate
An n ⁺ layer doped with about ^-3 P was grown to a thickness of 300 μm. Then, a high-purity Si crystal substrate was polished to a thickness of 10 μm, and P was selectively diffused at a high concentration of 1 μm to form an n ⁺ layer source region 3. Next, a groove of 2.5 μm is dug, and P and B are implanted so that the shielding region 5 has a concentration of 4 × 10 ¹⁵ cm ^{-3 and} the gate region 4 has a concentration of 1 × 10 ¹⁹ cm ^-3. Formed. At this time, the width L _{HY of the} shielding area 5 is 0.54 μm,
Further, the distance between the shielding regions 5, that is, the effective gate gap 2D
Was 3.6 μm. In addition, FIG.
_LSD was 10 μm and _LGR was 2.5 μm.

In this device, the center line between the gate regions 4 is set to 0, the outward dimension is plotted on the horizontal axis, the electron density is plotted on the vertical axis, and the bias voltage _VGS is applied to the gate electrode as 0, -1,.
FIG. 9 shows the distribution when -2, -3, and -4 V were changed. It can be seen from the figure that when the bias voltage is 0 V, the depletion layer completely stays in the n region, that is, in the shielding region 5, and when the bias voltage is lower than −2 V, the depletion layer is sufficiently spread to the n ⁻ region.

The shield gate type SIT according to the first embodiment
The current characteristics were examined by using Figure 10 shows the drain output characteristics.
The horizontal axis represents the drain voltage (V), and the vertical axis represents the drain current density (A
/ Cm ² ), and the bias voltage V _GS applied between the source electrode and the gate electrode is shown as a parameter. It can be seen from the figure that the unsaturated current is realized by the exponential function increase in the low current region. Therefore, shield gate type SIT
It can be seen that operates by electrostatic induction by the drain voltage.

Further, the electron concentration distribution of this device is shown in FIGS. 11 and 12, with the electron concentration on the vertical axis with respect to the plane of the channel region 6 in the X and Y directions in FIG. Here, FIG. 11 shows that the voltage V _DS between the drain electrode and the source electrode is 1
V and the gate bias voltage V _GS are set to 0 V, FIG.
Shows the electron concentration distribution when V _GS = -3V. As can be seen from these figures, when V _GS = 0 V, the depletion layer is formed in the channel region 6.
It can be seen that the depletion layer extends over the entire channel region 6 when V _GS = −3 V, although no influence is exerted on the channel region 6.

From the above results, it can be seen that this element satisfies both of the above conditions.

Example 2 Under the same conditions as in Example 1 for the semiconductor substrate and external dimensions, L _HY of the shielding area 5 was 1 μm and N _HY was 1.5 × 10 ¹⁵ cm ^−3.
Device was made. This condition corresponds to point C in FIG. FIG. 13 shows the distribution of the electron concentration with respect to the position between the gate regions in this device as in FIG. As is apparent from this figure, also in the device according to this embodiment, when V _GS = 0 V, the depletion layer completely exists in the n-layer shield region 5, and when V _GS = −2 V, the depletion layer is in the n ⁻ layer region. You can see that it is spreading.

With this device, the electric field strength in the source / drain direction (Y direction) along the center line of the channel region 6 when V _DS = 1 V and V _GS = −3 V was measured, and the distribution was shown in FIG.
It was shown to. In the figure, the horizontal axis represents the distance in the drain direction (Y direction) with reference to the source region 3, and the vertical axis represents the intensity of the electric field in V / cm. In addition to the field strength of the device of Example 1 of the aforementioned device according to the second embodiment in FIG. Also shows, further semiconductor substrate concentration SIT field strength of a conventional junction gate structure for comparison N _CH is 3 × 10 ¹⁴ , 2 × 10 ¹⁴ , 8 × 10 ¹³ cm ^-3
3 types. The electric field distribution of the conventional junction gate structure SIT is very high in the vicinity of the genuine gate portion corresponding to the place where the electric field is 0, and tends to decrease rapidly as approaching the drain junction. In particular, N _CH is 2 × 10 ¹⁴ and 3
In the case of × 10 ¹⁴ cm ⁻³ , a neutral region exists near the drain junction. On the other hand, it can be seen that the electric fields of the devices of Examples 1 and 2 having the shielded gate structure of the present invention are uniform over almost the entire region between the gate and the drain.

Embodiment 3 All the conditions other than the distance 2 G between the gate regions 4 such as device dimensions, semiconductor materials, and impurity concentrations were the same as those in Embodiment 1, and the values of 2G were 4.5, 6.5, 8.5, 10.5 and 12.5 μm.
With the five kinds of elements and the same five kinds of 2G values, elements under the same conditions as in Example 2 were produced. FIG. 15 shows the current density (A / cm ² ) of the drain current when the drain voltage V _DS = 1 V and the bias voltage V _GS = 0 V, and FIG. 16 shows the blocking gain indicating the degree of current blocking. The 2G interval is shown on the horizontal axis. In these figures, the data of the current density and the blocking gain are shown at the same time when the device having the conventional junction gate structure is manufactured under the same conditions. As a result, it is understood that the devices of Examples 1 and 2 have greatly improved on-current density and that the gate interval can be arbitrarily selected without depending on the gate interval. In the case of a device having a conventional junction gate structure, the current density sharply decreases due to the decrease in the gate interval, and at the same time, the blocking gain increases. This is because the conduction channel between the gates is pinched off by the depletion layer at zero bias as the gate interval is reduced, and a potential barrier is formed in the region. By introducing the shield gate structure of the present invention, the conflicting relationship between the ON current density and the blocking gain with respect to the change in the gate interval can be eliminated.

Embodiment 4 All conditions such as device dimensions, semiconductor material, and impurity concentration other than the impurity concentration N _HY of the shielding region 5 are set to the same conditions as those of the first embodiment (L _HY = 0.
54 .mu.m) and 2 (in the L _HY = 1 [mu] m) and the same, N _HY
Were fabricated with different concentrations of V _DS = 1 V and V _DS
It was operated at _GS = 0 V, the concentration was plotted on the horizontal axis, and the drain current density (A / cm ² ) was plotted on the vertical axis in FIG. In the same figure, the data of the device having the conventional pn junction gate structure are also measured and compared. Here, L _GR , L _SD , L _G , and 2G are set equal in the embodiment of the present invention and the example of the conventional structure. From this figure, for two embodiments of L _HY = 0.54 and 1 μm according to the present invention, the change in current density with increasing N _HY is shown by a solid line, and in the case of a conventional junction gate structure element, the change in N _CH is shown by a broken line. Shown. In the case of the present invention, the current density is N _HY where the equation (1) holds, and the current density is saturated. This is because the width of the depletion layer in the horizontal direction was sufficiently reduced by the expression (1). On the other hand if the conventional junction gate structure element, the current density is increased with increasing N _CH. This is because the width of the depletion layer of the gate is reduced due to this increase, and as a result, the degree of channel pinch-off is reduced.

[0039]

As described above, in the SIT having the shielded gate structure according to the present invention, the width of the depletion layer at zero bias is extremely small because it is limited to the thin n-layer serving as the shield region. Therefore, the drain current at zero bias is sufficiently obtained, and the ON current is kept constant even in a region where the gate interval is considerably small. In addition, in the current blocking state in which a reverse bias is applied to the gate, the depletion layer spreads sufficiently between the gates, and sufficient current control can be performed irrespective of the interval between the gate regions. SIT can be obtained.

As a result, according to the present invention, a triode by an ideal electrostatic induction operation can be achieved, which greatly contributes to the development of electronic equipment.

[Brief description of the drawings]

FIG. 1 is an explanatory sectional view of a shielded gate type SIT according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a first half of a manufacturing process of a shielded gate type SIT according to an embodiment of the present invention.

FIG. 3 is an explanatory view showing the latter half of the manufacturing process of the shielded gate SIT according to one embodiment of the present invention.

FIG. 4 is a diagram showing an electron concentration distribution in a super-step junction diode.

FIG. 5 is an explanatory sectional view showing an operation principle when a bias voltage V _GS = 0 V of a shielded gate type SIT according to an embodiment of the present invention.

FIG. 6 shows a V of a shield gate type SIT according to an embodiment of the present invention.
FIG. 9 is an explanatory diagram showing an operation principle when _GS is reverse biased.

FIG. 7 is an explanatory diagram showing a relationship between a depletion layer width W _DEP and a width L _HY of a shielding region.

FIG. 8 is a diagram showing an electron concentration distribution with respect to a position between gate regions, using an impurity concentration N _HY of a shielding region as a parameter.

FIG. 9 is a diagram showing an electron concentration distribution between gate regions with respect to a gate voltage in Example 1.

FIG. 10 is a diagram showing drain output characteristics of one example of the present invention.

FIG. 11 is a diagram showing an electron concentration distribution with respect to a channel region plane when V _GS = 0 V according to one embodiment of the present invention.

FIG. 12 is a diagram illustrating an electron concentration distribution with respect to a channel region plane when V _GS = −3 V according to one embodiment of the present invention.

FIG. 13 is a diagram showing an electron concentration distribution between gate regions with respect to a gate voltage in Example 2.

FIG. 14 is a diagram showing an electric field intensity distribution between a source region and a drain region.

FIG. 15 is a diagram showing a drain current density with respect to a distance between gate regions.

FIG. 16 is a diagram showing a blocking gain with respect to a distance between gate regions.

FIG. 17 is a diagram showing a drain current density with respect to an impurity concentration in a shielding region.

FIG. 18 is an explanatory sectional view showing the structure of a conventional SIT.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 drain region 3 source region 4 gate region 5 shielding region 6 channel region

────────────────────────────────────────────────── ─── Continuing the front page (72) Koji Yano, Inventor 631, Iita 63, Husa-cho, Husa-gun, Shizuoka Prefecture (72) Yasuo Kimura 2-1-1 Fukuoka, Fukuoka, Kamifukuoka-shi, Saitama (56) References JP-A-54-9586 (JP, A) JP-A-59-90963 (JP, A) JP-A-56-115572 (JP, A) JP-A-55-99772 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/80 H01L 29/812 H01L 21/338

Claims (2)

(57) [Claims] 1. A semiconductor substrate formed of one conductivity type having a low impurity concentration, a drain region formed of the one conductivity type having a high impurity concentration in the semiconductor substrate, and the semiconductor substrate facing the drain region. A source region formed of the one conductivity type having a high impurity concentration and forming a channel region between the drain region and the drain region; and a source region formed of another conductivity type having a high impurity concentration around the channel region of the semiconductor substrate. A static induction transistor comprising a gate region for adjusting a depletion layer of the channel region, wherein the transistor is formed at least on the channel region side of the gate region with the one conductivity type having an impurity concentration higher than an impurity concentration of the semiconductor substrate. It has a shielding area that is, the width of the shielding region is depleted due to diffusion potential
The width of the shielding area and the shielding area so as to be equal to the layer width
The following equation L _HY = W _DEP = [2 e _s / qN _HY V _bi ] (where L _HY is the width of the shielding region and W _DEP is the diffusion potential
Depletion layer width, N _HY impurity concentration of the shielding region, e _s is the semiconductor
The dielectric constant of the substrate, q is the unit charge, V _bi is the gate region and
It represents the diffusion potential of the shielding area. A) a shielded gate static induction transistor characterized in that: 2. The method according to claim 1, wherein the semiconductor substrate has an impurity concentration of 1 × 10
^2. The shielded gate static induction transistor according to claim 1, which has a size of ¹³ cm ^-3 or less.