JP3076952B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word on an interlayer insulating film.
Even if there is a large step caused by the wire,
The material film that will become the electrode of the memory capacitor
Semiconductor memory device that does not hinder
It relates to the manufacturing method. At present, semiconductor memory devices, especially dynamic
・ Random access memory (dynamic ra)
ndom access memory (DRAM)
Has been done to highly integrate fine memory cells
Memory key due to the step caused by the word line.
Various obstacles occur, such as difficulties in forming
We have to eliminate it. [0003] 2. Description of the Related Art FIG. 9 shows a general DRA which has been put into practical use.
It is a principal part cut side view for demonstrating the structure of M. In the figure, 1 is a p-type silicon semiconductor substrate
2 is a field insulating film made of silicon dioxide, 3
Is a gate insulating film made of silicon dioxide, 4₁, 4_Two,
4_ThreeIs a polycrystalline silicon gate electrode (word
Line), 5_1AIs n⁺Mold source area, 6 _1A, 6_1BIs n⁺Type
A rain region, 7 an interlayer insulating film made of silicon dioxide,
8_1A, 8_1BIs a stacked capacitor made of polycrystalline silicon.
The storage electrode, one of the electrodes in the pasta, 9_1A, 9_1B
Is a silicon dioxide stacked capacitor
Dielectric film, 10₁Is a cell made of polycrystalline silicon
The other in a stacked capacitor, called a plate
The counter electrode 11 is made of silicon dioxide
Interlayer insulating film, 12₁Is a refractory metal silicide (for example,
Bit line composed of polycide (polycide), 1
3 is phospho-silicate glass (phospho-silicate)
  glass: PSG), 14 is common
A part of the word line together with the gate electrode is called
Electrodes and wirings are shown. In this DRAM, for example, the gate electrode 4
₁And source area 5_1AAnd drain region 6_1AAnd one note
Transfer gate transistor in re-cell
And electrode 8_1AAnd dielectric film 9_1AAnd electrode 10₁And said above
The electrode forms the memory capacitor in the memory cell
8_1AIs the drain region 6_1ABy contacting
Sfa gate transistors and memory capacitors
Are coupled and the transfer gate transistor is turned off.
When the memory capacitor is turned off, information charges are taken in and out of the memory capacitor or
Or accumulation. The configuration and operation of the above-described DRAM are
Memory cell consisting of transistor and one memory capacitor
In a standard DRAM consisting of
It is currently used frequently as a semiconductor storage device.
Is what it is. The drain region 6_1B, Electrode 8_1B,
Dielectric film 9_1BEtc. are adjacent to the memory cell described above
A part of the memory cell to be used. [0007] Recently, semiconductor memory devices have been developed.
Tends to be further miniaturized, and where required
Anisotropic etching is often used to form patterns from
As a result, the edge of the pattern
And as it evolves, the underlying patterns
The effect of the step in the pattern is amplified and the formation of the upper layer pattern
It's getting harder. [0008] Therefore, spin-on-glass (spin
  Do not apply or etch back on glass
Although some measures such as eliminating steps are adopted,
Process is unstable or unstable for etch back control, etc.
There are many difficulties such as the fact that there is a source. The above is described with reference to FIG.
DRAM is not an exception, and miniaturization is progressing
As the size of memory cells in planar view decreases,
Is required, and trying to meet that demand increases the level difference.
This makes it extremely difficult to form a pattern. For example, when the planar area of a memory cell is 1
00 [μm^Two], It will no longer be
It is impossible to secure memory capacitor capacity
In order to avoid this, the memory capacitor
Thick storage electrode to increase the area on the side
The overall area as a memory capacitor
It is considered not to drop. However, such a thick storage electrode must be
For turning, the step of the base, that is, the unevenness is large.
Affect. FIG. 10 secures the capacity of the memory capacitor.
To explain a highly integrated DRAM with countermeasures
FIG. 9 is a side view of a part cut, and the same symbols as those used in FIG.
Represents the same part or has the same meaning. This DRAM is the same as the DRAM shown in FIG.
The difference is that the planar area of the memory cell is reduced.
Of course, the planar surface of the memory capacitor
The product is also smaller, so to compensate for the lack of capacity
Pole 8_1AAnd 8_1BAbout twice the normal thickness, ie, for example,
0.5 [μm] thick, and increase the area of the side
By doing so, the area acting as a capacitor as a whole
Is not reduced. However, the electrode 8_1AAnd 8_1Bof
When the thickness S is formed to be thick, the portion indicated by the arrow in the figure
Minute, that is, the electrode 8_1AAnd electrode 8_1BBetween the vertical
Gate electrode 4 which is a word line having a sharp edge
_TwoAnd 4_ThreeFormed a deep dip due to the presence of
Combined with the photolithography power
Pole 8_1A, 8_1BEtc. cannot be performed favorably. The present invention is applied to a gate electrode which is a word line.
When there is a step due to
By forming a sidewall film on a gate electrode forming a step, the step
Mitigates the adverse effect of the difference, and becomes a storage electrode formed on it.
Normal photolithography technology for thick conductor film to be
To allow patterning. [0016] According to the present invention, a word line and a word line are provided.
Process to form a gate electrode that extends
Standard conventional techniques may be applied, but gate
The edge side surface of the electrode becomes a step, so to reduce it
Side wall film is formed, and the side wall film is formed
In any case, a photo lithog
For patterning and film breakage due to ruffy technology
Develop limit conditions that can prevent adverse effects from appearing.
Show. FIG. 1 shows a DRA for explaining the principle of the present invention.
FIG. 11 is a cutaway side view of a main part showing M, which is shown in FIGS.
The same symbols as used above represent the same parts or have the same meaning
Have In the figure, a word line is formed on a field insulating film 2.
The gate electrode 4_TwoAnd 4_ThreeExtends on its edge side
The surface is the base side for giving a gentle slope to the step
A wall film 2A is formed, and an interlayer insulating film 7 is formed over the wall film 2A.
Polycrystalline silicon film to be used as a storage electrode
8 is shown. The present inventors have conducted a number of experiments and found that
Normal photolithography even when the silicon film 8 is thick
In order to be able to perform patterning with
Forming a sidewall film 2A as a basis for providing a gradual inclination
Requires certain conditions, and ignores them
It has been found that a good result cannot be obtained even if it is formed. According to the experiment, the gate electrode 4_Two, 4_Three
And d is the thickness of the base material in the side wall film 2A.
If the thickness of the contacting bottom surface is a, then a> d
Mandatory, and after doing so, required for today's DRAM
Standard thickness, for example, 100
0 [Å] interlayer insulating film, and a very thick multi-layer
Even if the crystalline silicon film 8 is formed,
Reliable fine patterning by lithography technology
can do. The thickness d is, for example, 0.4 [μm] or less.
The angle θ formed at the point where the lower end of the side wall film 2A contacts the base.
Is set to 60 ° or less, the thickness of the polycrystalline silicon film 8 is reduced.
Even if the thickness is 0.5 μm or more, for example,
And such conditions can be any
In this case, a> d can be satisfied. As described above, the half according to the present invention is used.
In the conductor storage device and the method of manufacturing the same, (1) On a substrate (for example, a p-type silicon semiconductor substrate 1).
A plurality of turned word lines (eg, polycrystalline silicon
Gate electrode 4 made of₁Etc.) and the edge of the word line.
Insulation material (eg, silicon dioxide) formed on the side of the device
A side wall film (for example, side wall film 2A) made of
And an interlayer insulating film (for example, silicon dioxide) covering the side wall film.
An interlayer insulating film 7) made of
Extends across the edge of the word line
One side of the patterned memory cell capacitor
Pole (eg, storage electrode 8)_1AThe word line
Is d and the side wall film is
Assuming the thickness of a> d Satisfy the following conditions, andThe memory cell capacity
The thickness of one of the electrodes is smaller than the thickness of the word line.
Thicker thanBetween the adjacent word lines
Characterized by being separated, or (2)For the surface of the substrate (for example, p-type silicon semiconductor substrate 1)
Membrane having substantially vertical edge sides and creating a step
A plurality of word lines having a thickness d (for example, polycrystalline silicon
Gate electrode 4 ₁ Etc.) on the substrate
And then covering the word line and connecting to the word line.
The insulating film (for example,
Forming a silicon dioxide film).
Anisotropically etching the edge film to the edge side of the word line
The thickness of the bottom surface in contact with the substrate is a, and a> d
Forming a sidewall film (for example, sidewall film 2A) maintaining the above conditions
And a layer covering the word line and the sidewall film.
Interlayer insulating film (for example, an interlayer insulating film made of silicon dioxide
Forming step 7), and then covering the interlayer insulating film.
And a conductor film thicker than the thickness of the word line (for example,
Forming a polycrystalline silicon film 8),
After forming a mask with a required pattern, the conductor film is
Anisotropically etch between the adjacent word lines
Separate one electrode of the memory cell capacitor (eg
For example, storage electrode 8 _1A Etc.)
It is characterized by that. [0025] According to the above-mentioned means, the memory capacity can be improved.
To increase the capacitance by forming a thick storage electrode
The thick polycrystalline silicon film to be the storage electrode
It is possible to pattern precisely and with good reproducibility
There is a word line that causes steps
And the thickness of the sidewall film formed on the side surface of the word line.
Higher integration of semiconductor memory devices only by considering the relationship
It is effective to apply. FIGS. 2 to 8 illustrate one embodiment of the present invention.
Main part representing the semiconductor memory device at the key process point
FIG. 3 is a plan view, and will be described below with reference to these figures. See FIG. 2- (1) For example, a silicon nitride film and a silicon dioxide film
Selective thermal oxidation using an oxidation resistant mask (eg,
local oxidation ofsilicon
Method: LOCOS method)
Feel made of silicon dioxide film on semiconductor substrate 1
A gate insulating film 2 is formed. 2- (2) Removing the oxidation-resistant mask to form a p-type silicon semiconductor substrate;
After exposing a part of 1, ie, the active region, the thermal oxidation method
Depending on the application, the thickness is about 200 [例 え ば], for example.
A certain gate insulating film 3 is formed. 2- (3) Chemical vapor deposition
position (CVD) method.
Polycrystalline silicon film having a thickness of, for example, about 2000 [Å]
Grow. 2- (4) Resist photolithography in normal photolithography technology
Process and etching gas to CCl_Four/ O_TwoTo be
Reactive ion etching (reactive ion etching)
  By applying the etching (RIE) method,
By patterning the polycrystalline silicon film, the gate
Electrode 4₁, 4_Two, 4_ThreeAnd other electrodes and wiring
You. 2- (5) By applying the ion implantation method, the gate electrode 4₁
Implantation of As ions using the mask as a mask
N depending on the alignment method⁺Mold source area (shown
Z) and n⁺Drain region 6_1ATo form In addition, this
The gate electrode 4₁Impurities introduced into various electrodes and wiring
Needless to say, it is made conductive. Referring to FIG. 3- (1) By applying the CVD method, the thickness is, for example, 3000
[Å] A silicon dioxide film having a thickness of about [Å] is formed. 3- (2) Etching gas is CF_Four+ O_Two+ H_TwoRIE method
The anisotropy of the silicon dioxide film
Perform etching to remove all silicon dioxide film on the plane.
Continue until removed. By performing this processing, the gate electrode 4
₁Side wall film with a gentle slope on the side only
2A remains. The side wall film 2A seen here is the same
Needless to say, the condition, a> d, is satisfied. Cause
Incidentally, the side wall film 2A after the anisotropic etching has been performed.
The thickness a at the bottom is 2400 [Å], and the gate
Pole 4₁Is 2000 [Å] as described above.
is there. Referring to FIG. 4- (1) By applying the CVD method, the thickness is, for example, 1000
[Å] interlayer insulating film 7 of silicon dioxide
To form Referring to FIG. 5- (1) The application of ordinary photolithography technology
Then, the interlayer insulating film 7 and the gate insulating film 3 are etched.
Is the contact window for the storage electrode of the memory capacitor
An opening 7A is formed and a drain region 6 is formed._1AExpress part of
Let it. Referring to FIG. 6- (1) The thickness is, for example, 0.5
A polycrystalline silicon film 8 having a thickness of about [μm] is formed. 6- (2) By applying the ion implantation method, for example, As ion
Is implanted to make the polycrystalline silicon film 8 conductive. Referring to FIG. 7- (1) Resist photolithography in normal photolithography technology
Process and etching gas to CCl_Four/ O_TwoTo be
By applying the RIE method, the polycrystalline silicon film 8
Patterning is performed on the memory capacitor
Storage electrode 8 which is the electrode of_1A, 8_1BAnd so on. This storage electrode 8_1APlane area and sides
Are almost equal, and the area of the plane of the memory cell is 10
[Μm^Two], The total area is 7 μm^Two]
Or more. The pattern of the polycrystalline silicon film 8
In the present invention, for example, when the gate electrode 4_TwoWhen
4_ThreeAnd the side wall film 2A exists between
As described above, since a> d is satisfied, the gap is formed on the side wall.
A> d
It is significantly narrower than when it is not below. Therefore, the layer reflecting the effect of the narrow gap
Since the gap that appears in the inter-insulating film 7 is also narrow,
The amount of a part of the polycrystalline silicon film 8 penetrating there
Very little compared to the case where the wall film 2A does not exist.
Then, when patterning the polycrystalline silicon film 8,
Since the amount of over-etching is small, etching
The result is good. Further, the presence or absence of the side wall film 2A
However, if the condition a> d is not satisfied,
Plate electrode 4_TwoInterlayer insulation covering edges and side surfaces
Since the film 7 falls very steeply,
Mask for patterning polycrystalline silicon film 8 is shifted
For example, the storage electrode 8_1AEdge near the arrow indicated in the figure
If it is located beside, the storage electrode 8_1AEdges and interlayers
A polycrystalline silicon film is interposed between the edge film 7 and a rising portion.
8 or a polycrystalline silicon
A sharp projection is formed on the edge of the ion
Dielectrics that occur or form on field concentration
This will cause problems with coverage such as membranes. In the present invention, the existence of the side wall film 2A where a> d is satisfied.
At present, it is completely free from the problems described above. Referring to FIG. 8 (and FIG. 9). 8- (1) By applying the thermal oxidation method in a humid atmosphere,
Storage electrode 8_1AFor example, the thickness is about 100 [Å] on the surface such as
Storage capacitor made of silicon dioxide
Dielectric film 9_1A, 9_1BAnd so on. 8- (2) After this, the polycrystalline silicon
A memory carrier called a cell plate
The counter electrode which is the other electrode in the pasta (for example, FIG.
Counter electrode 10₁), Interlayer insulation made of silicon dioxide
The film (for example, the interlayer insulating film 11 in FIG. 9) is made of polycide.
Bit line (for example, bit line 12 in FIG. 9)₁), PSG
An interlayer insulating film (for example, interlayer insulating film 13 in FIG. 9)
electrode / wiring forming part of the word line consisting of
For example, the electrodes and wirings 14) shown in FIG. 9 are formed. In the embodiment described above, the side wall film 2
A is set so that a> d, so that the storage electrode 8_1AWhat
Is precisely patterned and adversely affects subsequent processes
Is not given. [0049] The semiconductor memory device according to the present invention and its manufacture
In the fabrication method, multiple word lines are formed on a substrate,
A sidewall film made of an insulating material is formed on the side surface of the edge of the lead wire.
Word line and sidewall filmButCovered with interlayer insulation film, interlayer insulation
Extends over the edge of the word line over the film
One side of the patterned memory cell capacitor
Poles are formed, the thickness of the word line is d, and the side wall film is
A> d, where a is the thickness at the bottom surface in contact with the ground
Condition is satisfied and one of the memory cell capacitors
ElectrodeThe thickness of the word line is larger than the thickness of the word line.
KukatsuSeparated between the adjacent word lines.
You. By adopting the above configuration, the memory capacity
Increase the capacity by forming thick storage electrodes in the paster
Thick polycrystalline silicon to be the storage electrode
Possible to pattern the film precisely and with good reproducibility
Therefore, it is effective for high integration of the semiconductor memory device.
In addition, in order to realize the structure,
Thickness of the film and the thickness of the side wall film formed on the side surface of the film
It is only necessary to consider the relationship with
DifficultiesAnd a polycrystalline silicon to serve as a storage electrode.
When patterning the recon film, the adjacent gate electrode
Two sidewall films satisfying the condition a> d exist between them
Is located on the interlayer insulating film that has entered between them
Over-etching amount of polycrystalline silicon film is small
The patterning of the polycrystalline silicon film.
Even if the disk is misaligned,
The formation of sharp protrusions at the edges of the membrane
Cause electric field concentration at the edge, or
May cause problems with the coverage of the dielectric film, etc.
Not even.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a fragmentary side view showing a DRAM for explaining the principle of the present invention. FIG. 2 is a cutaway side view showing a main part of the semiconductor memory device at a key point in a process for explaining one embodiment of the present invention; FIG. 3 is a cutaway side view showing a main part of the semiconductor memory device at a key point in a process for explaining one embodiment of the present invention; FIG. 4 is a cutaway side view showing a main part of the semiconductor memory device at a key point in the process for explaining one embodiment of the present invention; FIG. 5 is a fragmentary side view showing a semiconductor memory device at a key point in a process for explaining an embodiment of the present invention; FIG. 6 is a cutaway side view of a main part of the semiconductor memory device at a key point in the process for explaining one embodiment of the present invention; FIG. 7 is a fragmentary side view showing a semiconductor memory device at a key point in a process for explaining one embodiment of the present invention; FIG. 8 is a cutaway side view showing a main part of the semiconductor memory device at a key point in a process for explaining one embodiment of the present invention; FIG. 9 is a fragmentary side view for explaining the structure of a general DRAM that is put into practical use. FIG. 10 is a fragmentary side view for explaining a highly integrated DRAM in which measures are taken to secure the capacity of a memory capacitor. [Description of Signs] 1 Semiconductor substrate 2 Field insulating film 2A Side wall film 3 Gate insulating film 4 ₁ Gate electrode (word line) 4 ₂ Gate electrode (word line) 4 ₃ Gate electrode (word line) 5 _1A n ⁺ type source region 6 _1A n ⁺ type drain region 6 _1B n ⁺ type drain region 7 Interlayer insulating film 7A Opening 8 Polycrystalline silicon film 8 _1A storage electrode 8 _1B storage electrode 9 _1A dielectric film 9 _1B dielectric film 10 ₁ Counter electrode 11 Interlayer insulation Film 12 ₁ Bit line 13 Interlayer insulating film 14 Electrode / wiring a Thickness of bottom surface where sidewall film is in contact with base d Thickness of gate electrode S Thickness of storage electrode θ Angle between bottom edge of sidewall film and base

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-33445 (JP, A) JP-A-62-190869 (JP, A) JP-A-60-124951 (JP, A) JP-A 62-334 252974 (JP, A) JP-A 61-53938 (JP, U) JP-B 60-2784 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21 / 822 H01L 21/8242 H01L 27/04

Claims (1)

(57) [Claims] A plurality of word lines patterned on a substrate; a side wall film made of an insulating material formed on an edge side surface of the word line; an interlayer insulating film covering the word line and the side wall film; One electrode of a patterned memory cell capacitor formed on the film and extending across the edge of the word line, wherein the thickness of the word line is d and the sidewall film is Assuming that the thickness at the bottom surface in contact with the base is a, the condition a> d is satisfied, and the thickness at one electrode of the memory cell capacitor is
The semiconductor memory device is characterized by being thicker than the word line and being separated between the adjacent word lines. 2. With edge sides substantially perpendicular to the substrate surface
And a plurality of word lines having a film thickness d for generating a step.
Forming on the substrate, and then covering the word lines and
Forming an insulating film having a thickness greater than the thickness d
And then anisotropically etching the insulating film to form the word
The thickness of the bottom surface in contact with the base on the side of the edge of the line is a
Forming a sidewall film while maintaining the condition of a> d, and then interlayer insulating covering the word line and the sidewall film.
Forming a film, and then covering the interlayer insulating film and forming a thickness of the word line.
Forming a conductor film thicker than the above, and then forming a mask having a required pattern,
The conductor film is anisotropically etched to form the adjacent wires.
One side of the memory cell capacitor
Forming an electrode of the present invention.
Manufacturing method of a semiconductor memory device.