JP3077168B2 - Bi-MOS semiconductor device and method of manufacturing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Bi-MOS semiconductor device and a method of manufacturing the same, and more particularly, to a bipolar transistor formed in a bipolar transistor region on a semiconductor substrate, M formed in the upper MOS transistor area
The present invention relates to a Bi-MOS semiconductor device including an OS transistor and a method for manufacturing the same.

[Conventional technology]

Generally, in a logic circuit, as a semiconductor device for obtaining low power consumption and high operation speed, in this case, N
CMOS (Comp.) Which is a complementary circuit including an insulated gate field effect transistor (hereinafter referred to as an NMOS transistor and a PMOS transistor, respectively) of a channel and a P channel.
In addition to complementary transistors, a Bi-CMOS semiconductor device in which NPN bipolar transistors are mixedly arranged on the same semiconductor substrate in addition to a transistor is well known in the related art. Circuits, such as ECL (Emitter Coupled Logic) logic circuits
Bi-CM with CMOS logic circuit on the same semiconductor substrate
OS semiconductor devices are also well known in the art.

FIG. 3 is a cross-sectional view schematically illustrating a part of a schematic configuration of a semiconductor integrated circuit device including such a conventional Bi-CMOS semiconductor device.

Here, the semiconductor integrated circuit device shown in FIG. 3 has a NPN type bipolar transistor 100 and a CMOS transistor including a PMOS transistor 200 and an NMOS transistor 300 formed on the same semiconductor substrate, respectively. Next, the configuration of the semiconductor integrated circuit device and the manufacturing method thereof will be described in detail with reference to FIGS. 4 (a) to 4 (d).

First, a bipolar transistor formation region A for forming an NPN type bipolar transistor 100 on a P type semiconductor substrate 1, and a PMOS transistor 200 and an NMOS transistor 300
Are formed in the CMOS transistor formation region B where
After selectively ion-implanting the type impurities, heat treatment is performed to form N ⁺ -type buried layers 2a and 2b and to surround the N ⁺ -type buried layer 2a corresponding to the bipolar transistor formation region A, thereby forming a P-type buried layer. After the impurity is selectively ion-implanted, heat treatment is performed to form a P-type buried layer 3 as an isolation region of the bipolar transistor formation region A (FIG. 4A). Then, an N-type epitaxial growth layer 4 is formed so as to cover each of the N ⁺ -type buried layers 2a and 2b and the P-type buried layer 3 (FIG. 2B).

Next, the CMOS on the N-type epitaxial growth layer 4
NMOS transistor formation region in transistor formation region B
The P-type well region 5 and the P-type diffusion region 6 are formed by selectively ion-implanting a P-type impurity into a Ba portion and a portion serving as an isolation region of the bipolar transistor formation region A and then performing a heat treatment. The portion of the PMOS transistor forming region Bb and the portion of the bipolar transistor forming region A in the CMOS transistor forming region B on the N-type epitaxial growth layer 4 thus remaining become the N-type well regions 7a and 7b. Here, the respective N-type well regions 7a,
As in the case of the P-type well region 5, 7b may be formed by selectively ion-implanting N-type impurities and then performing a heat treatment. The P-type well region 5 in the NMOS transistor formation region Ba is an N-type well region.
7b and the N ⁺ -type buried layer 2b are separated from the P-type semiconductor substrate 1, and the N-type well region 7a of the bipolar transistor formation region A is a P-type buried layer 3b.
And the P-type diffusion region 6 is separated from the N-type well region 7b of the PMOS transistor formation region Bb (FIG. 3C). Further, isolation oxide films 8 are selectively formed at predetermined positions (FIG. 4D).

Thereafter, as shown in FIG. 3, the N-type well region 7a in the bipolar transistor formation region A and the N-type well region 7b in the PMOS transistor formation region Bb are respectively formed by known means. An N ⁺ -type diffusion layer 9 serving as a collector electrode region is formed, and a bipolar transistor forming region A has a P region forming a base region.
Diffusion layer 10 and N-type diffusion layer 1 constituting the emitter region
1 are selectively formed to form an NPN-type bipolar transistor 100, and an NMOS transistor formation region Ba is formed.
In contrast, an NMOS transistor 300 is formed by providing a gate electrode 12 on a P-type well region 5 via a gate oxide film, and forming N-type source / drain regions 13 on both sides thereof. For the formation region Bb,
Gate electrode on N-type well region 7b via gate oxide film
14 and P-type source / drain regions 15 on both sides thereof.
Is formed to form the PMOS transistor 200. Thus, the intended Bi-CMOS device is obtained.

[Problems to be solved by the invention]

A conventional Bi-MOS semiconductor device such as a Bi-CMOS semiconductor device is configured as described above. As a result, the N-type source / drain region 13, the P-type well region 5 and the N ⁺ By each of the mold buried layers 2b,
In this case, a parasitic NPN transistor is formed.

By the way, in the method of manufacturing the conventional device described above,
Due to the heat treatment performed after the formation of the N ⁺ -type buried layer 2b, the N ⁺ -type buried layer 2b
Is diffused, and the P-type impurity concentration of the P-type well region 5 near the interface with the N ⁺ -type buried layer 2b is reduced. This is because the base region in the parasitic NPN transistor is reduced. Means that the impurity concentration of the NPN transistor becomes low, and as a result, the breakdown voltage of the parasitic NPN transistor decreases.

In order to prevent this decrease in breakdown voltage, the parasitic NPN
The thickness of the P-type well region 5 serving as the base region of the transistor may be increased (for example, about 4 μm or more), while the thickness of the P-type well region 5 and the collector region of the NPN-type bipolar transistor 100 may be increased. Since the thickness of the N-type well region 7a is equal to that of the P-type well region 5, simply increasing the thickness of the P-type well region 5 also increases the thickness of the N-type well region 7a as the collector region. As a result, the cutoff frequency of the NPN-type bipolar transistor 100 is reduced, and the performance of the device itself cannot be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object of the present invention is to simultaneously maintain a withstand voltage of a parasitic NPN transistor formed in a MOS transistor region while simultaneously maintaining a bipolar transistor region. An object of the present invention is to provide a Bi-MOS semiconductor device of this kind and a method of manufacturing the same, which can improve the performance of an NPN-type bipolar transistor.

[Means for solving the problem]

In order to achieve the above object, a Bi-MOS according to the present invention is provided.
The semiconductor device and the method of manufacturing the same have a relatively thick N ⁺ -type layer containing the same impurity as the subsequent relatively thin N ^-- type buried layer on the semiconductor substrate corresponding to the bipolar transistor formation region. A buried layer is formed, and a relatively thin N ⁻ -type buried layer is formed on the same semiconductor substrate corresponding to a CMOS transistor forming region.

That is, the present invention provides a Bi transistor formed by a bipolar transistor formed in a bipolar transistor formation region on a first conductivity type semiconductor substrate and a MOS transistor formed in a MOS transistor formation region on the semiconductor substrate. -A MOS semiconductor device, wherein the bipolar transistor is provided with a relatively high impurity concentration buried layer of a relatively thick second conductivity type formed on a semiconductor substrate in the bipolar transistor formation region;
Further, the MOS transistor is provided with a buried layer of a second conductive type having a relatively small thickness and a relatively low impurity concentration, which is formed on the semiconductor substrate in the MOS transistor formation region,
The buried layer having a relatively large thickness and a relatively high impurity concentration includes an impurity of the same element as the buried layer having a relatively small thickness and a relatively low impurity concentration. It is a MOS semiconductor device.

Further, the present invention provides a Bi transistor formed by a bipolar transistor formed in a bipolar transistor formation region on a first conductivity type semiconductor substrate and a MOS transistor formed in a MOS transistor formation region on the semiconductor substrate. Forming a buried layer of a relatively high impurity concentration of a relatively thick second conductivity type corresponding to the bipolar transistor formation region on the semiconductor substrate, the method comprising: Forming a buried layer of a second conductivity type having a relatively small thickness and a relatively low impurity concentration corresponding to the MOS transistor formation region on the semiconductor substrate; and forming the semiconductor including the respective buried layers. Forming a relatively thin single-crystal layer of a second conductivity type and a relatively low impurity concentration on the substrate; and forming a second crystal from each of the buried layers into the single-crystal layer. Bi-MOS that the step of diffusing the impurity of a conductivity type, characterized in that it comprises at least
6 shows a method for manufacturing a semiconductor device.

[Action]

Therefore, according to the present invention, a second conductive type relatively thick buried layer having a relatively high impurity concentration is formed in a bipolar transistor forming region on a semiconductor substrate, and a MOS transistor forming region is formed in a MOS transistor forming region on the same semiconductor substrate. By arranging a heat treatment after arranging a relatively thin buried layer of a two-conductivity type and a relatively low impurity concentration, a relatively thick second-conductivity-type thick region is formed in the bipolar transistor formation region. A relatively high impurity concentration buried layer can be formed in the MOS transistor formation region in the MOS transistor formation region because the second conductivity type relatively thin buried layer with a relatively low impurity concentration can be formed in the MOS transistor formation region. The effective base width of the base region of the parasitic NPN transistor generated when a MOS transistor is formed can be increased, and the bipolar region in the bipolar transistor formation region can be increased. As long as the effective collector width of the collector region of the bipolar transistor is reduced, the breakdown voltage of the parasitic NPN transistor can be maintained, and at the same time, the performance deterioration of the bipolar transistor, such as a decrease in cutoff frequency, can be effectively suppressed. You get.

〔Example〕

Hereinafter, an embodiment of a Bi-MOS semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to FIG. 1 and FIG.

FIG. 1 is a sectional view schematically showing a schematic configuration of a Bi-CMOS device to which this embodiment is applied.

In this case, the semiconductor integrated circuit device according to the embodiment shown in FIG. 1 also has an NPN-type bipolar transistor 1
00, a PMOS transistor 200 and an NMOS transistor 300 are formed. The difference from the conventional device is that the semiconductor substrate 1 corresponds to the bipolar transistor formation region A.
A relatively thick N ⁺ -type buried layer 2a is formed thereon, and a relatively thin N ^-- type buried layer 2b is formed on the same semiconductor substrate 1 corresponding to the CMOS transistor formation region B. It was done.

Next, the configuration of the semiconductor integrated circuit device and the manufacturing method thereof will be described in detail with reference to FIGS. 2 (a) to 2 (d).

First, a P-type impurity is selectively ion-implanted so as to surround the bipolar transistor formation region A of the NPN bipolar transistor 100 on the P-type semiconductor substrate 1, and a P-type impurity as an isolation region of the bipolar transistor formation region A is formed. After forming the mold buried layer 3, the bipolar transistor formation region A side and the same P-type semiconductor substrate 1
A resist 20 is formed to open a CMOS transistor formed region B side of a CMOS transistor including a PMOS transistor 200 and an NMOS transistor 300, and an N-type impurity is selectively implanted at a low dose using the resist 20 as a mask. By ion implantation, relatively thin N ^- type buried layers 2c and 2b are formed in the bipolar transistor formation region A and the CMOS transistor formation region B, respectively. (FIG. 2 (a)).

After removing the resist 20 used for the mask,
Next, a resist 30 for opening only the N ⁻ -type buried layer 2c in the bipolar transistor formation region A on the P-type semiconductor substrate 1 is formed, and N-type impurities are implanted at a high dose using the resist 30 as a mask. by selective ion implantation in an amount, the N in the bipolar transistor formation region a ^- to increase the N-type impurity of type buried layer 2c, to form a thick N ⁺ -type buried layer 2a having a relatively thick. Here, the formation of the relatively thick N ⁺ -type buried layer 2a and the relatively thin N ^-- type buried layer 2b, which are respectively formed in this manner, are also For example, a resist having an opening only on the side of the bipolar transistor formation region A is used as a mask, and N-type impurities are selectively ion-implanted at a high dose, so that N ⁺ having a relatively large thickness is formed only in the bipolar transistor formation region A. Mold buried layer 2a is formed, and similarly, a CMOS transistor forming region B
Using a resist having an opening only on the side as a mask, N-type impurities are selectively ion-implanted with a small implantation amount to form a relatively thin N ⁻ -type buried layer 2b only in the CMOS transistor formation region B. This may be done as shown in FIG.

Then, after removing the resist 30 used for the mask, the relatively thick N ⁺ type buried layer 2a in the bipolar transistor formation region A and the relatively thin N ⁻ in the CMOS transistor formation region B are used. An N-type epitaxial growth layer 4 having a relatively small thickness (for example, about 4 μm or less) is provided on the semiconductor substrate 1 which includes the P-type buried layer 2b and the P-type buried layer 3 surrounding the bipolar transistor formation region A. (FIG. 3C).

Next, the NM in the CMOS transistor formation region B on the N-type epitaxial growth layer 4 having a relatively small thickness is formed.
An OS transistor formation region Ba portion and a portion serving as an isolation region of the bipolar transistor formation region A, where a portion corresponding to the P-type buried layer 3 is selectively P-type.
The P-type well region 5 and the P-type diffusion region 6 are respectively formed by ion implantation of the N-type impurity, and the P-type well region 5 and the P-type diffusion region 6 are formed in the CMOS transistor formation region B on the N-type epitaxial growth layer 4 thus left. PMOS transistor formation region Bb
And the portion of the bipolar transistor formation region A become N-type well regions 7a and 7b, respectively.
An isolation oxide film 8 is selectively formed on each of the predetermined surface positions. Here, the respective N-type well regions 7a and 7b may be formed by selectively ion-implanting N-type impurities as in the case of the P-type well region 5. Then, by forming each of such parts, NM
The P-type well region 5 in the OS transistor formation region Ba is
The N-type well region 7a of the bipolar transistor formation region A is separated from the P-type semiconductor substrate 1 by the N-type well region 7b and the N ^- type buried layer 2d. This is separated from the N-type well region 7b of the transistor formation region Bb (FIG. 4D).

Then, as shown in FIG. 1, the N-type well region 7a in the bipolar transistor formation region A and the N-type well region 7b in the PMOS transistor formation region Bb are respectively formed by known means. An N ⁺ -type diffusion layer 9 serving as a collector electrode region is formed, and a bipolar transistor forming region A has a P region forming a base region.
Diffusion layer 10 and N-type diffusion layer 1 constituting the emitter region
1 are selectively formed to configure the NPN type bipolar transistor 100, and the NMOS transistor formation region B
For a, a gate electrode 12 is provided on the P-type well region 5 via a gate oxide film, and N-type source
A drain region 13 is formed to form an NMOS transistor 300. Further, for a PMOS transistor formation region Bb, a gate electrode 14 is provided on a N-type well region 7b via a gate oxide film, and P The source / drain region 15 is formed to configure the PMOS transistor 200. Thus, the intended Bi-CMOS device is obtained.

In the manufacturing process of the Bi-CMOS device according to this embodiment, a relatively thick N ⁺ -type buried layer is formed at the time of heat treatment in the active region forming process of each element component.
2a and N- type buried layer 2d having a relatively small thickness, N-type well region 7a in bipolar transistor formation region A and N ^- type buried layer 2d in PMOS transistor formation region Bb.
Type well region 7b, the impurity is diffused into the P-type well region 5 in the NMOS transistor formation region Ba, the respective N ⁺ -type buried layer 2a, and the N ^- type spreads impurity diffusion of the buried layer 2d are each Because of the difference, the effective collector width in one N ⁺ -type buried layer 2a is formed thin, and the other N ⁻
The effective base width in the mold buried layer 2b is formed to be large.

Therefore, even if the thickness of the N-type epitaxial growth layer 4 is relatively thin, about 3 μm or less, as described above, the N ⁺ epitaxial growth layer 4 has N ⁺ from the surface of the N-type epitaxial growth layer 4 on the bipolar transistor formation region A side. The depth to the mold buried layer 2a is relatively shallow, and CMOS
On the transistor forming region B side, the depth from the surface of the N-type epitaxial growth layer 4 to the N ⁻ -type buried layer 2b becomes relatively deep. In other words, in other words, the effective collector width of the collector region in the bipolar transistor formation region A is reduced, and the NMOS transistor formation region A
The effective base width of the base region of the parasitic NPN transistor in Ba is made thicker. As a result, in order to maintain the breakdown voltage of the parasitic NPN transistor as in the related art,
The effective collector width of the collector region of the bipolar transistor in the bipolar transistor formation region A can be reduced without increasing the base width of the PN transistor, that is, without increasing the film thickness of the N-type epitaxial growth layer 4.
It is possible to effectively suppress the performance degradation such as a decrease in the cutoff frequency, and at the same time, the NMOS transistor formation region Ba
In this case, the effective base width of the base region of the parasitic NPN transistor can be increased, and a decrease in the breakdown voltage of the MOS transistor can be effectively suppressed.

In the above embodiment, the case where the present invention is applied to a Bi-CMOS semiconductor device has been described. However, the present invention can also be applied to a Bi-MOS semiconductor device having a bipolar transistor 100 and one of a PMOS transistor 200 and an NMOS transistor 300. Of course, the same function and effect can be exerted in this case.

〔The invention's effect〕

As described above in detail, according to the present invention, a relatively thick buried layer of a relatively high impurity concentration of the second conductivity type is formed in a bipolar transistor formation region on a semiconductor substrate.
A second region is formed in the MOS transistor formation region on the same semiconductor substrate.
By providing a buried layer having a relatively small conductivity type and a relatively low impurity concentration, and then performing a heat treatment, the bipolar transistor formation region has a comparatively thick comparatively thick second conductivity type. Buried layer with extremely high impurity concentration
Since a relatively thin buried layer of the second conductivity type and a relatively low impurity concentration can be formed in each of the transistor formation regions, for example, the thickness of the epitaxial growth layer is set to a relatively thin thickness of about 3 μm or less. Also, the effective collector width of the bipolar transistor in the bipolar transistor formation region can be reduced, and the effective base width of the parasitic NPN transistor base region in the MOS transistor formation region can be increased. It has excellent features such as being able to effectively suppress performance degradation such as a decrease in the voltage and maintaining the breakdown voltage of the parasitic NPN transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing an outline of a device configuration to which an embodiment of a Bi-CMOS semiconductor device according to the present invention is applied.
FIGS. 3A to 3D are cross-sectional views schematically showing main manufacturing steps of the above device sequentially, and FIG. 3 is a schematic diagram showing a schematic configuration of a conventional Bi-CMOS device. FIGS. 4 (a) to 4 (d) are cross-sectional views schematically showing main manufacturing steps of the above device sequentially. 100 NPN bipolar transistor, 200 PMOS transistor, 300 NMOS transistor, A bipolar transistor formation region, B MOS transistor region, Ba NMOS transistor formation region, Bb PMOS transistor formation region , 1 ...... P-type semiconductor substrate, 2a, 2b ...... N ⁺ -type buried layer, 2c, 2d ...... N ^- type buried layer 3 ...... P-type buried layer, 4 ...... N-type epitaxial layer, 5 ...... P type well region, 6 ...... P-type diffusion region, 7a, 7b ...... N-type well region, 8 ...... isolation oxide film, 9 ...... N ⁺ -type diffusion layer, 10 ...... P-type diffusion layer, 11 ...... N Diffusion layer, 12 ... Gate electrode, 13 ... N-type source / drain region, 14 ... Gate electrode, 15 ... P-type source / drain region, 20,30 ... Resist.

Continuation of the front page (56) References JP-A-2-237058 (JP, A) JP-A-1-122152 (JP, A) JP-A-61-236139 (JP, A) JP-A-64-73758 (JP , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/8249 H01L 21/8222

Claims (2)

(57) [Claims] 1. A semiconductor device comprising: a bipolar transistor formed in a bipolar transistor forming region on a semiconductor substrate of a first conductivity type; and a MOS transistor formed in a MOS transistor forming region on the semiconductor substrate.
An i-MOS semiconductor device, wherein the bipolar transistor is provided with a relatively thick, relatively high impurity concentration buried layer of a second conductivity type formed on a semiconductor substrate in the bipolar transistor formation region. The MOS transistor further includes a second conductive type relatively thin buried layer having a relatively low impurity concentration formed on the semiconductor substrate in a region where the MOS transistor is formed; A Bi-MOS semiconductor device, characterized in that the thick buried layer having a relatively high impurity concentration includes the same element as the buried layer having a relatively low impurity concentration. 2. A semiconductor device comprising: a bipolar transistor formed in a bipolar transistor forming region on a semiconductor substrate of a first conductivity type; and a MOS transistor formed in a MOS transistor forming region on the semiconductor substrate.
A method of manufacturing an i-MOS semiconductor device, comprising: forming a relatively thick buried layer of a relatively high impurity concentration of a second conductivity type corresponding to the bipolar transistor formation region on the semiconductor substrate. Forming a buried layer of a second conductive type having a relatively small thickness and a relatively low impurity concentration corresponding to the MOS transistor formation region on the semiconductor substrate; and Forming a relatively thin second conductivity type single crystal layer with a relatively low impurity concentration on the semiconductor substrate; and diffusing the second conductivity type impurity from each of the buried layers into the single crystal layer. And a method of manufacturing a Bi-MOS semiconductor device.