JP3077826B2 - Gate array test method and test apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method and a test apparatus for a gate array, and more particularly, to a technique for testing a plurality of probe lines previously incorporated in a gate array and a plurality of sense lines which are substantially orthogonal thereto. Things.

[0002]

2. Description of the Related Art Conventionally, as a technique for testing whether a large number of logic elements (logic gates) incorporated in a semiconductor integrated circuit normally operate, a scan path technique and a cross check technique have been generally adopted. I have. The former scan path method is a technique of sequentially supplying a plurality of test pattern signals to a semiconductor integrated circuit and analyzing an output pattern signal of the test pattern signal.
Since the number of logic elements incorporated in a semiconductor integrated circuit has become enormous, testing a semiconductor integrated circuit by such a scan path method requires a great deal of test time and labor, and the cost becomes large. , And a large number of flip-flop circuits need to be provided.

On the other hand, Japanese Patent Application Laid-Open No. 1-179338 discloses a technique for testing a semiconductor integrated circuit by the cross check method. In this test technique, as shown in FIG.
A number of probe lines P _i , P _{i + 1} , P _{i + 2} respectively corresponding to each row of the array of logic elements such as AND, NOR, INVERTER, DF / F, and an array of logic elements over many columns. A large number of sense lines S _j corresponding to each column,
S _{j + 1} , S _{j + 2} and many probe lines P _i ,
Many sense lines S _j orthogonal to P _{i + 1} and P _{i + 2} ,
S _{j + 1} and S _{j + 2} are incorporated and the probe lines P _i ,
Each logic element is arranged so as to correspond to each of a plurality of grid points where P _{i + 1} , P _{i + 2} intersect with the sense lines S _j , S _{j + 1} , S _{j + 2} . The test point TP of each logic element is MOSF
Each of the electronic switches EQ is connected to a corresponding sense line via an electronic switch EQ made of ET, and is configured to be turned on by a selection signal of a corresponding probe line. Here, in a state of supplying one of a plurality of test pattern signals to the semiconductor integrated circuit, for example, the probe line P _i "1" level of the selection signals a plurality of which are connected to the probe line P _i Supplying Since the electronic switch EQ becomes conductive, INVERTER, NAN
Test signals at test points TP such as D and NOR are output to the sense lines S _j , S _{j + 1} and S _{j + 2} , respectively.
A select signal of “1” level is supplied to _{i + 1} to output NOR, D−
A test signal at a test point TP such as an F / F is output in the same manner as described above, and the test is repeated for all the logic elements. Thereafter, the same test is repeated with the next test pattern signal supplied. Then, the operation states of all the logic elements of the semiconductor integrated circuit for all the test pattern signals are tested.

[0004]

In the test technique of the semiconductor integrated circuit disclosed in the above-mentioned publication, a large number of probe lines are connected to each test point such that a grid point at which a probe line and a sense line intersect one by one corresponds to each test point. It is necessary to provide a large number of sense lines. That is, when the lattice structure of the logic element, that is, the lattice structure of the test points has an array size of X rows and Y columns, it is necessary to provide X probe lines and Y sense lines. Since it is necessary to incorporate the probe line and the sense line, there is a problem that the integration degree of the semiconductor integrated circuit is remarkably reduced and the test device cannot be an economical test device. An object of the present invention is to provide a test method and a test apparatus for a gate array, which can surely perform a test similarly to the cross check method and can improve the economic efficiency.

[0005]

According to a first aspect of the present invention, there is provided a gate array test method in which a plurality of logic elements are two-dimensionally or three-dimensionally arranged in a plurality of rows and a plurality of columns. In a test method for testing a gate array via a plurality of probe lines and a plurality of sense lines, a plurality of rows of logic elements of the gate array are grouped into a plurality of row groups, and a plurality of columns of logic elements are grouped into a plurality of column groups. In the gate array, a plurality of probe lines respectively corresponding to a plurality of row groups and a plurality of sense lines respectively corresponding to a plurality of column groups are incorporated in the gate array, and a plurality of intersections of the probe lines and the sense lines are provided. A plurality of electronic switch devices each of which can output a signal to a corresponding sense line in response to a selection signal supplied to a corresponding probe line, each of which corresponds to a grid point of A plurality of electronic switch devices each including a plurality of electronic switches connected to a plurality of test points of a plurality of logic elements belonging to a row group and a column group, and connected to a corresponding sense line, and a plurality of gate switches are provided in the gate array. A first step of selectively supplying one of the test pattern signals;
Supplying a selection signal to one of the plurality of probe lines;
And generating a multilevel signal corresponding to a combination of a plurality of test point binary signals from each of the plurality of electronic switch devices corresponding to the selected probe line to each corresponding sense line. Three steps, a fourth step of converting the multi-valued signals generated on the plurality of sense lines into a reproduced binary signal corresponding to the combination of the binary signals, and outputting the reproduced binary signals; A fifth step of sequentially repeating the second to third steps, and a sixth step of repeating the first to fifth steps using sequentially different test pattern signals. .

According to a second aspect of the present invention, there is provided a gate array test apparatus in which a plurality of logic elements are two-dimensionally or
In a gate array test apparatus for testing a gate array through a plurality of probe lines and a plurality of sense lines incorporated in a gate array arranged in a three-dimensional manner, a plurality of logic elements in a plurality of rows of the gate array are provided. And grouping the logic elements of a plurality of columns into a plurality of column groups,
In this gate array, a plurality of probe lines respectively corresponding to a plurality of row groups and a plurality of sense lines respectively corresponding to a plurality of column groups, respectively correspond to a plurality of lattice points where the probe lines and the sense lines intersect, and A plurality of electronic switch devices capable of outputting a signal to a corresponding sense line in response to a selection signal supplied to a corresponding probe line, each including a plurality of logic elements belonging to a corresponding row group and column group And a plurality of electronic switch devices each including a plurality of electronic switches connected to corresponding test lines and connected to corresponding sense lines, respectively, and sequentially outputs a selection signal to one of the plurality of probe lines. A multi-level generating unit for providing a multi-level signal corresponding to a combination of the binary signals of a plurality of test points connected to a plurality of electronic switches of each of the electronic switch devices on a corresponding sense line; And a binarizing means for converting the multilevel signal generated on each of the sense lines into a reproduced binary signal corresponding to a combination of the binary signals at a plurality of test points. Is what you do.

According to a third aspect of the present invention, in the gate array testing apparatus according to the second aspect, each of the electronic switch devices is interposed between a plurality of electronic switches and a corresponding sense line, and responds to a selection signal. And a plurality of selection switches which are brought into a conductive state.

According to a fourth aspect of the present invention, there is provided a gate array test apparatus according to the third aspect, wherein in each of the electronic switch groups, a plurality of selection switches and a plurality of electronic switches are each constituted by an N-channel MOS transistor. The gate electrodes of the selection switches are connected to the probe lines, the drain electrodes of the selection switches are connected to the sense lines, the gate electrodes of a plurality of electronic switches are connected to a plurality of test points, respectively, and the drains of the electronic switches are connected. The electrodes are respectively connected to the source electrodes of the corresponding selection switches, and the source electrodes of these electronic switches are connected to the ground of the gate array.

According to a fifth aspect of the present invention, there is provided a gate array test apparatus according to the fourth aspect, wherein the multi-level converting means includes a gate array constant voltage source connected to each sense line via a resistor; Grounding of the gate array connected to the source electrodes of the plurality of electronic switches of the switch group, and W / L values of the plurality of electronic switches of each electronic switch group and / or the plurality of selection switches connected to the plurality of electronic switches And a configuration different from each other.

According to a sixth aspect of the present invention, in the gate array testing apparatus according to the second aspect, each of the electronic switch devices is interposed in common between a plurality of electronic switches and corresponding sense lines and responds to a selection signal. And one selection switch that is brought into a conductive state.

According to a seventh aspect of the present invention, in the gate array testing apparatus according to the fifth aspect, the binarizing means connected to each of the sense lines comprises an A / D converter. .

According to an eighth aspect of the present invention, in the gate array testing apparatus according to the seventh aspect, the selecting means includes a shift register which outputs a selection signal to a plurality of probe lines alternatively. It is.

According to a ninth aspect of the present invention, there is provided a gate array test apparatus according to the eighth aspect, further comprising an observation unit for receiving outputs of a plurality of binarization units connected to the plurality of sense lines, respectively. The means includes a shift register for temporarily storing the outputs of the plurality of binarizing means.

According to a tenth aspect of the present invention, in the gate array testing apparatus according to the third aspect, the plurality of selection switches and the plurality of electronic switches are each formed by a P-channel MOS transistor, and the gate electrodes of the plurality of selection switches are provided. Are connected to the probe lines, the drain electrodes of these selection switches are connected to the sense lines, the gate electrodes of a plurality of electronic switches are connected to a plurality of test points, respectively, and the drain electrodes of these electronic switches correspond to the selection switches. And the source electrodes of these electronic switches are connected to a constant voltage source of the gate array.

[0015]

In the gate array testing method according to the present invention, a plurality of rows of logic elements of the gate array are grouped into a plurality of row groups, and a plurality of columns of logic elements are grouped into a plurality of column groups. In advance, a plurality of probe lines respectively corresponding to a plurality of row groups and a plurality of sense lines respectively corresponding to a plurality of column groups are incorporated. Further, the gate array is provided in advance with a plurality of grid points where a plurality of probe lines and a plurality of sense lines intersect, respectively, and in response to a selection signal supplied to the corresponding probe line, a corresponding sense line is provided. A plurality of electronic switch devices capable of outputting signals, each of which is connected to a plurality of test points of a plurality of logic elements belonging to a corresponding row group and a column group, and is connected to a corresponding sense line. Incorporate a plurality of electronic switch devices with electronic switches. Here, when testing the gate array, a first step of selectively supplying one of a plurality of test pattern signals to the gate array is performed, and a first step of supplying a selection signal to one of the plurality of probe lines is performed. Two steps are performed, and a multilevel signal corresponding to a combination of the binary signals of the plurality of test points is applied to each of the plurality of electronic switch devices corresponding to the selected probe line to the corresponding sense line. Performing a third step of generating, and converting a multi-level signal generated on a plurality of sense lines into a reproduced binary signal corresponding to a combination of the binary signals, and outputting the reproduced binary signal; A fifth step of sequentially repeating the second to fourth steps is performed for the probe line, and a sixth step of sequentially repeating the first to fifth steps using different test pattern signals is performed. In this way, a test can be reliably performed on all test points for each of the plurality of test pattern signals. According to the gate array test method, a plurality of logic elements, that is, a plurality of test points can be associated with each grid point of the probe line and the sense line, so that the number of probe lines and sense lines can be significantly reduced. Becomes possible. That is, if the test points of the gate array have an X-row, Y-column array structure and the plurality of test points corresponding to each grid point have an α-row, β-column array structure, the number of probe lines is X / α, The number of sense lines becomes Y / β, and these numbers can be greatly reduced.

In a gate array test apparatus according to a second aspect, a plurality of rows and a plurality of columns of logic elements of the gate array are grouped into a plurality of row groups and a plurality of column groups, and a plurality of logic elements corresponding to the plurality of row groups, respectively. Probe lines and a plurality of sense lines respectively corresponding to a plurality of column groups are incorporated in the gate array, and further, a plurality of probe lines correspond to a plurality of grid points where the plurality of sense lines intersect and correspond to the corresponding probe lines. A plurality of electronic switch devices capable of outputting a signal to a corresponding sense line in response to a supplied selection signal, each being provided at a plurality of test points of a plurality of logic elements belonging to a corresponding row group and column group, respectively. A plurality of electronic switch devices having a plurality of electronic switches connected and connected to corresponding sense lines are incorporated in the gate array. Here, when testing this gate array, in a state where one of a plurality of test pattern signals is supplied to the gate array, the selection means sequentially outputs a selection signal to one of the probe lines. A plurality of selection switch devices corresponding to the probe lines to which the signals have been supplied are ready to output signals to the corresponding sense lines. Then, the multi-level conversion means corresponds to the multi-level conversion signal corresponding to the combination of the binarization signals of the plurality of test points connected to the plurality of electronic switches of each electronic switch device corresponding to the selected probe line. Since it is generated on the sense line, 2
The binarizing means converts the multilevel binarized signal generated on each sense line into a reproduced binarized signal corresponding to a combination of binarized signals at a plurality of test points. Next, the selection signal is sequentially supplied from the selection means for all the probe lines to generate the binarized signals in sequence, whereby a group of reproduced binarized signals is obtained. Thereafter, a plurality of groups of reproduced binarized signals are obtained in the same manner as described above by sequentially using different test pattern signals, and a gate array of the gate array is obtained based on the plurality of groups of reproduced binarized signals thus obtained. The operation of many logic elements can be tested for good or bad. In this gate array test apparatus, each electronic switch device is associated with each grid point of a probe line and a sense line, and each electronic switch device has a plurality of logic elements connected to a plurality of test points of a plurality of logic elements. Since an electronic switch is provided, similar to claim 1,
The number of probe lines and sense lines can be significantly reduced. That is, the test points of the gate array have an array structure of X rows and Y columns, and a plurality of test points corresponding to each grid point are α rows,
Assuming an array structure of β rows, the number of probe lines is X / α and the number of sense lines is Y / β.

In the gate array test apparatus according to the third aspect, basically the same operation as that of the second aspect is obtained.
Further, each electronic switch device includes a plurality of electronic switches and one or more electronic switches.
Since a plurality of selection switches corresponding to each other are provided, stable performance can be obtained, and it is advantageous in configuring a multi-valued means.

In the gate array test apparatus according to the fourth aspect, basically the same operation as that of the third aspect is obtained.
Further, in each electronic switch group, the plurality of selection switches and the plurality of electronic switches are each formed of an N-channel MOS transistor, the gate electrodes of the plurality of selection switches are respectively connected to the probe lines, and the drain electrodes of these selection switches are The gate electrodes of the plurality of electronic switches are respectively connected to the plurality of test points, and the drain electrodes of these electronic switches are connected to the source electrodes of the corresponding selection switches, respectively, and the source electrodes of these electronic switches are connected to the sense lines. It is connected to the ground of the gate array.
Accordingly, in response to the selection signal, the plurality of selection switches are turned on, the plurality of electronic switches are connected to the corresponding sense lines in a conductive state, and a "1" level signal is sent from the test point to the gate electrode of the electronic switch. When supplied, the electronic switch is turned on, and when the "0" level signal is supplied, it is kept off. As described above, since the selection switch and the electronic switch are each formed of a small N-channel MOS transistor that operates at a high speed, it is possible to prevent a reduction in the degree of integration and a reduction in operation speed due to these switches as much as possible.

In the gate array test apparatus according to the fifth aspect, basically the same operation as that of the fourth aspect is obtained.
Further, the multi-level converting means includes a constant voltage source of a gate array connected to each sense line via a resistor, a ground of a gate array connected to source electrodes of a plurality of electronic switches of each electronic switch group, and A plurality of electronic switches of an electronic switch group and / or a plurality of selection switches connected to the plurality of electronic switches, wherein the W / L values are different from each other. That is, when the selection switch is turned on by the selection signal and the electronic switch is turned on by the "1" level signal at the test point, a current path from the constant voltage source to the ground is formed. Since the W / L values of the plurality of electronic switches and / or the plurality of selection switches connected to the plurality of electronic switches are different from each other, a voltage signal corresponding to the current path is sensed downstream of the resistor. A multi-level signal corresponding to a combination of the binarized signals at a plurality of test points can be generated on the sense line because it appears on the line portion.

In the gate array test apparatus according to the sixth aspect, basically the same operation as the second aspect can be obtained.
Furthermore, since each electronic switch device is provided with one selection switch common to a plurality of electronic switches, the number of selection switches can be reduced to a minimum.

In the gate array test apparatus according to the seventh aspect, basically the same operation as the fifth aspect can be obtained.
Further, since the binarizing means connected to each sense line is constituted by an A / D converter, the multi-valued signal can be easily converted to a reproduced binary signal.

In the gate array testing apparatus according to the eighth aspect, basically the same operation as that of the seventh aspect is obtained.
Further, since the selection means includes a shift register for selectively outputting a selection signal to a plurality of probe lines, the selection means can be simplified, and the shift register of the gate array can be effectively used. is there.

In the gate array test apparatus according to the ninth aspect, basically the same operation as that of the eighth aspect can be obtained.
Further, there is provided observation means for receiving the outputs of the plurality of binarization means respectively connected to the plurality of sense lines, and the observation means includes a shift register which receives the outputs of the plurality of binarization means and temporarily stores the outputs. The observation means can be simplified, and the shift register can be effectively used as a shift register.

In the gate array test apparatus according to the tenth aspect, basically the same operation as the third aspect is obtained. Further, the plurality of selection switches and the plurality of electronic switches are each configured by a P-channel MOS transistor,
The gate electrodes of the plurality of selection switches are respectively connected to the probe lines, the drain electrodes of these selection switches are respectively connected to the sense lines, the gate electrodes of the plurality of electronic switches are respectively connected to the plurality of test points, and Drain electrodes are respectively connected to the source electrodes of the corresponding selection switches, and the source electrodes of these electronic switches are connected to the constant voltage source of the gate array. Therefore, the selection switch is turned on by the selection signal, and the corresponding electronic switch is turned on by the "1" level signal of the test point, so that the electronic switch and the selection switch are switched from the constant voltage source. Thus, a current path to the sense line via the current path is formed.

[0025]

As described above, the following effects can be obtained. According to the gate array test method of the present invention, all test points can be reliably tested with a plurality of test pattern signals, and a plurality of test points are provided at each grid point of a probe line and a sense line. The number of probe lines and sense lines can be significantly reduced in order to cope with the problem. Economic efficiency can be dramatically improved.

According to the gate array test apparatus of the present invention, a plurality of probe lines, a plurality of sense lines, a selection means, and an electronic switch device corresponding to each grid point are provided. By providing an electronic switch device having a plurality of electronic switches connected to each other, a multi-valued means, and a binarized means, the number of probe lines and sense lines is significantly reduced as in claim 1. This makes it possible to prevent a reduction in the degree of integration of the gate array due to a large number of probe lines and a large number of sense lines, thereby dramatically improving the practicality and economy of the test apparatus.

According to the gate array test apparatus of the third aspect, basically the same effects as those of the second aspect can be obtained. Further, by providing a selection switch corresponding to a plurality of electronic switches on a one-to-one basis, stable performance can be obtained, and it is advantageous in configuring a multi-valued means.

According to the gate array test apparatus of the fourth aspect, basically the same effects as those of the third aspect can be obtained. Further, since the plurality of selection switches and the plurality of electronic switches are each formed of a small-sized N-channel MOS transistor which operates at high speed, it is possible to minimize the reduction in the degree of integration and the reduction in operation speed due to these switches.

According to the gate array test apparatus of the fifth aspect, basically the same effects as those of the fourth aspect can be obtained. Further, since the multi-value conversion means effectively utilizes the constant voltage source of the gate array and the ground of the gate array, the configuration can be simplified. Since the plurality of electronic switches and / or the plurality of selection switches connected to the plurality of electronic switches are configured to have different W / L values, the configuration is simplified.

According to the gate array test apparatus of the sixth aspect, basically the same effects as those of the second aspect can be obtained. Furthermore, since one common selection switch is provided for a plurality of electronic switches of each electronic switch device, the number of selection switches can be reduced to a minimum.

According to the gate array test apparatus of the seventh aspect, basically the same effects as those of the fifth aspect can be obtained. Further, since the binarizing means connected to each sense line is constituted by an A / D converter, the multi-valued signal can be converted into a reproduced binary signal by a simple configuration.

According to the gate array testing apparatus of the eighth aspect, basically the same effects as those of the seventh aspect can be obtained. Further, since the selection means includes a shift register for selectively outputting a selection signal to a plurality of probe lines, the selection means can be simplified, and the shift register of the gate array can be effectively used. is there.

According to the gate array test apparatus of the ninth aspect, basically the same effects as those of the eighth aspect can be obtained. Further, there is provided observation means for receiving the outputs of the plurality of binarization means respectively connected to the plurality of sense lines, and the observation means includes a shift register which receives the outputs of the plurality of binarization means and temporarily stores the outputs. The observation means can be simplified, and the shift register can be effectively used as a shift register.

According to the gate array test apparatus of the tenth aspect, basically the same effects as those of the third aspect can be obtained.
Furthermore, since the plurality of selection switches and the plurality of electronic switches are each formed of a small P-channel MOS transistor, it is possible to prevent a reduction in the degree of integration of these switches, and the P-channel MOS transistor has a high conduction resistance. Therefore, it is advantageous to use these switches as a resistance of the current path as a part of the multilevel means.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, the present invention is applied to a test method and a test apparatus for a gate array. First, the basic configuration of the test apparatus will be described. As shown in FIG. 1, the test apparatus includes logic elements LE _{1 to} LE _i (hereinafter, referred to as logic elements) having various functions.
The probe lines P _{1 to} P _m (hereinafter referred to as “P”) are two-dimensionally incorporated into the gate array GA having the LE.
) And n sense lines S _{1 to} S _n (hereinafter, collectively referred to as S) arranged substantially orthogonal to the m probe lines P, and are arranged on the periphery of the gate array GA. A selection device SD connected to each probe line P;
And m × n sets of electronic switch devices DA _{11 to} DA _mn (hereinafter, collectively referred to as DA) incorporated in the gate array GA in association with grid points at which the gate lines GA cross each other. Binarization devices AD _{1 to} AD which are arranged at the periphery and connected to respective sense lines S at input terminals, respectively.
_n (hereinafter collectively referred to as AD) and an observation device O arranged at the periphery of the gate array GA and connected to the binarization device AD.
D, and a test electronic device TE which is arranged outside the gate array GA and connected to a plurality of pads PD provided on a peripheral portion of the gate array GA via a probe.

Each of the electronic switch devices DA has an i
Test points TP _{1 to} TP on the output lines of the logic elements LE
_i (hereinafter, collectively referred to as TP), each of which includes an i number of electronic switches EQ connected to each other to form an electronic switch group G, and i selection switches SQ connected to each electronic switch EQ in a one-to-one correspondence. And a selection switch SQ connected to the corresponding probe line P and sense line S. The selection device SD sequentially outputs a selection signal to one of the probe lines P, and turns on the selection switch SQ of each electronic switch device DA connected to the probe line P to which the selection signal is supplied, As described later, when a selection signal is output to the probe line P, it corresponds to a combination of the binarized signal of the test point TP of each logic element LE connected to the probe line P via each electronic switch device DA. The multi-valued signal is generated on each of the sense lines S. The binarizing device AD reproduces the multi-valued signal generated on the sense line S to which it is connected into the original binarized signal at the i test points TP of each group. Are connected to the observation device OD via _i output lines L _{1 to} L _i (hereinafter collectively referred to as L) corresponding to the i test points TP respectively connected to the i electronic switches EQ. . The i reproduced binarized signals reproduced by each binarization device AD are output to the observation device OD via output lines L corresponding to the test points TP, respectively.
Is output to The observation device OD is for temporarily storing the reproduced binarized signal output from the binarization device AD and outputting it to the test electronic device TE at a predetermined timing. The test electronic device TE includes an input terminal of each logic element LE, a selection device SD, and an observation device OD via a pad PD formed on the gate array GA by the probe.
And electrically input to the gate array GA to input various known test pattern signals and input data and clock signals to the selection device SD and the observation device OD.
Analyzing the reproduced binary signal output from the observation device OD,
The judgment of pass / fail of the gate array GA, identification of defective logic elements, performance evaluation, and the like are performed. Test electronics TE
Has a pattern generation unit, a timing generation unit, a control unit, a fail memory, a formatter, and the like, and is substantially the same as a well-known device for testing a semiconductor integrated circuit. Therefore, detailed description is omitted in the following description. .

Next, an example of a detailed configuration of the test apparatus will be described with reference to FIG. Each electronic switch group G
The number of test points TP connected to is set to two. The electronic switch devices DA arranged corresponding to each of the lattice points at which the m probe lines P and the n senses S incorporated in the gate array GA intersect each other have the outputs of the logic elements LE ₁ and LE ₂ . the electronic switch EQ ₁ · EQ ₂ consisting of N-channel type MOS transistors are respectively connected to the test point TP ₁ · TP ₂ on line constituting the electronic switches G, respectively connected to each of the electronic switches EQ ₁ · EQ ₂ Selection switch SQ ₁ · S composed of N-channel type MOS transistor
Is composed of a Q _2, selection device SD for outputting a selection signal to the probe line P is, m-number of D-type flip-flops FF ₁ ~
FF _m is cascade-connected, and a binarizing device AD connected to each sense line S is a 2-bit A / A.
It has a D converter. Each sense line S, the electronic switch multivalued signal corresponding to a combination of the binary signal at the electronic switch EQ ₁ · EQ ₂ respectively connected to the test point TP ₁ · TP ₂ of each electronic switch group G EQ ₁・ EQ ₂
And the sense line S in cooperation with the selection switches SQ ₁ and SQ _2.
Is connected to the constant voltage source Vc of the gate array GA via the resistor R in order to generate the voltage. The observation device OD includes n 2-bit serial / parallel shift registers SR _{1 to} SR _1
n (hereinafter collectively referred to as SR) in cascade,
Each binarization device AD and the corresponding shift register SR
Are connected via _two output lines K ₁ and K ₂ , and these lines K ₁ and K ₂ are associated with test points TP ₁ and TP ₂ , respectively. The selection device SD is a test electronic device T
Together with the control data and clock signals from the E is connected to the pad PD ₁ · PD ₂ are respectively inputted, the pad PD ₃ for outputting control data to the test electronics TE
The observation device OD includes a pad PD to which a clock signal from the test electronic device TE, a mode setting signal for setting each shift register SR to the serial mode or the parallel mode, and test observation data are respectively input. _{4 to} PD ₇
Is connected, is connected to the pad PD ₈ · PD ₉ for outputting the reproduced binary signal in the test electronics TE has to. The selection device SD and the observation device OD are configured using the logic elements LE of the gate array GA.

The selection signal for selecting the probe line P is "1".
Assuming that the level and the non-selection non-selection signal are "0" level, when testing the gate array GA, a non-selection signal is first supplied to all the probe lines P to initialize them, and then the test electronics TE via pads PD _i for input supplying a selected one of the plurality of test pattern signals to the gate array GA. Then selected that is connected to the probe line P ₁ outputs a selection signal to the probe line P ₁ by inputting "1" level of the control data in the first time at the rising edge of the clock signal input from the pad PD ₁ thereby turning the switch S Q ₁ · S Q _2. At this time, corresponding to the sense lines S, multilevel signal corresponding to a combination of the binary signal of the test points TP ₁ · TP ₂ is generated from each of the n sets of electronic switches G corresponding to probe line P ₁ I do. The multi-valued signals generated on the sense lines S are respectively supplied to the corresponding binarizing devices A.
D reproduces the binarized signals at the original test points TP ₁ and TP ₂ , and reproduces the reproduced binarized signals at the test points TP ₁ and T
It is output to the corresponding shift register SR of the observation device OD via the output lines K ₁ and K ₂ corresponding to P ₂ . Each 2
The reproduced binarized signal output to the digitizing device AD is temporarily stored by the observation device OD, and thereafter is sequentially output from the observation device OD to the test electronic device TE at a predetermined timing. By then entering the control data of "0" level every time the second and subsequent rise of the clock signal, the selection signal to the probe line P sequentially adjacent the probe line P ₁ is output, the (m + 1) th clock during the rise of the signal is output selection signal to the probe line P _m. In this way, the selection signals are sequentially supplied to the other probe lines P,
In the same manner as described above, generation of a multilevel signal on each sense line, reproduction to a binary signal, output of the reproduced binary signal to the observation device OD, and a test electronic device TE for the reproduced binary signal Is repeated. When the test for one test pattern signal is completed in this way, another test pattern signal is selected, and the test is performed through all the probe lines P in the same manner as described above. A test is performed on the test pattern signal. The symbol PD _O is an output pad.

[0039] When the selection signal to the probe line P ₅ example of the probe line P is output, a constant voltage source Vc, resistance R, the selection switch SQ ₁ · SQ ₂ and the electronic switch EQ
_{By the 1} · EQ ₂ , the multilevel signal corresponding to one of four combinations of the “1” or “0” level binary signal at the test points TP ₁ and TP ₂ is applied to the sense line S. ₂ generated is input to the binarization unit AD _2. This multi-valued signal is supplied to the test points TP ₁ and TP ₁ by the binarization device AD _2.
The original binarized signal at TP ₂ is reproduced, and the reproduced binarized signal is output from the output line K corresponding to the test points TP ₁ and TP _2.
The output of the observation device OD through a ₁ · K ₂ corresponding to the shift register SR _2. Similarly, the binarized signals of the test points TP ₁ and TP ₂ of the other groups connected to the probe line P ₅ via the other electronic switch devices DA are respectively multi-valued, and the corresponding binarizing devices AD And is output to the observation device OD. Observation device OD from each binarization device AD
It reproduced binarized signal output to the observation device when the clock signal each shift register SR is inputted and from the pad PD ₄ have been set to the parallel mode by the mode setting signal of the observation device OD rises to the first time stored in the OD, then after being set to the serial mode by the shift register SR mode setting signal, the multi-level signal output to the sense line S _n every time the clock signal of the second and subsequent times is input The reproduced binarized signals of the multi-valued signals sequentially output to the adjacent sense lines S from the reproduced binarized signals are supplied to the pads PD ₈ and P _8.
Test through D ₉ are output to the electronic device TE.

Next, an example of a combination of binarized signals at the test point TP and a corresponding multi-valued signal generated on the sense line S will be described in detail with reference to FIGS.
Incidentally, the output selection signal to the probe line P ₅ and the sense line S
_The multilevel signal generated in ₂ will be described as an example. As shown in FIG. 3, the electronic switch device DA ₅₂ of the probe line P ₅ and the sense line S ₂ is arranged corresponding to the grid point intersection, N
Consisting of channel type MOS transistors and having a test point T
Electronic switches EQ ₁ and E connected to P ₁ and TP _{2 respectively}
Q ₂ and select switches SQ ₁ and SQ ₂ each formed of an N-channel MOS transistor and connected to each of the electronic switches EQ ₁ and EQ _2.
The gate electrode, the source electrode and the drain electrode of Q ₁ · EQ ₂ correspond to the corresponding test points TP ₁ · TP ₂ , the ground GND of the gate array GA and the corresponding selection switch SQ ₁ ·
Connected to the source electrode of SQ ₂ and each selection switch SQ ₁
Gate electrode and the drain electrode of the SQ ₂ is connected to the sense line S ₂ respectively probe line P _5. Thus, the electronic switches EQ ₁ and EQ ₂ and the selection switches SQ ₁ and SQ
By connecting _2, when the "1" level of the selection signal to the probe line P ₅ is not supplied, electrically disconnected from the sense line S ₂ do not conduct the selection switch SQ ₁ · SQ ₂ and the ground GND is, when the the selection signal to the probe line P ₅ are supplied, since the selector switch SQ ₁ · SQ ₂ conducts, according to "1" or "0" of the binary signal at the test point TP ₁ · TP ₂ the sense line S ₂ Te and the ground GND
Are electrically connected or disconnected.

[0041] In the state of connecting the sense line S ₂ to a constant voltage source Vc by a predetermined impedance, the selection signal is supplied to the probe line P _5, a set of binary signals in each test point TP ₁ · TP ₂ as the current of the correspondingly constant voltage source through a Vc from the resistor R can form a current path of the four kinds is the current flowing in the sense line S ₂ and different current values for each of these current paths in the mating flows to the sense line S ₂ The W / L values of the electronic switches EQ ₁ and EQ ₂ are set to be the same, and the W / L values of the selection switches SQ ₁ and SQ ₂ are set to be different from each other. That is, in the state where the selection signal is outputted to the probe line P _5, test points TP ₁ · TP _{2 2}
Both binary signal both "0" level, the binary signal is "0" level of the test point TP ₂ binary signal test points TP ₁ is "1" level, the binary signal of the test points TP ₁ is formed as the case binarized signal test point TP ₂ is "1" level, both the binary signal both test points TP ₁ · TP ₂ "1" level of each of at but "0" level Ground G from constant voltage source Vc
The current flowing through the current path of the four types leading to ND sense line S ₂ and binarizing circuit AD ₂ of the input terminal 's respectively the voltage level of the multilevel signal generated at the intersection Ip with V _00, V _10, V
When ₀₁ and V _11, as shown in FIG. 4, V _00> V _10>
The W / L values of the selection switches SQ ₁ and SQ ₂ are set to be different from each other so that multi-values are obtained in a relationship of V ₀₁ > V ₁₁ . Thus, the voltage signal corresponding to the combination of the binarized signals at the test points TP ₁ and TP ₂ is the binarized device A
D ₂ , and the multi-valued signal is supplied to a binarization device AD ₂
The reproduced into the original binary signal of the test points TP ₁ · TP _2, the output line K ₁ · corresponding to the test points TP ₁ · TP ₂
Is output to the observation device OD via the K _2.

Next, an example in which the logic element LE of the gate array GA, the electronic switch device DA, and the test point TP are specifically shown will be described in detail with reference to FIG. It is assumed that the number of test points TP connected to each electronic switch group G is four. In the vicinity of a lattice point where the sense line S _i and the probe line P _i intersect, as a group of logic elements LE corresponding to this lattice point, an inverter LE ₁ , a NAND LE ₂ , a NOR LE _3, and a D-type flip-flop LE ₄ is a logic element LE is arranged such, test points TP ₁ ~ positive logic output on line of logic elements LE ₁ ~LE ₃ output on line and the logic element LE ₄
TP ₄ are respectively provided, the electronic switch EQ ₁ These test points TP ₁ to TP ₄ constituting the respective electronic switches G
To EQ ₄ are connected. Electronic switches EQ _{1 to} EQ
₄ is composed of each N-channel type MOS transistor, a gate electrode of the electronic switch EQ ₁ ~EQ _4, the source electrode and the drain electrode, the corresponding test point TP ₁ to TP
_4, are respectively connected to the source electrode of the selection switches SQ ₁ ~SQ ₄ corresponding constituted by the ground GND and N-channel type MOS transistor of the gate array GA, the gate electrode and the drain electrode of the selection switches SQ ₁ ~SQ ₄ are each It is connected to the probe line P _i and the sense line S _i .

As described above, by connecting the electronic switches EQ _{1 to} EQ ₄ and the selection switches SQ _{1 to} SQ ₄ , it is determined corresponding to 16 combinations of the binarized signals at the test points TP _{1 to} TP ₄ . as is the current path 16 types for the current flowing in the sense line S _i from the voltage source Vc through a resistor R is formed, the current of different current values for each of these current paths flows through the sense line S _i, each of the electronic Switch EQ _1-
The W / L value of EQ ₄ is set to the same value and the selection switch SQ
₁ W / L value of ～SQ ₄ is set to be different from each other. By thus setting the W / L value of the electronic switch EQ ₁ ~EQ ₄ and selection switches SQ ₁ ~SQ _4, the voltage level corresponding to the combination of the binarized signal at the test point TP ₁ to TP ₄ it is possible to generate different multilevel signal to the sense lines S _i.

FIG. 6 shows a part of an example of the layout of the probe lines P, the sense lines S and the switch device DA in the gate array GA. In this layout,
As shown in the equivalent circuit diagram of FIG.
Transistor Q _1, N-channel type MOS transistors Q ₂ and inverter LE ₁ that is constituted by, P-channel MOS transistor Q ₃ · Q ₄ and N-channel type MO
NAND LE ₂ composed of S transistors Q ₅ and Q ₆
Are provided as the logic element LE. Switch device DA _ii, the test point on the output line of the inverter LE ₁ T
P ₁ to the connected electronic switches EQ ₁ and connected thereto a selected switch SQ ₁ and NAND LE ₂ of the electronic switches connected to the test point TP ₂ on the output line EQ ₂ and connected select switch SQ thereto It consists of _two . Electronic switch EQ ₁ · EQ ₂ and select switch SQ
₁ · SQ ₂ is formed of an N-channel type MOS transistor, for generating a multilevel signal, W / L values of the selection switches SQ ₁ · SQ ₂ is laid out so different from each other in the sense line S _i .

As described above, according to the test apparatus for the gate array GA, the test points TP of the gate array GA are set to X rows and Y rows.
In the case of a column array structure, if a plurality of test points TP corresponding to each grid point are arranged in α rows and β columns, the number of probe lines P is X / α and the number of sense lines S is Y. / Β remarkably, and prevents a large number of probe lines P and a large number of sense lines S from deteriorating the degree of integration of the gate array GA, thereby increasing the practicality and economy of the test apparatus. Can be increased.

Here, as shown in FIG. 8, the selection switch SQ connected to each electronic switch EQ of the electronic switch device DA can be shared by one selection switch SQ. Electronic switching device DA _ii is the one that is connected connected to the electronic switch EQ ₁ and electronic switch connected to a test point TP ₂ EQ ₂ and the electronic switch EQ ₁ · EQ ₂ in the test point TP ₁ selection switch SQ ₁ The W / L values of the electronic switches EQ ₁ and EQ ₂ are set to be different from each other. By configuring the electronic switch device DA _ii in this manner, the test point TP ₁ is set in the same manner as in the above embodiment.
- a multi-level signal corresponding to a combination of the binarized signal at TP ₂ can be generated on the sense line S _i, and an electronic switch device DA _ii can reduce the number of selection switches SQ constituting the.

[Another Embodiment] The test apparatus of this embodiment converts the multilevel signal output to a plurality of sense lines S into one common
The binarization device AD is configured to perform binarization.
As shown in FIG. 9, each of the sense lines S incorporated in the gate array GA is provided with a selection device S composed of an analog switch.
DA is connected, one binarizing device AD is connected to the selecting device SDA via a line H, and the binarizing device AD has the same number of output lines as the number of test points TP connected to the electronic switch device DA. through L ₁ ~L _i is connected to the observation apparatus ODA. The multi-valued signal output to the sense line S by sequentially outputting the selection signal from the selection device SD to the probe line P is output to each of the sense lines S by the selection device SDA.
2 at a predetermined timing for each multi-level signal output to
Is output to the binarizing circuit AD, binarization device as the original binary signal by AD is outputted to the observation apparatus ODA from the output line L ₁ ~L _i corresponding to being reproduced test points TP ₁ to TP _i It has become. By configuring the test apparatus in this manner, the binarization apparatus AD and the observation apparatus OD can be reduced in scale, and the number of lines connecting them can be significantly reduced.

The electronic switch EQ and the selection switch S
Q can be formed by a P-channel MOS transistor, and is not limited to a MOS transistor, but may be formed by a bipolar transistor, a Josephson element, or a GaAs element. Further, in the embodiments other than the above-described modification, the W / L values of the electronic switches EQ constituting the electronic switch device DA are set to be the same, and the W / L values of the selection switches SQ are set to be different from each other. But,
The W / L value of the selection switch SQ may be set to be the same, and the W / L value of the electronic switch EQ may be set to be different from each other, or the W / L value of the combination of the electronic switch EQ and the selection switch SQ may be set. The settings may be different from each other.
Further, it is also possible to observe a signal generated on the sense line S using a laser beam or an electron beam, and to output a selection signal to the probe line P.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a gate array test apparatus.

FIG. 2 is a detailed circuit diagram of the test apparatus.

FIG. 3 is a circuit diagram showing a connection between an electronic switch device and a binarization device.

FIG. 4 is a diagram illustrating an example of a multi-level signal output to a sense line;

FIG. 5 is a circuit diagram showing an example of an electronic switch device.

FIG. 6 is a layout diagram illustrating an example of a sense line, a probe line, and a switch device.

FIG. 7 is an equivalent circuit diagram of FIG. 6;

FIG. 8 is a view corresponding to FIG. 3 of a gate array test apparatus according to a modification.

FIG. 9 is a diagram showing a gate array test apparatus according to another embodiment.
FIG.

FIG. 10 is a diagram corresponding to FIG. 5 of a test apparatus for a semiconductor integrated circuit according to the related art.

[Explanation of symbols]

 AD Binarization device DA Electronic switch device EQ Electronic switch G Electronic switch group GA Gate array GND Ground OD / ODA observation device P Probe wire R Resistance S Sense wire SD Select device SQ Select switch TE Test electronic device Vc Constant voltage source

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 H01L 21/66 H01L 21/822 H01L 27/04 H01L 27/118

Claims (10)

(57) [Claims] 1. A gate array having a plurality of logic elements arranged in a plurality of rows and a plurality of columns in a two-dimensional or three-dimensional manner and incorporated in a gate array through a plurality of probe lines and a plurality of sense lines. In the test method for testing, the logic elements in a plurality of rows of the gate array are grouped into a plurality of row groups, and the logic elements in a plurality of columns are grouped into a plurality of column groups. A plurality of probe lines and a plurality of sense lines respectively corresponding to a plurality of column groups are respectively incorporated, and probe lines respectively corresponding to and corresponding to a plurality of grid points at which the plurality of probe lines and the plurality of sense lines intersect. A plurality of electronic switch devices capable of outputting a signal to a corresponding sense line in response to a selection signal supplied to a plurality of logic elements belonging to a corresponding row group and column group. A plurality of electronic switch devices each having a plurality of electronic switches connected to corresponding test lines and connected to corresponding sense lines, respectively, and selectively supplying one of a plurality of test pattern signals to the gate array. And a second step of supplying a selection signal to one of the plurality of probe lines.
And generating a multilevel signal corresponding to a combination of the binary signals of the plurality of test points on each of the corresponding sense lines from each of the plurality of electronic switch devices corresponding to the selected probe line. Three steps; a fourth step of converting the multi-valued signals generated on the plurality of sense lines into a binary signal corresponding to the combination of the binary signals and outputting the converted signals; A gate array test, comprising: a fifth step of repeating each of the second to fourth steps; and a sixth step of repeating the first to fifth steps using different test pattern signals in sequence. Method. 2. A gate array via a plurality of probe lines and a plurality of sense lines incorporated in a gate array in which a plurality of logic elements are two-dimensionally or three-dimensionally arranged in a plurality of rows and a plurality of columns. A plurality of rows of logic elements of the gate array are grouped into a plurality of row groups, and a plurality of columns of logic elements are grouped into a plurality of column groups. A plurality of probe lines respectively corresponding to a group, a plurality of sense lines respectively corresponding to a plurality of column groups, and probe lines respectively corresponding to and corresponding to a plurality of grid points at which the plurality of probe lines and the plurality of sense lines intersect. A plurality of electronic switch devices capable of outputting a signal to a corresponding sense line in response to a selection signal supplied to a plurality of logic elements belonging to a corresponding row group and column group. Point incorporate a plurality of electronic switching device comprising a plurality of electronic switches connected to a sense line respectively connected to and corresponding to one of said plurality of probe lines
Selection means for sequentially outputting a selection signal, and corresponding to a multi-valued signal corresponding to a combination of binary signals of a plurality of test points connected to a plurality of electronic switches of each of the electronic switch devices. A multi-level conversion means for generating a multi-level signal generated on each of the sense lines, and converting the multi-level signal generated on each of the sense lines into a reproduced binarization signal corresponding to a combination of the binarization signals at a plurality of test points; A gate array test apparatus, comprising: means for providing a gate array. 3. The electronic switch device according to claim 1, further comprising a plurality of selection switches interposed between the plurality of electronic switches and the corresponding sense lines, and being turned on in response to a selection signal. The test device for a gate array according to claim 2. 4. In each of the electronic switch groups, a plurality of selection switches and a plurality of electronic switches are each constituted by an N-channel MOS transistor, and gate electrodes of the plurality of selection switches are connected to a probe line, respectively. Drain electrodes are connected to the sense lines, respectively.
The gate electrodes of the electronic switches are connected to a plurality of test points, respectively, and the drain electrodes of the electronic switches are connected to the source electrodes of the corresponding selection switches, respectively, and the source electrodes of the electronic switches are connected to the ground of the gate array. 4. The gate array test apparatus according to claim 3, wherein: 5. The multi-level converting means includes: a gate array constant voltage source connected to each sense line via a resistor; and a gate array connected to the source electrodes of a plurality of electronic switches of each electronic switch group. It is characterized by comprising grounding and a configuration in which W / L values of a plurality of electronic switches of each electronic switch group and / or a plurality of selection switches connected to the plurality of electronic switches are different from each other. The test apparatus for a gate array according to claim 4. 6. The electronic switch device according to claim 1, further comprising a selection switch that is commonly provided between the plurality of electronic switches and the corresponding sense line, and that is turned on in response to a selection signal. The test apparatus for a gate array according to claim 2. 7. The gate array test apparatus according to claim 5, wherein the binarizing means connected to each of the sense lines comprises an A / D converter. 8. The gate array test apparatus according to claim 7, wherein said selecting means includes a shift register for selectively outputting a selection signal to a plurality of probe lines. 9. A shift unit for receiving an output of a plurality of binarization units connected to the plurality of sense lines, and the observation unit receives and temporarily stores outputs of the plurality of binarization units. 9. The apparatus according to claim 8, further comprising a register. 10. The plurality of selection switches and the plurality of electronic switches are each constituted by a P-channel MOS transistor, the gate electrodes of the plurality of selection switches are respectively connected to probe lines, and the drain electrodes of these selection switches are connected to sense lines. , The gate electrodes of a plurality of electronic switches are respectively connected to a plurality of test points, and the drain electrodes of these electronic switches are respectively connected to the source electrodes of corresponding selection switches, and the source electrodes of these electronic switches are connected to a gate array. 4. The gate array test apparatus according to claim 3, wherein the gate array is connected to a ground .