JP3077876B2 - Surface treatment method for III-V compound semiconductor - Google Patents
Surface treatment method for III-V compound semiconductorInfo
- Publication number
- JP3077876B2 JP3077876B2 JP06194809A JP19480994A JP3077876B2 JP 3077876 B2 JP3077876 B2 JP 3077876B2 JP 06194809 A JP06194809 A JP 06194809A JP 19480994 A JP19480994 A JP 19480994A JP 3077876 B2 JP3077876 B2 JP 3077876B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- iii
- surface treatment
- compound semiconductor
- treatment method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 27
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004381 surface treatment Methods 0.000 title claims description 12
- 150000001875 compounds Chemical class 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims description 29
- 229910052785 arsenic Inorganic materials 0.000 claims description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical class [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000012433 hydrogen halide Substances 0.000 claims description 2
- 229910000039 hydrogen halide Inorganic materials 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000005336 cracking Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- -1 radicals form hydrides Chemical class 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、III−Ｖ族化合物半導
体の表面処理方法およびその装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for treating a surface of a III-V compound semiconductor.
【０００２】[0002]
【従来の技術】ＧａＡｓ，ＩｎＰ等のIII−Ｖ族化合物
半導体は、電子移動度がＳｉより数倍早いこと、バンド
構造が直接遷移型であること、半絶縁性基板が容易に得
られることなどの物理的性質により次世代のデバイス材
料として早くから脚光を浴びており、実際、高周波デバ
イス、低雑音デバイス、光デバイス、高速論理素子等に
応用されている。そして、デバイスの高性能化に伴っ
て、エピ成長技術、微細加工技術などのプロセス技術も
高度化している。その一つに、有機金属気相成長法（Ｍ
ＯＶＰＥ）や有機金属分子線エピタキシー法（ＭＯＭＢ
Ｅ）を用いて、絶縁膜によりマスクを施した基板上の、
半導体層のみに選択成長を行う選択成長法がある。この
方法では、たとえばＦＥＴのコンタクト層に用いるとソ
ース抵抗を低減することができるなど、新規構造が可能
になるため、最近、注目されている。2. Description of the Related Art Group III-V compound semiconductors such as GaAs and InP have electron mobility several times faster than Si, a direct transition band structure, and a semi-insulating substrate can be easily obtained. Due to its physical properties, it has been spotlighted as a next-generation device material from an early stage, and is actually applied to high-frequency devices, low-noise devices, optical devices, high-speed logic elements, and the like. As the performance of devices increases, process technologies such as epi growth technology and microfabrication technology also become more sophisticated. One of them is metal organic chemical vapor deposition (M
OVPE) and metalorganic molecular beam epitaxy (MOMB)
E) on a substrate masked with an insulating film using
There is a selective growth method for performing selective growth only on a semiconductor layer. This method has attracted attention recently because a new structure can be realized, for example, when the method is used for a contact layer of an FET, the source resistance can be reduced.
【０００３】しかしこのような再成長プロセスでは、界
面にカーボン（Ｃ）や酸素（Ｏ）などの不純物が残留
し、特にｎ型半導体の場合、これが電子のキラーセンタ
ーとなり、界面におけるキャリア空乏化を引き起こし、
コンタクト抵抗増大の原因になっている。また、再成長
でなく通常成長の場合でも、基板とエピ界面における不
純物の振る舞いが、デバイス特性を劣化させるという報
告もある（T.Yokoyama et al. IEEE Electron Device L
etters Vol.EDL-8, No.6, 1987, pp280-281）。そして
これらの不純物は、通常の成長前の６００℃程度の熱処
理では、除去できない。これらの不純物を除去するため
に、Ｎ．Ｋｏｎｄｏらは、水素を電子サイクロトロン共
鳴（Electron Cyclotron Resonance：ＥＣＲ）により活
性化させて基板に照射し、表面を清浄化する方法を試み
た（Japanese Journal of Applied Physics Vol.25, N
o.1, 1989, ppL7-L9）。また、Ｊ．Ｓａｉｔｏらは、分
子線エピタキシー法（ＭＢＥ）を用いた成長の前処理に
ＨＣｌガスによって、基板表面をエッチングして清浄化
を行った（Journal of Applied Physics Vol.67, No.1
0, 1990, pp6274-6280）。同様なＨＣｌガスによるエッ
チングは、ＭＯＶＰＥ法でも試みられている（K.Shimoy
ama et al.Journal of Crystal Growth Vol.107, 1991,
pp767-771）。[0003] However, in such a regrowth process, impurities such as carbon (C) and oxygen (O) remain at the interface. In the case of an n-type semiconductor, in particular, this becomes a killer center for electrons, and depletion of carriers at the interface occurs. Cause
This causes an increase in contact resistance. In addition, even in the case of normal growth rather than regrowth, there is a report that the behavior of impurities at the interface between the substrate and the epitaxy deteriorates device characteristics (T. Yokoyama et al. IEEE Electron Device L).
etters Vol.EDL-8, No.6, 1987, pp280-281). These impurities cannot be removed by ordinary heat treatment at about 600 ° C. before growth. To remove these impurities, N.I. Kondo et al. Tried a method of cleaning a surface by irradiating a substrate with hydrogen activated by electron cyclotron resonance (ECR) (Japanese Journal of Applied Physics Vol. 25, N
o.1, 1989, ppL7-L9). Also, J.I. Saito et al. Performed cleaning by etching the substrate surface with HCl gas for pretreatment for growth using molecular beam epitaxy (MBE) (Journal of Applied Physics Vol. 67, No. 1).
0, 1990, pp6274-6280). Similar etching with HCl gas has also been attempted in the MOVPE method (K. Shimoy.
ama et al. Journal of Crystal Growth Vol. 107, 1991,
pp767-771).
【０００４】[0004]
【発明が解決しようとする課題】以上述べたような従来
技術の方法には、次のような問題がある。ＥＣＲ法を用
いて水素を活性化させる方法は、５００℃以下で処理が
でき、ＣやＯの低減に効果があるが、Ｃを１０17ｃｍ-3
以下の濃度に下げることはできない。また基板がＧａＡ
ｓの場合、５００℃程度の処理温度になると、基板から
砒素が抜け始め、表面が平坦でなくなるという問題も生
じる。ＨＣｌガスを用いる方法も、Ｃ，Ｏ低減に効果が
あるが、これも完全ではなく、さらにこの場合、基板を
６００℃以上の高温にしなければエッチングができない
という問題がある。本発明の目的は、基板表面の平坦性
を損なわず、５００℃以下の低温処理でも完全に界面で
の不純物を除去することのできる表面処理方法とその装
置を提供することにある。The above-mentioned prior art methods have the following problems. The method of activating hydrogen using the ECR method can be performed at a temperature of 500 ° C. or less and is effective in reducing C and O. However, C is reduced to 10 17 cm −3.
It cannot be reduced to the following concentrations: The substrate is GaAs
In the case of s, at a processing temperature of about 500 ° C., arsenic starts to escape from the substrate, and there is a problem that the surface becomes uneven. The method using HCl gas is also effective in reducing C and O, but is not perfect, and in this case, there is a problem that etching cannot be performed unless the substrate is heated to a high temperature of 600 ° C. or more. SUMMARY OF THE INVENTION An object of the present invention is to provide a surface treatment method and apparatus capable of completely removing impurities at an interface even at a low temperature of 500 ° C. or less without impairing the flatness of the substrate surface.
【０００５】[0005]
【課題を解決するための手段】 本発明は、III―Ｖ族
化合物半導体表面のカーボンおよび酸素を除去する表面
処理方法において、加熱されたIII―Ｖ族化合物半導体
基板表面に活性化させた水素ガスもしくはハロゲン化水
素ガスと、熱的に解離させた砒素とを同時に供給するこ
とを特徴とするIII―Ｖ族化合物半導体の表面処理方法
である。Means for Solving the Problems The present invention relates to a surface treatment method for removing carbon and oxygen from the surface of a III-V compound semiconductor, wherein hydrogen gas activated on a heated III-V compound semiconductor substrate surface is provided. Or halogenated water
A surface treatment method for a group III-V compound semiconductor, characterized by simultaneously supplying an elemental gas and thermally dissociated arsenic.
【０００６】[0006]
【作用】本発明では、活性化させた水素とクラッキング
した砒素を基板表面に供給することにより、基板表面で
以下のような反応を起こさせる。According to the present invention, the following reaction is caused on the substrate surface by supplying activated hydrogen and cracked arsenic to the substrate surface.
【０００７】[0007]
【数１】 As2 + H* → 2AsHx … (1) C(ad) + 2H* → CH2(ad) … (2) AsHx + CH2(ad) → CH3(g)↑ … (3)[Equation 1] As 2 + H * → 2AsH x … (1) C (ad) + 2H * → CH 2 (ad)… (2) AsH x + CH 2 (ad) → CH 3 (g) ↑… ( 3)
【０００８】通常のＥＣＲによる水素処理と本発明の違
いは、(1)式に示すように、本発明ではAsHxを発生さ
せ、これをＣ除去に利用する点である。砒素をクラッキ
ングして基板に送るのは、このAsHxを生成しやすくする
ためである。本発明では、Ｈラジカルにより、表面に付
着しているカーボンの水素化物を形成し、それを(3)式
に示すようにAsHxと反応させて、脱離しやすいCH3にし
てしまうため、有効にＣを基板表面から除去することが
できる。またＯは、Ｈラジカルにより除去できる。な
お、(3)式の反応は５００℃程度で起きるので、ＨＣｌ
処理よりは低温で表面処理を行うことができる。しかも
砒素雰囲気中で処理することにより、基板からの砒素抜
けも防止できる。また、水素の代わりにＨＣｌのような
ハロゲン化水素ガスを用いれば、上記の効果の他に基板
をエッチングすることもできる。[0008] difference between hydrotreating and this invention by conventional ECR, as shown in equation (1), in the present invention to generate AsH x, a point for utilizing them C removed. Sending the substrate arsenic and cracking is to easily generate this AsH x. In the present invention, H radicals form hydrides of carbon attached to the surface, and react with AsH x as shown in formula (3) to form CH 3 which is easily desorbed. C can be removed from the substrate surface. O can be removed by H radicals. Since the reaction of the formula (3) occurs at about 500 ° C., HCl
The surface treatment can be performed at a lower temperature than the treatment. Moreover, by performing the treatment in an arsenic atmosphere, arsenic escape from the substrate can be prevented. Further, when a hydrogen halide gas such as HCl is used instead of hydrogen, the substrate can be etched in addition to the above effects.
【０００９】[0009]
【実施例】次に、本発明の一実施例について、図面を参
照して説明する。図１は、本実施例の表面処理装置の概
略構成図である。本実施例の処理装置は、高真空に保持
できる処理室１と、この処理室１に接続して備えられた
排気装置２と、基板７を保持する加熱機構の付設された
基板ホルダ３と、水素ガスを導入するガス導入口４と、
ガス導入口４に設けられた水素を活性化するためのＥＣ
Ｒ装置５と、砒素分子線をクラッキングして供給する砒
素クラッキングセル６によって構成されている。本実施
例では、本装置を通常のＭＢＥ成長室に接続し、ＧａＡ
ｓ基板に本装置による表面処理を行った後、ｎ型ＧａＡ
ｓをエピタキシャル成長させて、界面の評価を行った。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of the surface treatment apparatus of the present embodiment. The processing apparatus of this embodiment includes a processing chamber 1 capable of holding a high vacuum, an exhaust device 2 connected to the processing chamber 1, a substrate holder 3 provided with a heating mechanism for holding a substrate 7, A gas inlet 4 for introducing hydrogen gas,
EC for activating hydrogen provided at gas inlet 4
It comprises an R device 5 and an arsenic cracking cell 6 that cracks and supplies arsenic molecular beams. In this embodiment, the apparatus is connected to a normal MBE growth chamber,
After subjecting the s-substrate to the surface treatment by this apparatus, the n-type GaAs
s was epitaxially grown and the interface was evaluated.
【００１０】基板としては、１×１０18ｃｍ-3のＳｉを
ドープしたｎ型ＧａＡｓ基板を用いた。この基板上にＭ
ＢＥ法にて、Ｓｉドープ５×１０16ｃｍ-3のｎ型ＧａＡ
ｓを０．５μｍ成長させた後、一旦装置から取り出し、
数時間大気露出させ表面に不純物を付着させた。次に図
１に示す装置に基板をセットし、表面処理を行った後、
連続的にＭＢＥ法で、再びＳｉドープ５×１０16ｃｍ-3
のｎ型ＧａＡｓを０．５μｍ成長させた。表面処理の条
件は、水素圧：１×１０-4Ｔｏｒｒ、砒素圧：１×１０
-5Ｔｏｒｒ、処理時間：１０分、基板温度：５００℃で
ある。水素はＥＣＲ励起して基板に供給し、砒素は８０
０℃に加熱してクラッキングした。As the substrate, an n-type GaAs substrate doped with 1 × 10 18 cm −3 of Si was used. M on this substrate
By BE method, n-type GaAs doped with Si doped 5 × 10 16 cm -3
After growing s by 0.5 μm, once remove from the device,
Exposure to air for several hours allowed the impurities to adhere to the surface. Next, after setting the substrate in the apparatus shown in FIG. 1 and performing surface treatment,
Continuously with Si-doped 5 × 10 16 cm -3 by MBE method
Was grown to 0.5 μm. The conditions of the surface treatment were as follows: hydrogen pressure: 1 × 10 −4 Torr, arsenic pressure: 1 × 10 4
-5 Torr, processing time: 10 minutes, substrate temperature: 500 ° C. Hydrogen is ECR excited and supplied to the substrate, and arsenic is
Cracked by heating to 0 ° C.
【００１１】図２は、本実施例で作製した試料の深さ方
向のキャリア濃度分布を示す図である。測定法は、Ｃ−
Ｖ法による。従来技術による方法では、再成長界面近傍
においてキャリア濃度が減少しているのに対して、本発
明による方法では、キャリア濃度の減少はまったく見ら
れない。従って、良好な再成長界面が形成されているこ
とがわかる。またこの試料をＳＩＭＳ測定したところ、
Ｃ，Ｏは検出限界以下であり、有効に不純物が除去され
ていることが示された。さらに、水素ガスの代わりにＨ
ＣｌやＨＢｒなど水素原子を含むハロゲンガスを用いた
場合でも同様の効果が得られた。FIG. 2 is a diagram showing the carrier concentration distribution in the depth direction of the sample manufactured in this embodiment. The measurement method is C-
According to the V method. In the method according to the prior art, the carrier concentration decreases near the regrowth interface, whereas in the method according to the present invention, no decrease in the carrier concentration is observed. Therefore, it can be seen that a good regrowth interface is formed. When this sample was measured by SIMS,
C and O were below the detection limit, indicating that impurities were effectively removed. Further, instead of hydrogen gas, H
Similar effects were obtained when a halogen gas containing a hydrogen atom such as Cl or HBr was used.
【００１２】なお、処理条件は本実施例に限定されるも
のではなく、本発明範囲を逸脱しないものであれば、任
意であることは言うまでもない。また本実施例では、Ｇ
ａＡｓの処理について述べたが、他のIII−Ｖ族化合物
半導体についても同様の効果がある。処理装置について
も、水素を励起する方法、砒素をクラッキングする方法
は、その目的を満たすものであれば、どのような手段で
もかまわない。The processing conditions are not limited to the present embodiment, but may be arbitrary as long as they do not deviate from the scope of the present invention. In this embodiment, G
Although the processing of aAs has been described, similar effects can be obtained for other III-V compound semiconductors. Regarding the processing apparatus, any method may be used as a method for exciting hydrogen and a method for cracking arsenic as long as the purpose is satisfied.
【００１３】[0013]
【発明の効果】以上説明したように、本発明によれば、
清浄な基板／エピ界面、再成長界面を形成することがで
き、ひいてはデバイス特性を向上させる効果を有する。As described above, according to the present invention,
A clean substrate / epi interface and a regrowth interface can be formed, which has the effect of improving device characteristics.
【図１】本発明による表面処理装置の一実施例の概略構
成図である。FIG. 1 is a schematic configuration diagram of an embodiment of a surface treatment apparatus according to the present invention.
【図２】本発明の方法によって得られた試料の深さ方向
のキャリア濃度を従来技術による場合と比較して示す図
である。FIG. 2 is a diagram showing the carrier concentration in the depth direction of a sample obtained by the method of the present invention in comparison with the case of the conventional technique.
１ 処理室 ２ 排気装置 ３ 基板ホルダ ４ ガス導入口 ５ ＥＣＲ装置 ６ 砒素クラッキングセル ７ 基板 DESCRIPTION OF SYMBOLS 1 Processing chamber 2 Exhaust device 3 Substrate holder 4 Gas inlet 5 ECR device 6 Arsenic cracking cell 7 Substrate
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−18384（ＪＰ，Ａ) 特開 平４−26587（ＪＰ，Ａ) 特開 平１−301584（ＪＰ，Ａ) 特開 平２−153892（ＪＰ，Ａ) 特開 平６−224123（ＪＰ，Ａ) 特公 昭55−28544（ＪＰ，Ｂ２) ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-18384 (JP, A) JP-A-4-26587 (JP, A) JP-A-1-301584 (JP, A) JP-A-2-301 153892 (JP, A) JP-A-6-224123 (JP, A) JP-B-55-28544 (JP, B2)
Claims (1)
および酸素を除去する表面処理方法において、加熱され
たIII―Ｖ族化合物半導体基板表面に活性化させた水素
ガスもしくはハロゲン化水素ガスと、熱的に解離させた
砒素とを同時に供給することを特徴とするIII―Ｖ族化
合物半導体の表面処理方法。1. Carbon on the surface of a III-V compound semiconductor
And a surface treatment method for removing oxygen , wherein activated hydrogen gas or hydrogen halide gas and thermally dissociated arsenic are simultaneously supplied to a heated III-V compound semiconductor substrate surface. III-V compound semiconductor surface treatment method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06194809A JP3077876B2 (en) | 1994-07-27 | 1994-07-27 | Surface treatment method for III-V compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06194809A JP3077876B2 (en) | 1994-07-27 | 1994-07-27 | Surface treatment method for III-V compound semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0845842A JPH0845842A (en) | 1996-02-16 |
| JP3077876B2 true JP3077876B2 (en) | 2000-08-21 |
Family
ID=16330625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06194809A Expired - Lifetime JP3077876B2 (en) | 1994-07-27 | 1994-07-27 | Surface treatment method for III-V compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3077876B2 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5528544A (en) * | 1978-08-18 | 1980-02-29 | Matsushita Electric Ind Co Ltd | Auto-player |
| JPH01301584A (en) * | 1988-05-30 | 1989-12-05 | Nec Corp | Process for growing crystal and apparatus therefor |
| JPH0218384A (en) * | 1988-07-05 | 1990-01-22 | Fujitsu Ltd | Method for molecular beam epitaxial growth |
| JPH02153892A (en) * | 1988-12-06 | 1990-06-13 | Nec Corp | Process for molecular beam epitaxial growth |
| JP2840381B2 (en) * | 1990-05-18 | 1998-12-24 | シャープ株式会社 | (III)-Crystal growth method for group V compound semiconductor and crystal growth apparatus used in this method |
| JP3121945B2 (en) * | 1993-01-21 | 2001-01-09 | 富士通株式会社 | Semiconductor crystal growth method |
-
1994
- 1994-07-27 JP JP06194809A patent/JP3077876B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0845842A (en) | 1996-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3330218B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JPH09190979A (en) | Selective silicon epitaxial growth method and growth apparatus | |
| US5275687A (en) | Process for removing surface contaminants from III-V semiconductors | |
| JP2576766B2 (en) | Semiconductor substrate manufacturing method | |
| JP3077876B2 (en) | Surface treatment method for III-V compound semiconductor | |
| US5869398A (en) | Etching of indium phosphide materials for microelectronics fabrication | |
| JPH04146619A (en) | Thin film growth method | |
| KR910009409B1 (en) | Thermal etching treatment method and compound processing method of compound semiconductor substrate used for molecular beam epitaxy | |
| JP2699928B2 (en) | Pretreatment method for compound semiconductor substrate | |
| JPH09320967A (en) | Method for manufacturing compound semiconductor wafer | |
| JP2596027B2 (en) | Compound semiconductor crystal growth method and crystal growth apparatus | |
| US5248376A (en) | Process for thermal-etching treatment of compound semiconductor substrate used in molecular beam epitaxy and apparatus for performing same | |
| JP2917900B2 (en) | Method for surface treatment of III-V compound semiconductor substrate | |
| JP2639376B2 (en) | Method of growing III-V compound semiconductor | |
| JP3272531B2 (en) | Method for manufacturing compound semiconductor device | |
| JP3541324B2 (en) | Method for manufacturing semiconductor device | |
| JP2897107B2 (en) | Crystal growth method | |
| JPH0243720A (en) | Molecular beam epitaxial growth method | |
| JPH06101454B2 (en) | Vapor phase etching method for compound semiconductor | |
| JPH1012553A (en) | Compound semiconductor wafer and method of manufacturing the same | |
| JPH0587190B2 (en) | ||
| JPH0443631A (en) | Growth method of compound semiconductor crystal and equipment therefor | |
| JPH03131593A (en) | Preliminary treatment of substrate for epitaxial grow | |
| JPH01301584A (en) | Process for growing crystal and apparatus therefor | |
| JPH11106299A (en) | Compound semiconductor vapor deposition method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980519 |