JP3079532B2 - Semiconductor substrate manufacturing method - Google Patents
Semiconductor substrate manufacturing methodInfo
- Publication number
- JP3079532B2 JP3079532B2 JP01182004A JP18200489A JP3079532B2 JP 3079532 B2 JP3079532 B2 JP 3079532B2 JP 01182004 A JP01182004 A JP 01182004A JP 18200489 A JP18200489 A JP 18200489A JP 3079532 B2 JP3079532 B2 JP 3079532B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- substrate
- buried
- forming
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 74
- 229910052710 silicon Inorganic materials 0.000 claims description 74
- 239000010703 silicon Substances 0.000 claims description 74
- 238000005498 polishing Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 35
- 229910052814 silicon oxide Inorganic materials 0.000 description 35
- 239000013078 crystal Substances 0.000 description 33
- 238000000034 method Methods 0.000 description 25
- 239000010408 film Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 16
- 229910052760 oxygen Inorganic materials 0.000 description 14
- 239000001301 oxygen Substances 0.000 description 14
- 230000007547 defect Effects 0.000 description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- GLUUGHFHXGJENI-UHFFFAOYSA-N Piperazine Chemical compound C1CNCCN1 GLUUGHFHXGJENI-UHFFFAOYSA-N 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- -1 oxygen ion Chemical class 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板の製造方法に関し、特に絶縁膜物
上にシリコン（Si）単結晶層が形成されてなるSOI（Sil
icon On Insulator）基板の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to an SOI (Sil) having a silicon (Si) single crystal layer formed on an insulating film.
icon On Insulator) The present invention relates to a method for manufacturing a substrate.
今日の大規模集積回路（LSI:Large Scale Integratio
n）では、動作速度の高速化の要請から種々の改善がな
されているが、更に高速化を図るには寄生容量を大幅に
引き下げる技術が重要とされる。このような寄生容量の
低減には、絶縁物上にシリコン単結晶薄膜層を形成した
SOI基板の使用が有望と考えられており、これまでに種
々のSOI基板の製造方法に関する提案がなされている。Today's Large Scale Integratio (LSI)
In n), various improvements have been made in response to a demand for an increase in operation speed. However, in order to further increase the speed, a technique for significantly reducing the parasitic capacitance is important. In order to reduce such parasitic capacitance, a silicon single crystal thin film layer was formed on an insulator.
The use of SOI substrates is considered promising, and various methods for manufacturing SOI substrates have been proposed so far.
その１つとして、SIMOX（Separation by Implanted O
xygen）法がある。これは、シリコン単結晶基板の表面
から高加速で所定量の酸素（Ｏ）をイオン注入し、高温
熱処理によって注入された酸素とシリコンとを化学結合
させて埋込みシリコン酸化層とし、かつこのシリコン埋
込み酸化層の上側に残された層を薄いシリコン単結晶層
として素子形成領域に供するというものである（例えば
K.Izumi etal.Election.Lett.,Vol 14,p 593（1978））
参照。One of them is SIMOX (Separation by Implanted O
xygen) method. This is because a predetermined amount of oxygen (O) is ion-implanted from the surface of the silicon single crystal substrate at high acceleration, and the oxygen and silicon implanted by the high-temperature heat treatment are chemically bonded to form a buried silicon oxide layer. The layer left over the oxide layer is provided as a thin silicon single crystal layer to the element formation region (for example,
K. Izumi et al. Election. Lett., Vol 14, p 593 (1978))
reference.
このようなSIMXO法は、他のSOI基板の製造方法、例え
ば絶縁膜上に多結晶シリコン（或いは非晶質シリコン）
を堆積し、これを固相エピタキシャル成長して大径結晶
粒に育成する方法や、シリコン選択エピタキシャル成長
を応用して絶縁膜上にシリコン単結晶を成長する方法と
比較して、絶縁膜上に良質で大面積のシリコン単結晶を
容易に形成できることから、最も有望なSOI基板の製造
方法と考えられている。Such SIMXO method is a method for manufacturing other SOI substrates, for example, polycrystalline silicon (or amorphous silicon) on an insulating film.
Deposits and grows them into large-diameter crystal grains by solid phase epitaxial growth, or by using silicon selective epitaxial growth to grow a silicon single crystal on the insulating film. It is considered to be the most promising method for manufacturing an SOI substrate because a large-area silicon single crystal can be easily formed.
しかし、従来のSIMOX法は後に素子形成領域となるシ
リコン単結晶基板の表面を通して高加速で大用量の酸素
をイオン注入するため、イオン注入後の熱処理を経て
も、この素子形成領域におけるシリコン単結晶の結晶性
回復が不充分であり、埋込みシリコン酸化層の表面側及
び基板側の界面に多数の結晶欠陥が誘起される。この問
題は、イオン注入後の熱処理を1200℃程度以上に高温化
することで改善され、素子形成領域の結晶性回復と埋込
みシリコン酸化層の基板側界面の結晶欠陥消去は、充分
に達成される。しかしながら、素子形成領域の界面に生
じた結晶欠陥を完全に消去するには困難が多く、この問
題は解消されていない。（例えば吉野明他 電子情報通
信学会 技術研究報告,SDM87−39,p 73,1987年）。However, in the conventional SIMOX method, a large amount of oxygen is ion-implanted at a high acceleration through the surface of a silicon single crystal substrate which will later become an element formation region. Is insufficiently recovered, and a number of crystal defects are induced at the interface between the surface of the buried silicon oxide layer and the substrate. This problem is solved by increasing the temperature of the heat treatment after the ion implantation to about 1200 ° C. or more, and the recovery of the crystallinity of the element formation region and the elimination of the crystal defects at the substrate side interface of the buried silicon oxide layer are sufficiently achieved. . However, it is often difficult to completely eliminate crystal defects generated at the interface of the element formation region, and this problem has not been solved. (For example, Akira Yoshino et al. IEICE Technical Report, SDM 87-39, p. 73, 1987).
このような素子形成領域側の界面に生じた結晶欠陥
は、後に形成される素子のリーク特性劣化の原因とな
り、上述したSIMOX法の最大の問題点である。Such crystal defects generated at the interface on the element formation region side cause deterioration of leak characteristics of an element to be formed later, which is the biggest problem of the SIMOX method described above.
本発明はSIMOX法における上述した問題を解消した半
導体基板の製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor substrate which solves the above-mentioned problem in the SIMOX method.
本発明の半導体基板の製造方法は、シリコン基板の表
面側から凹部を形成する工程と、前記表面側からのイオ
ン注入により前記凹部底面の前記シリコン基板中に埋込
みシリコン絶縁層を形成する工程と、前記表面側から前
記凹部底面の周辺部に選択的にイオン注入して前記周辺
部に前記埋め込みシリコン絶縁層より前記シリコン基板
の裏面側に突出する厚い埋込みシリコン絶縁層を選択的
に形成する工程と、前記シリコン基板の裏面側を前記厚
い埋込みシリコン絶縁層が露呈されるまで研磨し、前記
埋込みシリコン絶縁層で絶縁された島状のシリコン領域
を形成する工程とを含んでいる。The method of manufacturing a semiconductor substrate according to the present invention includes a step of forming a recess from the front side of the silicon substrate, and a step of forming a buried silicon insulating layer in the silicon substrate at the bottom of the recess by ion implantation from the front side, Selectively forming a thick buried silicon insulating layer projecting from the front side to the peripheral portion of the bottom surface of the concave portion and projecting toward the back surface side of the silicon substrate from the buried silicon insulating layer in the peripheral portion; Polishing the back side of the silicon substrate until the thick buried silicon insulating layer is exposed, thereby forming island-shaped silicon regions insulated by the buried silicon insulating layer.
また、前記した厚い埋込シリコン絶縁層を形成する代
わりに、前記シリコン基板の裏面側から前記凹部の周辺
部に沿った箇所に前記埋込みシリコン絶縁層に達する溝
を形成する工程と、前記溝内にシリコン絶縁膜を埋設す
る工程を用いてもよい。A step of forming a groove reaching the buried silicon insulating layer at a location along the periphery of the concave portion from the back surface side of the silicon substrate instead of forming the thick buried silicon insulating layer; A step of burying a silicon insulating film in the substrate may be used.
更に、溝内へのシリコン絶縁膜の埋設に際しては、前
記シリコン基板の裏面側に形成した前記溝を含む全面に
シリコン絶縁膜を形成し、かつこれをエッチングバック
する方法が採用できる。Further, when the silicon insulating film is buried in the groove, a method of forming a silicon insulating film on the entire surface including the groove formed on the back surface side of the silicon substrate and etching back the silicon insulating film can be adopted.
この製造方法により製造される半導体基板は、酸素の
イオン入力によっても結晶欠陥が生じ難いシリコン単結
晶基板の裏面側を、素子形成用の主面としたSOI構成の
基板として構成される。The semiconductor substrate manufactured by this manufacturing method is configured as an SOI-structured substrate in which a back surface of a silicon single crystal substrate, in which crystal defects hardly occur even by oxygen ion input, is used as a main surface for element formation.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の第１実施例の初期
工程の状態を示す平面図及び縦断面図である。FIGS. 1 (a) and 1 (b) are a plan view and a longitudinal sectional view showing a state of an initial step of a first embodiment of the present invention.
先ず、両面を鏡面研磨した直径100mm,厚さ400μｍの
シリコン単結晶基板１（伝導型:P型，比抵抗：約1000Ω
・cm,面方位：〔100〕）に縦15mm,横15mm,深さ330μｍ
の凹部２を形成する。このとき、隣接する凹部２の間隔
は10mmとした。これら凹部２の形成に際しては、集積回
路の製造工程で広く用いられている光リソグラフィ技術
を応用し、感光樹脂もしくはシリコン酸化膜をマスクと
したドライエッチングを適用した。但し、凹部２の底部
の平坦性が損なわれないエッチング法であればいかなる
手法も適用可能である。First, a silicon single crystal substrate 1 having a diameter of 100 mm and a thickness of 400 μm, mirror-polished on both sides (conductivity type: P type, specific resistance: about 1000Ω)
・ Cm, plane orientation: [100]), length 15mm, width 15mm, depth 330μm
Is formed. At this time, the interval between the adjacent concave portions 2 was 10 mm. In forming these recesses 2, a photolithography technique widely used in an integrated circuit manufacturing process was applied, and dry etching using a photosensitive resin or a silicon oxide film as a mask was applied. However, any method can be applied as long as the etching method does not impair the flatness of the bottom of the concave portion 2.
以後の工程については、１つの凹部２について説明す
る。In the subsequent steps, one recess 2 will be described.
第１図のようにシリコン単結晶基板１の一主面上に凹
部２を形成した後、第２図（ａ）のように凹部２を設け
た基板１の主面の全面に加速エネルギー200KeV,用量1.5
×1018/cm2で第１の酸素イオン３の注入を行う。After forming a concave portion 2 on one main surface of a silicon single crystal substrate 1 as shown in FIG. 1, an acceleration energy of 200 KeV and an entire surface of the main surface of the substrate 1 having the concave portion 2 as shown in FIG. Dose 1.5
The first oxygen ions 3 are implanted at × 10 18 / cm 2 .
次に、第２図（ｂ）のように、凹部２の底面の周辺部
のみに加速エネルギー400KeV,用量１×1018/cm2で直径3
0μｍ程度に細く絞り込んだ酸素イオンビームで選択的
に第２の酸素イオン４の注入を行う。Next, as shown in FIG. 2 (b), only the periphery of the bottom surface of the recess 2 has an acceleration energy of 400 KeV, a dose of 1 × 10 18 / cm 2 and a diameter of 3
The second oxygen ions 4 are selectively implanted with an oxygen ion beam narrowed to about 0 μm.
これら第１及び第２の酸素イオン注入を行った後に、
1280℃３時間の熱処理を施すと、第２図（ｃ）のよう
に、凹部２の底面の下側領域に深さ約0.5μm,厚さ約0.1
5μｍの埋込みシリコン酸化層５が形成され、かつ底面
の周辺部に厚いシリコン酸化層からなるシリコン酸化微
小突起６が形成される。After performing these first and second oxygen ion implantations,
When a heat treatment at 1280 ° C. for 3 hours is performed, a depth of about 0.5 μm and a thickness of about 0.1 μm
A buried silicon oxide layer 5 of 5 μm is formed, and silicon oxide microprojections 6 made of a thick silicon oxide layer are formed on the periphery of the bottom surface.
なお、この状態においては、透過電子顕微鏡の観察に
よれば、埋込みシリコン酸化層５と表面側のシリコン層
との界面には、積層欠陥と双晶を中心とする結晶欠陥７
が多数残存することが確認された。しかし、埋込みシリ
コン酸化層５の反対側の界面には結晶欠陥は皆無であっ
た。In this state, according to observation with a transmission electron microscope, the interface between the buried silicon oxide layer 5 and the silicon layer on the surface side has a stacking fault and a crystal defect 7 centered on twins.
Was confirmed to remain in large numbers. However, there was no crystal defect at the interface on the opposite side of the buried silicon oxide layer 5.
また、シリコン酸化微小突起６は埋込みシリコン酸化
層５の下面から約0.5μｍ程度突き出して形成される。
これは、酸素のイオン注入における投影飛程が200KeVで
約0.5μm,400KeVで約1.0μｍであることに起因してお
り、シリコン酸化微小突起６が、埋込みシリコン酸化層
５よりも、投影飛程の差分に相当する約0.5μｍだけ突
き出た形で形成される。The silicon oxide microprojections 6 are formed so as to protrude from the lower surface of the buried silicon oxide layer 5 by about 0.5 μm.
This is because the projection range in oxygen ion implantation is about 0.5 μm at 200 KeV and about 1.0 μm at 400 KeV, and the silicon oxide microprojections 6 have a larger projection range than the buried silicon oxide layer 5. Is formed so as to protrude by about 0.5 μm corresponding to the difference of
次いで、第２図（ｄ）のように、シリコン単結晶基板
１を上下逆向きにした上で、基板１の裏面側をアルミナ
製の微細砥粒で約60μｍ程度研磨する。続いて、ピペラ
ジン（NH（CH2）4NH）によるシリコンの選択研磨技術
（浜口他，電子情報通信学会 技術研究報告,SSD86−6
3,p37,1986年）により仕上げ研磨を行った。ピペラジン
による選択研磨では、シリコン酸化物は研磨されないこ
とから、第２図（ｅ）のようにシリコン酸化微小突起６
がストッパーとなりシリコン酸化微小突起６の突き出し
分0.5μｍに等しい厚さのシリコン単結晶層が埋込みシ
リコン酸化層５の上層（基板１の下層）に形成され、こ
れが素子形成領域８となる。Next, as shown in FIG. 2 (d), the silicon single crystal substrate 1 is turned upside down, and the back surface of the substrate 1 is polished by about 60 μm with fine abrasive grains made of alumina. Then, selective polishing technology of silicon by piperazine (NH (CH 2 ) 4 NH) (Hamaguchi et al., IEICE Technical Report, SSD86-6)
3, p37, 1986). Since the silicon oxide is not polished by the selective polishing with piperazine, the silicon oxide microprojections 6 as shown in FIG.
Serves as a stopper, and a silicon single crystal layer having a thickness equal to the protrusion of the silicon oxide microprojections 6 equal to 0.5 μm is formed above the buried silicon oxide layer 5 (under the substrate 1), and this becomes the element formation region 8.
このように形成された素子形成領域を、同一規格のシ
リコン単結晶基板にSIMOX法で形成した素子形成領域と
をそれぞれ透過電子顕微鏡で観察した結果、SIMOX法の
ものでは界面から素子形成領域に向かって111面に沿っ
た積層欠陥と双晶が多数観察されたが、本実施例のもの
では結晶欠陥の存在は確認されなかった。As a result of observing the element formation region thus formed and the element formation region formed by the SIMOX method on a silicon single crystal substrate of the same standard with a transmission electron microscope, the SIMOX method is directed from the interface to the element formation region. Many stacking faults and twins were observed along the 111 plane, but the presence of crystal defects was not confirmed in this example.
なお、SIMOX法では、シリコン単結晶基板に200KeV,1.
5×1018/cm2での酸素のイオン注入を行い、1280℃,3時
間の熱処理を施して、埋込みシリコン酸化層及び素子形
成領域を形成している。In the SIMOX method, 200 KeV, 1.
Oxygen ions are implanted at 5 × 10 18 / cm 2 and heat treatment is performed at 1280 ° C. for 3 hours to form a buried silicon oxide layer and an element formation region.
第３図は本発明の第２実施例を工程順に示す縦断面図
である。FIG. 3 is a longitudinal sectional view showing a second embodiment of the present invention in the order of steps.
第３図（ａ）はシリコン単結晶基板１の一主面に縦15
mm,横15mm,深さ330μｍの凹部２を形成したものを示し
ている。なお、ここまでの工程については第１実施例の
第１図で説明したものと同様である。その上で、凹部２
が設けられた基板１の主面の全面に加速エネルギー200K
eV,用量1.5×1018/cm2で酸素イオン３の注入を行う。FIG. 3 (a) shows a vertical plane 15
The figure shows a recess 2 having a width of 15 mm, a width of 15 mm and a depth of 330 μm. The steps so far are the same as those described with reference to FIG. 1 of the first embodiment. Then, the recess 2
200K acceleration energy over the entire main surface of the substrate 1 provided with
Oxygen ions 3 are implanted at an eV and dose of 1.5 × 10 18 / cm 2 .
この後、1280℃３時間の熱処理を施すと、第３図
（ｂ）のように、凹部２の底面の下側領域に深さ約0.5
μm,厚さ0.15μｍの埋込みシリコン酸化層５が形成され
る。この時点では、埋込みシリコン酸化層５の表面側の
界面には多数の結晶欠陥７が残存し、反対側の裏面側の
界面には結晶欠陥のないことが透過電子顕微鏡で確認さ
れている。Thereafter, when a heat treatment at 1280 ° C. for 3 hours is performed, as shown in FIG.
A buried silicon oxide layer 5 having a thickness of 0.15 μm and a thickness of 0.15 μm is formed. At this time, it has been confirmed by a transmission electron microscope that many crystal defects 7 remain at the interface on the front surface side of the buried silicon oxide layer 5 and no crystal defects exist on the interface on the opposite back surface side.
続いて、第３図（ｃ）のように、基板を上下逆に向け
た上で、基板１の裏面をアルミナ製の微細砥粒で約60μ
ｍだけ研磨する。更に、第３図（ｄ）のように、凹部２
の底面周辺部に対応する位置の埋込みシリコン酸化層５
上の基板裏面に溝状の開口部９を開設する。Subsequently, as shown in FIG. 3 (c), the substrate is turned upside down, and the back surface of the substrate 1 is coated with alumina fine abrasive particles for about 60 μm.
Polish by m. Further, as shown in FIG.
Buried silicon oxide layer 5 at a position corresponding to the periphery of the bottom surface of
A groove-shaped opening 9 is formed on the back surface of the upper substrate.
次いで、第３図（ｅ）のように、基板１の裏面に化学
的気相成長法によりシリコン酸化膜10を堆積する。そし
て、第３図（ｆ）のように、このシリコン酸化膜10をエ
ッチングバックし、開口部９の底部にのみ厚さ0.6μｍ
程度にシリコン酸化膜10を残す。Next, as shown in FIG. 3E, a silicon oxide film 10 is deposited on the back surface of the substrate 1 by a chemical vapor deposition method. Then, as shown in FIG. 3 (f), the silicon oxide film 10 is etched back and only the bottom of the opening 9 has a thickness of 0.6 μm.
The silicon oxide film 10 is left to the extent.
しかる後、第１実施例と同様にピペラジンによるシリ
コン選択研磨により仕上げ研磨を行う。このとき、シリ
コン選択研磨のストッパーは第３図（ｆ）で示した開口
部９の底部に残されたシリコン酸化膜10であり、したが
って第３図（ｇ）で埋込みシリコン酸化層５上に形成さ
れるシリコン単結晶の素子形成領域８の厚さは0.6μｍ
となる。Thereafter, as in the first embodiment, finish polishing is performed by selective silicon polishing using piperazine. At this time, the stopper of the silicon selective polishing is the silicon oxide film 10 left at the bottom of the opening 9 shown in FIG. 3 (f), and thus formed on the buried silicon oxide layer 5 in FIG. 3 (g). The thickness of the silicon single crystal element forming region 8 is 0.6 μm.
Becomes
以上のように、第１及び第２実施例で製造したSOI基
板の素子形成領域にMOSダイオードを作製し、MOSc−ｔ
法により少数キャリアの生成寿命を測定したところ、い
づれの場合も1msec前後と良好な結果が得られた。これ
に対し、従来のSIMOX法で作製したSOI基板では少数キャ
リア生成寿命は１〜30μsecと非常に短く、埋込みシリ
コン酸化層界面から素子形成領域に延びている結晶欠陥
の影響が認められた。As described above, a MOS diode is manufactured in the element formation region of the SOI substrate manufactured in the first and second embodiments, and the MOSc-t
When the generation lifetime of the minority carrier was measured by the method, good results were obtained in all cases, about 1 msec. On the other hand, in the SOI substrate manufactured by the conventional SIMOX method, the minority carrier generation lifetime was extremely short, 1 to 30 μsec, and the effect of crystal defects extending from the buried silicon oxide layer interface to the element formation region was recognized.
なお、第１及び第２実施例では、共にシリコン単結晶
基板に形成する凹部の寸法を、縦15mm,横15mm,深さ330
μm,隣接凹部との距離を10mmとしたが、これはシリコン
単結晶基板の直径，厚さに依存するものであり、後の熱
処理工程或いは素子製造工程で機械的強度を維持できる
ものであれば、前記値に限定されるものではない。In the first and second embodiments, the dimensions of the recesses formed in the silicon single crystal substrate were 15 mm long, 15 mm wide and 330 cm deep.
μm, and the distance between adjacent recesses was 10 mm, but this depends on the diameter and thickness of the silicon single crystal substrate. If the mechanical strength can be maintained in the subsequent heat treatment process or device manufacturing process, , Are not limited to the above values.
また、最終の仕上げ研磨にはピペラジンによるシリコ
ン選択研磨を用いたが、充分な研磨精度が得られ、研磨
がシリコン酸化層領域に達したことを感度よく検知でき
る研磨法であれば、この選択研磨に限定されるものでは
ない。In addition, silicon selective polishing using piperazine was used for final polishing. However, if the polishing method can obtain sufficient polishing accuracy and can detect that polishing has reached the silicon oxide layer region with high sensitivity, this selective polishing can be used. However, the present invention is not limited to this.
また、前記各実施例はシリコン単結晶基板に酸素をイ
オン注入して埋込みシリコン酸化層を形成しているが、
窒素をイオン注入して埋込みシリコン窒化層を形成する
場合にも適用可能である。In each of the above embodiments, oxygen is ion-implanted into a silicon single crystal substrate to form a buried silicon oxide layer.
The present invention is also applicable to a case where a buried silicon nitride layer is formed by ion implantation of nitrogen.
以上説明したように本発明は、シリコン単結晶基板に
凹部を形成した上で、この凹部の底面下側に埋込みシリ
コン酸化層を形成し、この埋込みシリコン酸化層の下側
のシリコン単結晶基板を他と絶縁してこの領域を素子形
成領域として構成しているので、埋込みシリコン絶縁層
を形成する際に生じる結晶欠陥が素子形成領域に存在す
ることはなく、結晶性の良好な大面積のSOI基板を容易
に製造することができる。As described above, the present invention forms a recess in a silicon single crystal substrate, forms a buried silicon oxide layer below the bottom of the recess, and forms a silicon single crystal substrate below the buried silicon oxide layer. Since this region is insulated from the others and configured as an element formation region, there is no crystal defect generated in forming the buried silicon insulating layer in the element formation region, and a large-area SOI with good crystallinity The substrate can be easily manufactured.
また、本発明では埋込シリコン絶縁膜の周辺に厚い埋
込シリコン絶縁膜を形成する際にも表面側からのイオン
注入を行っているため、周辺部での結晶性も良好なもの
とすることができる。また、埋込シリコン絶縁膜の周辺
部にシリコン基板の裏面側から溝を形成する場合には、
凹部の周辺部に沿って形成すればよいため、凹部を利用
して溝を高精度に形成でき、埋込シリコン絶縁膜の周辺
に高精度に絶縁分離用のシリコン絶縁膜を形成すること
も可能となる。Also, in the present invention, when forming a thick buried silicon insulating film around the buried silicon insulating film, ions are implanted from the surface side, so that the crystallinity in the peripheral portion is also good. Can be. Also, when forming a groove in the peripheral portion of the buried silicon insulating film from the back side of the silicon substrate,
Since it is only necessary to form along the periphery of the concave part, the groove can be formed with high accuracy using the concave part, and the silicon insulating film for insulation separation can be formed with high precision around the embedded silicon insulating film Becomes
第１図（ａ）及び（ｂ）は本発明方法の初期工程を示す
基板全体の平面図及び縦断面図、第２図（ａ）乃至
（ｅ）は本発明の第１実施例の製造方法を工程順に示す
基板の一部の縦断面図、第３図（ａ）乃至（ｇ）は本発
明の第２実施例の製造方法を工程順に示す基板の一部の
縦断面図である。 １……シリコン単結晶基板、２……凹部、３……第１酸
素イオン注入、４……第２酸素イオン注入、５……埋込
みシリコン酸化層、６……シリコン酸化微小突起（厚い
埋込みシリコン酸化層）、７……結晶欠陥、８……素子
形成領域、９……溝（開口部）、10……シリコン酸化
膜。1 (a) and 1 (b) are a plan view and a longitudinal sectional view of an entire substrate showing initial steps of the method of the present invention, and FIGS. 2 (a) to 2 (e) show a manufacturing method of a first embodiment of the present invention. 3 (a) to 3 (g) are longitudinal sectional views of a part of the substrate showing the manufacturing method of the second embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1 ... Single-crystal silicon substrate, 2 ... Concave part 3 ... First oxygen ion implantation, 4 ... Second oxygen ion implantation, 5 ... Embedded silicon oxide layer, 6 ... Silicon oxide microprojection (thick embedded silicon Oxide layer), 7: crystal defect, 8: element formation region, 9: groove (opening), 10: silicon oxide film.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−225130（ＪＰ，Ａ) 特開 昭53−31983（ＪＰ，Ａ) 特開 昭60−94736（ＪＰ，Ａ) 特開 昭59−193044（ＪＰ，Ａ) 特開 昭63−2349（ＪＰ，Ａ) 特開 昭60−111437（ＪＰ，Ａ) 特開 昭63−58851（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/76 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-225130 (JP, A) JP-A-53-31983 (JP, A) JP-A-60-94736 (JP, A) JP-A-59-1983 193044 (JP, A) JP-A-63-2349 (JP, A) JP-A-60-1111437 (JP, A) JP-A-63-58851 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 21/76
Claims (3)
工程と、前記表面側からのイオン注入により前記凹部底
面の前記シリコン基板中に埋込みシリコン絶縁層を形成
する工程と、前記表面側から前記凹部底面の周辺部に選
択的にイオン注入して前記周辺部に前記埋め込みシリコ
ン絶縁層より前記シリコン基板の裏面側に突出する厚い
埋込みシリコン絶縁層を選択的に形成する工程と、前記
シリコン基板の裏面側を前記厚い埋込みシリコン絶縁層
が露呈されるまで研磨し、前記埋込みシリコン絶縁層で
絶縁された島状のシリコン領域を形成する工程とを含む
ことを特徴とする半導体基板の製造方法。A step of forming a recess from the front side of the silicon substrate; a step of forming a buried silicon insulating layer in the silicon substrate at the bottom of the recess by ion implantation from the front side; Selectively forming a thick buried silicon insulating layer protruding from the buried silicon insulating layer to the back side of the silicon substrate in the peripheral portion by selectively ion-implanting the peripheral portion of the bottom surface of the concave portion; Polishing the back surface until the thick buried silicon insulating layer is exposed to form island-shaped silicon regions insulated by the buried silicon insulating layer.
工程と、前記表面側からのイオン注入により前記凹部底
面の前記シリコン基板中に埋込みシリコン絶縁層を形成
する工程と、前記シリコン基板の裏面側から前記凹部の
周辺部に沿った箇所に前記埋込みシリコン絶縁層に達す
る溝を形成する工程と、前記溝内にシリコン絶縁膜を埋
設する工程と、前記シリコン基板の裏面側を研磨して前
記埋込みシリコン絶縁層及び前記埋設したシリコン絶縁
膜で絶縁された島状のシリコン領域を形成する工程とを
含むことを特徴とする半導体基板の製造方法。2. A step of forming a recess from the front side of the silicon substrate, a step of forming a buried silicon insulating layer in the silicon substrate at the bottom of the recess by ion implantation from the front side, and a back side of the silicon substrate. Forming a groove reaching the buried silicon insulating layer at a location along the periphery of the concave portion from the side, burying a silicon insulating film in the groove, polishing the back surface side of the silicon substrate, Forming a buried silicon insulating layer and an island-shaped silicon region insulated by the buried silicon insulating film.
溝を含む全面にシリコン絶縁膜を形成し、かつこれをエ
ッチングバックして溝内にのみ該シリコン絶縁膜を埋設
させてなる特許請求の範囲第２項記載の半導体基板の製
造方法。3. A silicon insulating film is formed on the entire surface including the groove formed on the back side of the silicon substrate, and the silicon insulating film is etched back to bury the silicon insulating film only in the groove. 3. The method of manufacturing a semiconductor substrate according to claim 2, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01182004A JP3079532B2 (en) | 1989-07-14 | 1989-07-14 | Semiconductor substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01182004A JP3079532B2 (en) | 1989-07-14 | 1989-07-14 | Semiconductor substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0346344A JPH0346344A (en) | 1991-02-27 |
| JP3079532B2 true JP3079532B2 (en) | 2000-08-21 |
Family
ID=16110639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01182004A Expired - Fee Related JP3079532B2 (en) | 1989-07-14 | 1989-07-14 | Semiconductor substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3079532B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5416348A (en) * | 1993-07-15 | 1995-05-16 | Micron Semiconductor, Inc. | Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing the floor of the trench |
| EP1852908A1 (en) * | 2000-05-03 | 2007-11-07 | Ibis Technology, Inc. | Implantation process using sub-stoichiometric, oxygen doses at diferent energies |
-
1989
- 1989-07-14 JP JP01182004A patent/JP3079532B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0346344A (en) | 1991-02-27 |
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