JP3079566B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

The present invention relates to a thin film transistor and a method of manufacturing the same, wherein the thin film transistor used in an active matrix type liquid crystal display device has a reduced leakage current between the source and drain electrodes and an active semiconductor layer, and the thin film transistor and an active matrix using the same. A contact layer connected to a source electrode and a drain electrode on a substrate and having a first impurity added thereto, with the object of improving the quality and reliability of the liquid crystal display panel. In a thin film transistor in which a working semiconductor layer is formed and a gate is formed on the working semiconductor layer with a gate insulating film interposed therebetween, a junction between the working semiconductor layer and the contact layer has a second impurity. Is added, and the second impurity is contained in the contact layer. The diffusion coefficient is larger than that of the first impurity and is added at a lower addition concentration, and the concentration gradient in the active semiconductor layer is higher on the contact layer side. Is configured.

In addition, a contact layer connected to each of the source electrode and the drain electrode and doped with the first impurity, and an operating semiconductor layer joined to the contact layer are formed on the substrate, and a gate is formed on the operating semiconductor layer. In the method for manufacturing a thin film transistor in which a gate is formed through an insulating film, a step of forming the contact layer, depositing a second impurity on a surface of the contact layer, and then forming the operating semiconductor layer In the method, the method for manufacturing a thin film transistor is configured so that the second impurity is diffused into the active semiconductor layer.

[Industrial applications]

The present invention relates to an improvement in a thin film transistor used for an active matrix type liquid crystal display device and a method for manufacturing the same.

In recent years, as liquid crystal display devices have been improved and spread, there has been a strong demand for large capacity and colorization. In particular, active matrix type liquid crystal display devices using thin film transistors as switching elements are expected to have excellent performance and quality, and are expected to meet a wide range of needs.
Improvements in quality stability and long-term reliability are strongly required.

[Conventional technology]

FIG. 7 is an external perspective view of an active matrix type liquid crystal display panel.

In the figure, 1 is an active matrix substrate which is a transparent substrate 11
A thin-film transistor element array is formed thereon, and each element is provided with a transparent pixel electrode corresponding to a display pixel. Reference numerals 40 and 50 denote a gate bus line and a drain bus line in which the gate electrode and the drain electrode of each thin film transistor are connected, and the alignment film 12 is provided thereon. On the other hand, 2 is a common electrode substrate and a transparent substrate 20.
A transparent solid electrode 21 and an alignment film 22 are formed on the substrate. Both substrates are hermetically sealed with a sealing material (not shown) sandwiching a spacer (not shown) so that a narrow space is formed with the alignment film surface in the middle, and the liquid crystal 3 is injected and sealed into the space. The active matrix type liquid crystal display panel is constituted by stopping. Note that this drawing shows a case for black and white display, but a color liquid crystal display panel is constituted by adding a color filter to this.

FIG. 8 is a diagram showing an example of the structure of a thin film transistor, and is a conceptual enlarged view of a part of the thin film transistor element group of the active matrix substrate 1 described in FIG.

In the figure, reference numeral 10 denotes a thin film transistor, which is a gate bus line 40.
An operating semiconductor layer 15, for example, an amorphous silicon film (α-Si) is formed on a gate electrode 14 extending from
A drain electrode connected to the drain bus line 50 from both sides thereof, for example, ITO (In ₂ O ₃ -SnO
A source electrode connected to the transparent pixel electrode 19 composed of ₂ ) is provided to form a thin film transistor. The operation mechanism is publicly known, and the description is omitted. Note that, in this drawing, an example of a so-called top gate stagger type in which the gate electrode 14 is arranged in the uppermost layer has been illustrated and described.

Conversely, the so-called bottom gate stagger type, in which the gate electrode 14 is arranged in the lowermost layer, is mainly mainly used practically at present because relatively stable characteristics can be obtained.

However, since the bottom gate stagger type has a complicated structure and the manufacturing process is difficult, improvement of a method of manufacturing a thin film transistor having a top gate stagger type structure is strongly demanded.

FIG. 9 is a view showing an example of manufacturing a conventional thin film transistor. FIGS. 9A, 9B, and 9C show examples of a top gate stagger type structure.

In the figure, 16 and 17 are contact layers, for example, n ⁺ Si layers, 9
A gate insulating film, for example, SiN _x film, the source and drain electrodes 4 and 5, 7 protective film, is 160, 170 is an ion implantation region.

The same parts as those described in the above drawings are denoted by the same reference numerals, and the description of the same parts will be omitted.

In FIG. 3A, the contact layers 16 and 17 and the active semiconductor layer 15 are shown.
And a so-called Abrupt junction is used to reduce the channel length. On the other hand, in FIGS. 2B and 2C, the contact layers 16 and 17 and the active semiconductor layer 1 are shown.
5, ion implantation regions 160 and 170 are provided so that an inclined junction is formed.

[Problems to be solved by the invention]

However, in the above conventional thin film transistor having a top gate stagger type structure, the Ab Ab in FIG.
When a rupt junction is formed, a leakage current at the time of OFF based on electric field concentration is likely to occur between the contact layers 16 and 17 and the operating semiconductor layer 15. On the other hand, the method of providing the ion implantation region shown in FIGS. 2B and 2C not only increases the resistance value between the channels and lowers the ON current, but also requires a long time for the ion implantation process and a large-screen liquid crystal display panel. There are many problems, such as not being suitable for the manufacture of, and the solution has been demanded.

[Means for solving the problem]

The above problem is solved by forming contact layers 16 and 17 connected to a source electrode and a drain electrode on a substrate 11 and joining the contact layers 16 and 17 to the operating semiconductor layer 1.
5, and a gate electrode on the gate electrode
This problem can be solved by a thin film transistor in which the second impurity concentration gradient is formed at the junction between the main surface and the side surfaces of the contact layers and the active semiconductor layer 15 in the thin film transistor in which 14 is formed. Further, a multi-function circuit including a high-speed element can be formed by forming the contact layers 16, 17 and the operating semiconductor layer 15 from polycrystalline silicon. Specifically, the concentration gradient of the impurity is
A second impurity different from the first impurity doped in the contact layers 16 and 17 is deposited on the contact layers 16 and 17 and then the active semiconductor layer 15 is laminated to form a thin film transistor. can do. Then, the first layers doped in the contact layers 16 and 17 are formed.
May be selected so as to have a higher concentration than the second impurity deposited thereon and to have a low diffusion coefficient in silicon.

Also, the method of manufacturing a thin film transistor may be such that the concentration gradient of the second impurity is formed by a change in the flow rate of a gas containing the first impurity to be doped during the vapor phase growth (CVD) of the contact layers 16 and 17. Even if it comprises, it can solve effectively.

[Action]

According to the present invention, the contact layer of the thin film transistor 10
Since the concentration gradient of the second impurity is formed at the junction between the main surface and the side surfaces 16 and 17 and the operation semiconductor layer 15, an energy barrier having a moderate inclination is formed to prevent electric field concentration. It is possible to prevent the occurrence of leakage current at the time of OFF.

Then, a second impurity different from the first impurity doped in the contact layers 16 and 17 is deposited on the contact layers 16 and 17 by a concentration gradient of the second impurity. Contact layers 16, 17
The formation of the first impurity which is doped so that the concentration is higher than that of the impurity to be deposited thereon and the diffusion coefficient in silicon is small is very easy. Further, the concentration gradient of the second impurity can be easily formed by changing the flow rate of the gas containing the second impurity to be doped during the vapor phase growth (CVD) of the contact layers 16 and 17.

〔Example〕

FIG. 1 is a view showing the structure of a thin film transistor according to the method of the present invention. In the figure, reference numeral 18 denotes a region having a second impurity concentration gradient.

The same parts as those described in the above drawings are denoted by the same reference numerals, and the description of the same parts will be omitted.

Principal and side surfaces of contact layers 16 and 17 and operating semiconductor 15
A region 18 having a concentration gradient of the second impurity is formed at the junction with the above, so that the energy band profile of the junction has an energy barrier having an appropriate gradient.

FIG. 2 is a schematic diagram showing an energy profile, as viewed on the YY axis in FIG. In the figure, [9]
The region of [15] is a gate insulating film 9, for example, an SiO ₂ film, and the region of [15] is an operating semiconductor layer 15, for example, a polycrystalline silicon layer, [1].
A region 8] represents a region 18 having a second impurity concentration gradient, for example, an As or P diffusion layer, and [17] represents a contact layer 17, for example, an As-doped polycrystalline silicon layer. Also,
E _C and E _V indicate conduction band and valence band levels, and E _F indicates Fermi level. The broken line indicates the conventional Abrupt junction [the ninth
The case of FIG. (A)] is shown for comparison.

The slope of the band profile observed at the junction between the contact layer 17 and the operating semiconductor layer 15, ie, the region [18] having the second impurity concentration gradient, is the solid line of the present invention in the case of the present invention. A moderate gradient is formed that is gentler than that of the broken line, and, for example, electric field concentration when the operation of the thin film transistor is turned off is prevented, and obstacles such as an increase in leak current can be removed. The same applies to the junction between the contact layer 16 and the operating semiconductor layer 15, and the description is omitted.

FIG. 3 is a view showing a method of one embodiment of the present invention, in which main steps are schematically illustrated in the order of steps.

Step (1): A 50 to 100 mm thick, for example, As-doped polycrystalline silicon film (doping amount of about 2 × 10 ² ) is mixed on a transparent substrate 11, for example, a glass substrate, by mixing SiH ₄ + AsH ₃ . Low pressure vapor phase epitaxy (CVD) is performed in a gas at 600 ° C., and contact layers 16 and 17 containing first impurities are formed as shown in the figure using a known photolithography technique.

Step (2): A first impurity doped into the contact layer, for example, a second impurity having a larger diffusion coefficient in silicon than As, for example, As, is doped on the main surfaces and side surfaces of the contact layers 16, 17 of the processing substrate. , P at a low concentration to form a second impurity layer 6. As a forming method, for example,
The substrate is heated to 400 ° C. and, for example, treated in a PH ₃ plasma of 10 ⁻¹ Torr to deposit a second impurity layer 6 made of a thin layer of phosphorus (P).

Step (3): An active semiconductor layer 15, for example, a 150 nm-thick non-doped polycrystalline silicon film is
Low pressure chemical vapor deposition (CVD) at 600 ° C in ₄ gases.
At this time, since the substrate 11 is heated to 600 ° C., As doped in the contact layers 16 and 17 and the contact layers 16 and 17 are doped.
P is thermally diffused to both sides of the interface between the contact layer and the operating semiconductor layer in accordance with the respective doping or the amount of deposition and the magnitude of the diffusion coefficient, and there is a concentration gradient of the second impurity. A region 18 is formed. Needless to say, the thermal diffusion treatment of the impurities may be performed separately if necessary.

Step (4): A gate insulating film 9, for example, a 200-nm-thick SiN _x film is formed on the operating semiconductor layer 15 of the processing substrate at a substrate temperature of 300.
After being formed by plasma CVD at a temperature of 100 ° C., a gate electrode 1 made of, for example, 200 nm thick Al
4 and, if necessary, a protective film (not shown) are formed, whereby the thin film transistor of the present invention is manufactured.

FIG. 4 is a diagram showing an example of a state in which an impurity concentration gradient is formed (part 1), in which the vertical axis represents the impurity concentration, the horizontal axis represents the distance in the depth direction,
That is, the distance from the interface between the substrate and the contact layer is set.

The first impurity (As) doped into the contact layer has a higher concentration than the second impurity (P) deposited on the main surface and side surfaces of the contact layer, and has a lower diffusion coefficient in silicon. Therefore, the respective impurity concentrations of As and P have a concentration profile as shown in the junction, and a moderate and moderate impurity concentration gradient is realized as shown by the dashed line. Note that the conventional As
It goes without saying that the state of the junction due to the single diffusion is the same as the broken line.

FIG. 5 is a view showing another embodiment of the present invention, in which main steps are schematically illustrated in the order of steps.

Step (1): thickness of a transparent substrate 11, for example, a glass substrate, on which P is doped as a second impurity, for example.
A 100-nm polycrystalline silicon film is grown so that the impurity concentration decreases toward the upper layer, and patterning is performed using a known photolithography technique to form contact layers 16 and 17. To form such a film specifically, at a substrate temperature of 600 ° C., the gas flow ratio PH ₃ / SiH ₄ is gradually changed from, for example, 2 × 10 ^-2 to 0, and a low-pressure gas phase is formed. What is necessary is just to grow (CVD).

Step (2): An active semiconductor layer 15, for example, a 150 nm-thick non-doped polycrystalline silicon film is
Low pressure chemical vapor deposition (CVD) at 600 ° C in ₄ gases.

Step (3): A gate insulating film 9, for example, a 200-nm-thick SiN _x film is formed on the operating semiconductor layer 15 of the processing substrate at a substrate temperature of 300.
After being formed by plasma CVD at a temperature of 100 ° C., a gate electrode 1 made of, for example, 200 nm thick Al
By forming 4 and, if necessary, forming a protective film (not shown), a thin film transistor according to another embodiment of the present invention is manufactured.

FIG. 6 is a diagram (part 2) showing an example of an impurity concentration gradient formation state, in which the vertical axis represents the impurity concentration, the horizontal axis represents the distance in the depth direction,
That is, the distance from the interface between the substrate and the contact layer is set.

As shown in the figure, a second impurity, for example, in a region above the contact layer, that is, in a region in contact with the active semiconductor layer 15,
Since a concentration gradient of P is formed and a so-called inclined junction is formed between the two, no leak current occurs even during the OFF operation.

In any of the above embodiments, the operating semiconductor layer 15
As such, non-doped polycrystalline silicon with high mobility was used so that it could be applied to high-speed transistors in peripheral circuits other than the switching element of the pixel electrode, but of course amorphous silicon may be used depending on the application. is there.

As a method of forming the working semiconductor layer 15 made of polycrystalline silicon, instead of directly forming polycrystalline silicon as in the above embodiment, first, an amorphous Si film is formed, and then thermal annealing is performed at 580 ° C. or more. Alternatively, polycrystallization may be performed by irradiating a laser beam.

〔The invention's effect〕

As described above, according to the present invention, since the concentration gradient of the second impurity is formed at the junction between the main surface and the side surfaces of the contact layers 16 and 17 of the thin film transistor 10 and the active semiconductor layer 15, a moderate An energy barrier having a slope is configured to prevent electric field concentration and, for example, to prevent generation of a leak current at the time of OFF.

Then, the concentration gradient of the impurity is
After depositing a second impurity different from the first impurity doped on the contact layers 16 and 17 on the contact layers 16 and 17,
The first impurity doped in the contact layers 16 and 17 has a higher concentration than the second impurity deposited thereon, and has a diffusion coefficient in silicon. Choosing it to be small greatly facilitates its formation. Further, the concentration gradient of the second impurity can be easily formed by changing the flow rate of the gas containing the second impurity to be doped during the vapor phase growth (CVD) of the contact layers 16 and 17.

Therefore, it greatly contributes to the improvement of the yield, quality, and reliability of the thin film transistor and the active matrix type liquid crystal display device using the thin film transistor, and to the reduction of the price.

[Brief description of the drawings]

1 is a diagram showing a structure of a thin film transistor according to the method of the present invention, FIG. 2 is a schematic diagram showing an energy profile, FIG. 3 is a diagram showing a method of one embodiment of the present invention, and FIG. FIG. 5 shows an example of a state (part 1), FIG. 5 shows a method of another embodiment of the present invention, FIG. 6 shows an example of an impurity concentration gradient forming state (part 2), FIG. Is a perspective view showing the appearance of an active matrix type liquid crystal display panel, FIG. 8 is a diagram showing a configuration example of a thin film transistor, and FIG. 9 is a diagram showing a configuration example of a conventional thin film transistor. In the figure, 1 is an active matrix substrate, 2 is a common electrode substrate, 3 is a liquid crystal, 4 is a source electrode, 5 is a drain electrode, 6 is a second impurity deposition layer, 7 is a protective film, and 9 is a gate insulating film. Reference numeral 10 denotes a thin film transistor, 11 denotes a substrate, 14 denotes a gate electrode, 15 denotes a working semiconductor layer, 16 and 17 denote contact layers, 18 denotes a region having a second impurity concentration gradient, and 19 denotes a pixel electrode.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-136373 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1 / 1368

Claims (2)

(57) [Claims] A contact layer connected to each of a source electrode and a drain electrode and having a first impurity added thereto; and an operating semiconductor layer bonded to the contact layer, the operating semiconductor layer being formed on the substrate. A thin film transistor having a gate formed thereon with a gate insulating film interposed therebetween, wherein a junction between the operating semiconductor layer and the contact layer is doped with a second impurity, and the second impurity is The first layer included in the contact layer
A thin film transistor, wherein the diffusion coefficient is larger than that of the impurity and is added at a low addition concentration, and the concentration gradient in the operating semiconductor layer is higher on the contact layer side. A contact layer connected to each of the source electrode and the drain electrode and having a first impurity added thereto; and an operating semiconductor layer bonded to the contact layer, the active semiconductor layer being formed on the substrate. In the method for manufacturing a thin film transistor having a gate formed thereon with a gate insulating film interposed therebetween, after forming the contact layer, a second impurity is deposited on a surface of the contact layer. A method for manufacturing a thin film transistor, comprising: diffusing the second impurity into the active semiconductor layer in the forming step.