JP3080064B2 - Drive circuit for plasma display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel driving circuit, and more particularly, to a plasma display panel (PDP).
And a display panel drive circuit having a function of recovering and reusing charge / discharge power of a display panel including capacitive light emitting cells.

[0002]

2. Description of the Related Art A power recovery circuit for recovering and reusing charge / discharge power to and from a display cell of a PDP is, in particular, a data IC.
(Data electrode driver) is configured to suppress power consumption and further compensate for the power consumption. Such recovery and reuse of charging / discharging power to and from the display cell is required in order to suppress the increase in power consumption due to the trend of energy saving in recent years, the higher definition of display images, and the higher brightness. I have.

To meet this demand, for example, Japanese Patent Application Laid-Open No. 9-146490 discloses a display panel drive circuit for recovering power of a power supply for supplying power to a data IC.

The technique disclosed in this prior art document collects and reuses charging / discharging power for a display cell individually and in parallel for each electrode, and supplies power not only during a sustain discharge period but also during a data writing period. It is intended to reduce. Hereinafter, this technique is referred to as a technique described in a gazette.

In this prior art, a series resonant LC circuit having a natural cycle substantially equal to a cycle of recovering a recovered current from an electrode of a PDP and reusing the recovered power is provided by a recovered power storage shared by a plurality of unit electrode drivers. It is provided as a part. Each unit electrode driver has first, second, third, and fourth switches. The recovery current flowing from the scan electrode or the data electrode is conducted to the recovery power storage unit by the first switch. Also, during the recovered power discharge period (sustain discharge period and data writing period), the recovered power is supplied from the recovered power storage unit to individual display electrodes or display cells via the second switch. The third switch and the fourth switch are configured to prevent the scan pulse or the data pulse from reaching the scan pulse level or the data pulse level, respectively, due to power consumption by the resistance component of the current path and power consumption by the data electrode and the scan electrode, or The scan electrodes or the data electrodes are connected to respective pulse voltage sources and base voltage sources to prevent the ground level (usually the ground level) from being reached.

The first advantage of the technology described in this publication is that an electrode driver is provided for each scanning electrode and each data electrode, and a switch is provided so that the power recovery operation and the power discharging operation can be simultaneously performed in each electrode driver. By controlling the open / close timing, power can be collected and reused not only during the sustain driving period but also during the display data writing period.

A second advantage of the technology described in this publication is that
The use of a single coil (resonant circuit coil) for a plurality of unit electrode drivers reduces the volume occupied by the coils even when the number of unit electrode drivers is large.

[0008]

In the technique described in the above publication, power can be recovered and reused not only in the sustain driving period but also in the display data writing period. When the value is indicated, it is effective for reducing the power consumption of the display electrode driver. However, the technique described in this publication has a problem in that performing the power recovery operation depending on the lighting rate of the display cell may consume power on the contrary.

For example, when the lighting rate of the display cell is particularly high,
That is, when the number of cells to be lit is large, the number of electrodes that take the high level state among the data electrodes of the data IC increases. In this state, when the data electrode in the high level state of the data IC transits to the low level state, a loss of a current collected from a large number of display cells occurs due to a circuit for performing a power recovery operation and the resistance of the data IC. Would. As for the output of the data IC, since the power loss is zero during the period when the data electrode maintains the high level, when the display rate is high, the power recovery circuit can be operated to increase the power consumption. Will be. In addition, when the display rate is low, the recovery circuit operates even if there is no power to be recovered, so that unnecessary power consumption occurs in the recovery circuit (see FIG. 5 described later).

SUMMARY OF THE INVENTION It is an object of the present invention to perform an inefficient power recovery operation when the display rate of a display panel is high and when the display rate is low, thereby efficiently recovering power without generating unnecessary power and recovering recovered power. An object of the present invention is to provide a PDP drive circuit that can be used.

[0011]

In order to achieve the above object, a first PDP driving circuit according to the present invention comprises an R, G, and B write circuit for writing to an addressed display cell of a PDP in synchronization with a clock signal. An address control circuit for outputting data, and R, G, and B data output from the address control circuit in synchronization with a clock signal are input, and the designated R, G, and B data are applied to the addressed data electrode. And a power recovery circuit that recovers the power of the discharge current when the display cell is discharged, and discharges the recovered power when the display cell is charged, and a power recovery circuit that recovers the power, and A drive circuit for a PDP, comprising: a timing control circuit for controlling a timing of releasing electric power; Calculate the total number of R, G, and B data having a logic level for lighting the indicated cell per unit time arbitrarily set, that is, the lighting rate of the display cell, and determine that the lighting rate of the display cell is higher than a predetermined upper limit. Or, when belonging to a first lighting rate region lower than a predetermined lower limit, outputs a collection control signal of a first logic level to the timing control circuit,
A lighting rate detection circuit that outputs a recovery control signal of a second logic level to the timing control circuit when the lighting rate belongs to the second lighting rate area that is equal to or greater than the lower limit value and equal to or less than the upper limit value; Controls the power recovery circuit when receiving the first logic level recovery control signal, disables power recovery or power release, and receives the second logic level recovery control signal when the second logic level recovery control signal is received. Controls the power recovery circuit to execute a power recovery operation and a power release operation.

A second PDP drive circuit according to the present invention inputs RGB data to be written to an addressed display cell of a plasma display panel in synchronization with a clock signal, and applies a designated data electrode to a designated data electrode. R, G, B
A data IC that receives data, a power recovery circuit that recovers power of a discharge current when the display cell is discharged, and a power recovery circuit that releases the recovered power when the display cell is charged; and a power recovery circuit that recovers power. And a timing control circuit for controlling the timing of discharging power, wherein the power consumption is detected by the data IC and the power recovery circuit, and the detected power consumption is set. When the detected power consumption is higher than the set reference value, the recovery control signal of the second logic level is output to the timing control circuit when the detected power consumption is higher than the set reference value. A power consumption detection circuit that outputs the
When the timing control circuit receives the first logic level recovery control signal, the timing control circuit controls the power recovery circuit to disable power recovery or power release, and receives the second logic level recovery control signal. In this case, the power recovery circuit is controlled to execute power recovery and power release.

As one embodiment of the power consumption detection circuit, the power consumption detection circuit is provided between the data IC and the power recovery circuit.
It is connected to a current path that collects and discharges power. In this case, the power consumption detection circuit detects a resistor connected in series with a current path between the data IC and the power recovery circuit for recovering and discharging power, and a voltage between both ends of the resistor for a predetermined time. An integration circuit that integrates the hit, and compares the integration result by the integration circuit with the predetermined reference value, and when the integration result is equal to or less than the predetermined reference value, outputs a first logic level collection control signal; When the integration result is higher than the predetermined reference value, a comparator that outputs a recovery control signal of a second logic level is provided.

[0014]

According to the first PDP drive circuit of the present invention, of the RGB data inputted to the data IC, the total number of RGB data having a display level per unit time,
That is, the lighting rate is determined, and when the lighting rate is higher than a predetermined upper limit (in the case where the lighting rate is 90% or more in FIG. 5 described later),
Alternatively, a case where the power recovery efficiency is low is lower than the predetermined lower limit (in FIG. 5, the case where the lighting rate is 10% or less), and power recovery by the power recovery circuit is suppressed. here,
The display level is a logical level for controlling the data electrode voltage so as to generate plasma in the display cell (turn on the display cell).

The second PDP drive circuit of the present invention directly detects the power consumption by the data IC and the power recovery circuit, and when the power consumption is equal to or less than a set reference value (FIG. (When the relative value is 10% or less), the power recovery by the power recovery circuit is suppressed.

The detection of power consumption by the above-described embodiment of the second PDP drive circuit is based on the following principle. If data I
If there is no power consumption by C and the power recovery circuit, a pulse of the set voltage level should be applied to the data electrode when the power recovered by the power recovery circuit is reused for lighting. Then, in this case, the current (recovered current) recovered from the data IC to the power recovery circuit
And the current (emission current) emitted from the power recovery circuit to the data IC during lighting is equal and opposite.
Therefore, when this current is passed through the resistor and the voltage across the resistor is integrated over a period of an integer period, the integration result becomes zero.

However, since power is normally consumed by the data IC and the power recovery circuit, when the power recovered by the power recovery circuit is reused for lighting, the pulse level applied to the data electrode is a predetermined voltage. Does not reach level. Therefore, in order to apply a pulse of a set level to the data electrode, usually, a period during which a current is discharged from the power recovery circuit to the data IC (a period during which the display cell is charged), that is, at the end of the charging period, The electrodes are connected to a compensation power supply (clamp power supply) to compensate for the lack of pulse level due to power consumption. As a result, the voltage across the resistor causes an imbalance between the recovery period and the charging period by the amount of power compensated by the compensation power supply.
Therefore, when this voltage is integrated over a predetermined period, a non-zero integrated value is obtained. This integral value is the data I
This corresponds to power loss due to C and the power recovery circuit.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the PDP drive circuit of the present invention. The PDP drive circuit of the present embodiment includes an address control circuit 1,
Data IC 2, recovery circuit 3, timing control circuit 4, display cell lighting rate detection circuit (hereinafter referred to as lighting rate detection circuit)
5 is provided.

The address control circuit 1 outputs RGB data to be written to an addressed display cell (not shown) of the PDP in synchronization with a clock signal. The data IC 2 receives the RGB data output from the address control circuit 1 in synchronization with the clock signal, and applies the specified RGB data to the data electrode of the specified address.
Apply B data. The lighting rate detection circuit 5 is a data IC
2, the total number of high-level data (logic-level control signals that specify the plasma state of the display cell) per unit time arbitrarily set, that is, lighting of the display cell When the lighting rate of the display cell is equal to or more than a predetermined upper limit and equal to or less than a predetermined lower limit, a non-operating state of the collection circuit 3 is designated. A collection control signal Srec for designating a state is output.

The timing control circuit 4 inputs a clock and a recovery control signal Srec, and the recovery control signal Srec designates a first inactive state of the recovery / release operation in the recovery circuit 3.
, The control signals Sw1 and Sw2 for controlling the power release operation of the recovery circuit 3 and the timing of the power recovery operation (the period of the power release operation and the power recovery operation) are made inactive, and the recovery circuit 3 makes the data IC2 The control signal Sw3 for controlling the timing of supplying the power supply voltage to the data electrode is activated. The timing control circuit 4 activates the control signals Sw1, Sw2 and the control signal Sw3 when the collection control signal Srec is at the second logical level designating the operation state of the collection circuit 3.

The recovery circuit 3 recovers and accumulates the discharge current from the display cell when the data electrode changes from high level to low level when the control signal Sw2 is activated. The recovery circuit 3 discharges the stored recovered power to the display cell when the data electrode changes from the low level to the high level when the control signal Sw1 is activated. When the control signal Sw3 is activated, the recovery circuit 3 connects the data electrode to a voltage source that provides a predetermined pulse level or a predetermined base level to the data electrode at a predetermined timing. Therefore, the recovery circuit 3
When the lighting rate of the display cell is higher than a predetermined upper limit, and when lower than a predetermined lower limit, the recovery / discharge operation of the recovery circuit is in an inactive state, and the lighting rate is equal to or higher than the lower limit and equal to or lower than the upper limit. At times, the recovery / release operation of the recovery circuit is activated.

The lighting rate detection circuit 5 includes a lighting rate calculating section 6 and a lighting rate determining section 7. The lighting rate calculation unit 6 includes BR, R,
G data is input, and a high-level (control signal level for lighting a display cell) B, R,
The total number of G data is calculated, and the calculation result is output as the lighting rate. For this purpose, the lighting rate calculation unit 6 includes a display signal detection circuit 8, a counter 9, and an adder 10. The display signal detection circuit 8 receives the B, R, and G data, detects the logical level of the data for each color in synchronization with a clock, and outputs a pulse when a high level is detected. The counter 9 counts the pulses of each color of the display signal detection circuit 8. The adder 10 adds the number of pulses for each color counted by the counter 9 for a predetermined unit time and outputs the result as a lighting rate.

The lighting rate judging section 7 inputs the lighting rate output from the lighting rate calculating section 6 and sets the maximum value ma at which the lighting rate is set.
When the lighting rate is higher than x or lower than the set minimum value min, the recovery control signal Srec of the first logical level is output. When the lighting rate is higher than the minimum value min and lower than the maximum value max, the second logical level is output. Is output.
The lighting rate determination unit 7 includes comparators 11 and 12, and an OR gate 13. The maximum value max is connected to the inverting input terminal of the comparator 11, and the minimum value min is connected to the non-inverting input terminal of the comparator 12. The lighting rate calculated by the lighting rate calculator 6 is input to the non-inverting input terminal of the comparator 11 and the inverting input terminal of the comparator 12. In the present embodiment, the first logic level of the collection control signal Srec is high and the second logic level is low.

FIG. 2 is a configuration diagram of the display signal detection circuit 8 of the present embodiment. The display signal detection circuit 8 of the present embodiment
-It is composed of a D flip-flop (DF / F) for inputting RGB data for each color. The same clock as the clock input to the address control circuit 1 is input to the clock input terminal of the DF / F. The Q output is input to the counter 9.

FIG. 3 is a circuit diagram of the recovery circuit 3 of the present embodiment. The recovery circuit 3 includes a switch SW1 and a diode 41 for preventing reverse current of the current, a switch SW2 and a diode 42 for preventing reverse current, and a switch SW for connecting the data IC to a voltage clamping power supply for applying a predetermined voltage to the data electrode.
3. It has a capacitor C and a coil L for storing the recovered power. The capacitance C and the coil L substantially constitute a series resonance circuit, and the resonance cycle is set to be substantially equal to the cycle of charging / discharging the display cell. The resistance R in the figure is the effective resistance of the data IC and the current path of the recovery current and the emission current, and the PDP drive circuit causes power loss due to this resistance.

The control signals Sw1, Sw2, Sw3 in FIG. 1 control the opening and closing of the switches SW1, SW2, SW3 in FIG. 3, respectively. When the collection control signal Srec is at a high level, at least one of the switches SW1 and SW2 is in an off state, the states of SW1 and SW2 are fixed, and the switch 3 is fixed in an on state. Therefore, R, G, B
Although the data is input to the display matrix from the data IC, the collection operation is inactive. As a result, unnecessary collection operation is not performed, and power consumption can be reduced.

FIG. 4 is a timing chart showing the operation of the switches SW1, SW2 and SW3 when the collection control signal Srec is at a low level. First, the period from the left end of the figure will be described. During this period, the switch SW1 transitions from on to off, and the release of the recovered power to the next display cell to be lit (charging of the next display cell) ends. However, due to the resistance loss of the current path and the power loss of the data IC, the voltage level of the data electrode that drives the display cell cannot reach a predetermined value only by the recovered power that is released. Therefore, the switch SW3 is turned on to connect the power supply for clamping and the data electrode, thereby compensating for the insufficient voltage level. During this time, when the voltage between the data electrode and the scan electrode of the display cell reaches the discharge threshold, discharge (lighting) of the display cell is started. The period when the switch SW3 is on is called a clamp period.

When the clamp period ends, the switch SW
2 turns on, and the collection period T1 starts. At this time, due to the self-induction of the coil L, the collection current is not immediately accumulated in the capacitor C even when the collection period starts. However, since the series resonance cycle of the coil L and the capacitor C is set substantially equal to the recovery period, the recovery of the discharge current from the display cell almost ends during this recovery period.

Next, the switch SW1 is turned on, and a charging period (a period for charging the display cell) T2 is started. In this embodiment, in order to perform power recovery and release in the LC resonance cycle, during this period, the switch SW1 and the switch SW2
And both are turned on. (The reason why the switch SW2 of the recovery current circuit and the switch SW1 of the charging current circuit (the circuit of the emission current from the capacitor C) are made conductive at the same time is as follows. Is not an independent current, but an oscillating current of the LC series resonance circuit.After the recovery current flowing toward the capacitor C is accumulated in the capacitor C, the recovery period is released from the capacitor C and becomes a charging current. This is because, in order to end and start the charging period, it is necessary to make both the recovery current circuit and the charging current circuit conductive for a certain time width near the turning point.) Next, the switch SW2 Is turned off, the switch SW3 is turned on to start the clamp period. When the collection control signal Srec is at the low level, the collection circuit repeats the above operation.

The operation of this embodiment will be described below. The R, G, and B data signals from the address control circuit 1 and the clock for each cell are supplied to the display signal detection circuit 8.
When the input signal is at a high level (in the case of a display signal), the display signal detection circuit 8 outputs a high level. This output signal is sent to the counter 9 where the number of high-level data signals is counted. The counting result is sent to the adder 10 and the high level data of the three colors R, G, B is added. Next, the lighting rate determination unit 7 determines that the calculated lighting rate is lower than the reference lighting rate (display rate) or higher than the reference lighting rate. When the lighting rate is lower than the reference lighting rate (display rate) or higher than the reference lighting rate, the recovery efficiency is low even when the power is recovered. The collection operation is suppressed.

FIG. 5 shows the data I for the display rate (lighting rate).
9 is a graph illustrating an example of a relative power consumption value of C. In the figure, when there is no power recovery, the power consumption increases in proportion to the display rate up to the display rate of about 50%. When the display ratio exceeds about 50%, the power consumption decreases linearly this time. When the display ratio is large, the reason why the power consumption decreases with the increase in the display ratio is that, as described above, when the display ratio is large, the time during which the data electrode maintains the high level on average is long, and the data electrode is at the high level. This is because the loss of the output of the data IC is zero during the period in which is maintained.

In the example of FIG. 5, the display ratio is about 10% to about 9%.
When power recovery is performed up to 0%, the power consumption is much smaller than when power recovery is not performed, but both power consumption curves intersect at display rates of about 10% and about 90%. When the display rate is 10% or less and 90% or more, it is understood that the power consumption is smaller when the power recovery is not performed. Therefore, in the example of this figure, if the display rate is set to 10% as the lower limit value MIN of the display rate for performing power recovery, and 90% is set to the upper limit value MAX of the display rate for performing power recovery, efficient power recovery is performed. Can be achieved.

FIG. 6 shows a second embodiment of the PDP drive circuit according to the present invention.
FIG. 3 is a circuit diagram showing the embodiment. The PDP drive circuit of the present embodiment includes a data IC 62, a recovery circuit 63, a timing control circuit 64, and a power consumption detection circuit 65. Among them, the data IC 62, the recovery circuit 63, and the timing control circuit 64 are the same as the data IC 2, the recovery circuit 3, and the timing control circuit 4 of FIG. 1, but the power consumption detection circuit 65 that generates the recovery control signal This is different from the lighting rate detection circuit 5 of the first embodiment.

The power consumption detection circuit is connected to a current path between the data IC 62 and the recovery circuit 63 for recovering and discharging power, and detects power consumed by the data IC 62 and the recovery circuit 63 to detect the power consumption. When the detected power consumption is equal to or less than the set reference value, the recovery control signal Srec of the first logic level is output to the timing control circuit 64. When the detected power consumption is higher than the set reference value, the second control signal Srec is output. A recovery control signal Srec of a logic level is output to the timing control circuit 64.

When the timing control circuit receives the recovery control signal of the first logic level, it controls the recovery circuit 63 to disable power recovery or power release, and to recover the second logic level. When the control signal is received, the control of the power recovery circuit to recover the power and release the power is the same as in the first embodiment.

The power consumption detecting circuit 65 includes a resistor 66, an integrating circuit 67, a differential amplifier 68, and a comparator 69. The resistor 66 is connected in series to a current path between the data IC 62 and the recovery circuit 63 for recovering and discharging power. The integration circuit 67 integrates the voltage between both ends of the resistor 66 per predetermined time. The differential amplifier 68 amplifies the result of integration by the integration circuit. The comparator 69 compares the output of the differential amplifier 68 with a predetermined reference value VR. If the comparison result is equal to or smaller than the reference value VR, the comparator 69 outputs a first logic level recovery control signal Srec. If the value is higher than the value VR, the second logic level recovery control signal Srec
Is output. In the present embodiment, the comparator 69
The output of the differential amplifier 68 is connected to the inverting input terminal of
The reference value VR is connected to a non-inverting input terminal of the comparator 69. Therefore, the first of the collection control signal Srec
Is a high level, and the second logic level is a low level.

Next, the operation of this embodiment will be described. First, when the power consumption by the data IC and the recovery circuit is very small and almost zero, when the power recovered by the recovery circuit 63 is reused for lighting, it is set to the data electrode. A voltage level pulse is applied.
In this case, the current (collection current) collected by the collection circuit 63 from the data IC 62 and the collection circuit 63 for lighting.
The current (emission current) emitted from the data IC 62 to the data IC 62 is equal in magnitude and opposite. Therefore, when the voltage generated across the resistor 66 due to this current is integrated over a period of an integer period, the integration result becomes substantially zero. When the power consumption by the data IC 62 and the recovery circuit 63 is large, when the power recovered by the recovery circuit is reused for lighting, the pulse applied to the data electrode does not reach a predetermined pulse level. Therefore, in order to apply a pulse of the set voltage level to the data electrode, a period during which a current is discharged from the recovery circuit 63 to the data IC 62 (a period during which the display cell is charged), that is, a period shown in FIG. At the end of the charging period T2, the data electrode is connected to a compensation power supply (clamp power supply, a power supply connected to the switch SW3 in FIGS. 3 and 6) to compensate for the shortage of the pulse level due to power consumption (FIG. 4 clamp period T
3). Therefore, the voltage across the resistor 66 causes an imbalance between the recovery period and the charging period by the amount of power provided by the compensation power supply. As a result, when this voltage is integrated over a predetermined period, a non-zero integrated value is obtained.
This integrated value corresponds to the power loss caused by the data IC 62 and the recovery circuit 63.

In the embodiment of FIG. 6, when the voltage corresponding to the power consumption relative value of 10% is used as the reference value VR, the power consumption is particularly low (the display rate of FIG.
(Or not less than MAX), the recovery circuit 63 is not operated.
In this way, it is possible to constantly monitor the power consumption and suppress unnecessary power consumption caused by unnecessary charging and discharging due to the operation of the recovery circuit.

[0039]

As described above, the present invention has the following effects. By providing a lighting rate detection circuit and constantly monitoring the lighting rate of the display cell, when the display rate of the display panel is high and when the display rate of the display panel is low, an inefficient power recovery operation is performed and unnecessary power is not generated. It is possible to efficiently recover power and reuse recovered power. By providing a power consumption detection circuit and constantly monitoring the power consumption of the data IC and the power recovery circuit, an inefficient power recovery operation is performed when the power consumption is small, and the power consumption is not generated and the power consumption is reduced. It is possible to recover power and reuse recovered power.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a PDP drive circuit according to the present invention.

FIG. 2 is a configuration diagram of a display signal detection circuit according to the first embodiment.

FIG. 3 is a circuit diagram of a recovery circuit according to the first embodiment.

FIG. 4 is a timing chart showing the operation of switches SW1, SW2, and SW3 when the recovery control signal Srec is at a low level.

FIG. 5 is a graph showing an example of a relative value of power consumption of a data IC with respect to a display rate (lighting rate).

FIG. 6 is a circuit diagram showing a second embodiment of the PDP drive circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address control circuit 2, 62 Data IC 3, 63 Recovery circuit 4, 64 Timing control circuit 5 Lighting rate detection circuit 6 Lighting rate calculation part 7 Lighting rate judgment part 8 Display signal detection circuit 9 Counter 10 Adder 11, 12 Comparator 13 OR circuit 21 Flip-flop circuit 41, 42 Backflow preventing diode 65 Power consumption detecting circuit 66 Resistor 67 Integrating circuit 68 Differential amplifier 69 Comparator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/28 G09G 3/20

Claims (7)

(57) [Claims] 1. An address control circuit for outputting R, G, and B data to be written to an addressed display cell of a plasma display panel in synchronization with a clock signal, and an output from the address control circuit in synchronization with a clock signal. A data IC receiving the specified R, G, and B data at the data electrode addressed by inputting the R, G, and B data, and recovering the power of the discharge current when the display cell discharges. A power recovery circuit that releases recovered power when a display cell is charged; and a timing control circuit that controls the timing at which the power recovery circuit recovers power and discharges power. , R, G, B data are input, and the display level, that is, the logical level for lighting the display cell Calculates the total number of the R, G, and B data per unit time, that is, the lighting rate of the display cell, and determines whether the lighting rate of the display cell is higher than a predetermined upper limit or lower than a predetermined lower limit. When belonging to the first lighting rate region, a recovery control signal of the first logic level is output to the timing control circuit, and when the lighting ratio belongs to the second lighting rate region equal to or more than the lower limit value and equal to or less than the upper limit value, A lighting rate detection circuit that outputs a recovery control signal of a second logic level to a timing control circuit, wherein the timing control circuit controls the power recovery circuit when a recovery control signal of a first logic level is received. And controlling the power recovery circuit to perform the power recovery operation and the power release operation when the recovery control signal of the second logic level is received. To Characteristic plasma display panel driving device. 2. The lighting rate detection circuit according to claim 1, wherein
A lighting rate calculation unit that inputs data and calculates a lighting rate; and determines whether the lighting rate belongs to the first lighting rate area or the second lighting rate area, and determines whether the lighting rate belongs to the first lighting rate area. When it belongs to the lighting rate region, a recovery control signal of the first logic level is output to the timing control circuit, and
2. The apparatus according to claim 1, further comprising: a lighting rate determination unit that outputs a recovery control signal of a second logic level to the timing control circuit when the timing control circuit belongs to a lighting rate area of the second type. 3. A display signal detection circuit which receives RGB data and outputs a display pulse when detecting the RGB data having the display level, wherein the display signal detection circuit outputs the display pulse. 3. The apparatus according to claim 2, further comprising a counter for counting pulses, and an adder for calculating a total number of display pulses of all colors per predetermined time from an output of the counter. A first comparator for comparing a total number of display pulses output from the adder with the predetermined upper limit, and a lighting comparator for determining a total number of display pulses output from the adder; 3. The apparatus according to claim 2, further comprising a second comparator for comparing with a predetermined lower limit value, and a gate circuit for receiving outputs of the first and second comparators and outputting the collection control signal. 5. The apparatus according to claim 3, wherein said display signal detection circuit is a D flip-flop. 6. A data electrode designated by inputting RGB data to be written to an addressed display cell of a plasma display panel in synchronization with a clock signal.
A data IC for receiving designated RGB data;
When the display cell discharges, recovers the power of the discharge current, and when the display cell is charged, a power recovery circuit that releases the recovered power, and the power recovery circuit recovers the power,
And a timing control circuit for controlling the timing of discharging power, wherein the power consumed by the data IC and the power recovery circuit is detected, and the detected power consumption is set. When the detected power consumption is higher than the set reference value, the recovery control signal of the second logic level is output to the timing control circuit when the detected power consumption is higher than the set reference value. Having a power consumption detection circuit for outputting, the timing control circuit controls the power recovery circuit when receiving a recovery control signal of the first logic level to disable power recovery or power release. When the recovery control signal of the second logic level is received, the power recovery circuit is controlled to perform power recovery and power release. An apparatus for driving a plasma display panel, characterized in that to. 7. The power consumption detecting circuit is connected to a current path for recovering and discharging power between the data IC and the power recovery circuit, and the power consumption detection circuit is connected to the data IC and the power recovery circuit. A resistor connected in series to a current path for collecting and discharging power, an integrating circuit for integrating a voltage between both ends of the resistor per a predetermined time, and an integration result obtained by the integration circuit as the predetermined reference value. And outputs a recovery control signal of a first logic level when the integration result is equal to or less than the predetermined reference value, and outputs a second logic level when the integration result is higher than the predetermined reference value. The apparatus according to claim 6, further comprising a comparator that outputs a recovery control signal of the control signal.