JP3080223B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, it relates to a semiconductor device having a semiconductor resistance element (diffusion resistance).

[0002]

2. Description of the Related Art As shown in FIG. 12, a conventional semiconductor resistance element has a second conductivity type diffusion layer 1 formed in a first conductivity type semiconductor region 6, and this second conductivity type diffusion layer is used as a resistance element. Was to be used. Many of the shapes are rectangular layout patterns or combinations of rectangular layout patterns. Electrodes 2 and 3 that are in ohmic contact with the diffusion layer 1 are formed at both ends of the second conductivity type diffusion layer 1 which is a semiconductor resistance element. In order to prevent a current from flowing between the second conductivity type diffusion layer 1 and the first conductivity type semiconductor region 6, the voltage is used in a voltage range in which the two regions are in a reverse bias state.

The parameters that determine the resistance value of a semiconductor resistance element are the density and mobility of carriers moving in the resistance element and the shape of the resistance element. Therefore, the resistance value of the resistance element is determined by the impurity concentration of the second conductivity type diffusion layer, the ambient temperature, and the size of the resistance element. In FIG.
Assuming that the length of the long side of the resistive element is L and the length of the short side is W, and the carrier flows intensively on the substrate surface, the resistance value R is calculated as R ₀ = ρ _S · L / W. Can be Here, ρ _S is the sheet resistance. The reason for forming the resistance element using the impurity diffusion layer is as follows.
This is because a larger resistance value can be obtained with a smaller area than polycrystalline silicon or the like. However, the resistance element of the impurity diffusion layer has a disadvantage that the bias dependency is larger than that of polycrystalline silicon. This bias dependency becomes more conspicuous as the impurity concentration of the resistance element is lower. The reason for this is that the depletion layer formed by the applied voltage between the first conductivity type semiconductor region 6 and the second conductivity type diffusion layer 1 becomes wider as the impurity concentration becomes lower, and the dimension W of the resistance element becomes smaller. is there.

FIG. 13 is a diagram showing the spread of a depletion layer 5 of a conventional semiconductor resistance element. The resistance value R ₀ obtained by the above equation
Is the resistance value in the ideal state where there is no depletion layer,
The actual resistance value R of the semiconductor resistance element is obtained by the following equation in consideration of the bias dependency. _{R = ∫ρ S · L / (} W-2 · Wk) · dL where, Wk denotes a width of the depletion layer.

[0005]

One of the problems when a resistance element is constituted by an impurity diffusion layer is that the spread of a depletion layer changes according to an applied voltage, and the effective sectional area of the resistance element changes. Changes the resistance value. Due to the bias dependence of the resistance value, it has been difficult to form a high-precision resistance element with a conventional diffused resistor. The depletion layer generation region can be defined separately on the resistance element side surface and the resistance element bottom surface, which is the boundary surface of the resistance element. Is determined by the distribution of carriers moving through the carrier. If the impurity concentration forming the resistance element is low and the distribution in the depth direction is uniformly spread from the surface of the semiconductor substrate to a certain depth, the distribution of carriers is concentrated on the surface of the semiconductor substrate. The main factor of the bias dependence of the resistance value is a depletion layer generated on the side surface of the resistance element. Conversely, the impurity concentration is high and the distribution in the depth direction is
If the carrier is concentrated on the semiconductor surface or at a certain depth, the distribution of carriers is uniformly distributed over the entire resistance element.
A depletion layer generated on the bottom surface of the resistance element is added.

Conventionally, various proposals have been made regarding the bias dependence of the resistance value due to the change of the depletion layer in the depth direction (JP-A-61-94353, JP-A-1-316969, JP-A-63-157461, etc.). Although countermeasures have been taken, no special consideration has been given to the depletion layer formed on the side surface of the semiconductor resistance element. Therefore,
The problem to be solved by the present invention is to reduce the bias dependency of the resistance value caused by a depletion layer formed especially on the side surface of the semiconductor resistance element, so that a highly accurate diffusion resistance can be provided. It is to be.

[0007]

According to the present invention, there is provided a semiconductor device having a second conductivity type diffusion layer formed in a surface region of a first conductivity type semiconductor region. Using the second conductivity type diffusion layer as a resistance element, on the side where the potential difference between the side parallel to the carrier flow path of the second conductivity type diffusion layer and the first conductivity type semiconductor region is large.
Only one or more protrusion-shaped patterns (4) are formed. And, preferably,
The protrusion pattern (4) is formed in a rectangular shape (FIGS. 1 and 7) or a triangular shape (FIGS. 6 and 8). Also,
This protruding pattern may be formed alternately on opposing sides (FIGS. 7 and 8).

[Operation] The projection-shaped layout pattern added in the present invention hardly contributes to the resistance value of the resistance element. The resistance value is substantially determined as before.
L and W are the basic parameters of the resistance element. According to the present invention, it is possible to absorb a part of the generation region of the depletion layer which causes the bias dependence of the resistance value by the projection-like pattern added by the present invention, regardless of the factor determining the resistance value. (See FIG. 5), thereby, it is possible to provide a semiconductor resistance element with less bias dependency.

[0009]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a layout pattern diagram of a resistive element formed on a semiconductor substrate for explaining a first embodiment of the present invention. As shown in FIG. 1, in the semiconductor device of the present invention, a second conductivity type diffusion layer 1 is formed in a surface region of a first conductivity type semiconductor region 6,
The second conductivity type diffusion layer 1 is used as a resistance element. At both ends of the resistance element, electrodes 2 and 3 that are in ohmic contact with the second conductivity type diffusion layer 1 are formed. The voltage applied to these electrodes is set so that the first conductivity type semiconductor region 6 and the resistance element are reversely biased, so that no current flows between the two semiconductor regions. According to the present invention, one or a plurality of projecting patterns 4 are provided on the longer side of the planar pattern of the second conductivity type diffusion layer 1 serving as a resistance element, where the potential difference from the first conductivity type semiconductor region 6 is larger. It is formed. FIG. 2 is a cross-sectional view taken along line AA 'of FIG. The depth of the second conductivity type diffusion layer 1 forming the resistance element is constant, and its impurity concentration is also uniform in the depth direction.

[Explanation of Operation] In the first embodiment, assuming that carriers moving in the resistance element are concentrated on the surface of the semiconductor substrate, the operation will be described below. In FIG. 1, when the resistance element according to the present invention is constituted by an n-conductivity type diffusion layer, a positive potential
The ground potential and the potential of the p-type semiconductor region (6) covering the resistance element are set as the ground potential. 3 and 4
FIG. 3 is a diagram showing the state of the depletion layer 5 on the resistance element side at this time. As the voltage applied to the electrode 3 is increased, the depletion layer 5 changes from FIG. 3 to FIG.

FIG. 5 is an enlarged view of the protruding pattern portion shown in FIGS. In a conventional resistance element, that is, in a resistance element having no projection pattern 4, SI1 or S1
Although the portion indicated by I2 was also depleted, according to the present invention,
The portions indicated by SI1 and SI2 are not depleted. The depletion layer occurs instead of the portions shown in SI1 and SI2.
It occurs in the portions indicated by 1 and SO2. The portions indicated by SI1 and SI2 are regions that can be flow paths of carriers moving in the resistance element, but the portions indicated by SO1 and SO2 cannot be flow paths of carriers moving in the resistance element. . Therefore, the fluctuation of the resistance value of the resistance element can be suppressed by an amount corresponding to the depletion layer generation region being absorbed by the protruding pattern. Therefore, according to the first embodiment of the present invention, the bias dependence of the resistance value can be suppressed without changing the manufacturing conditions of the resistance element.

FIG. 6, FIG. 7, and FIG. 8 are layout pattern diagrams showing second, third, and fourth embodiments of the present invention. The difference between the embodiment shown in FIG. 6 and the embodiment shown in FIG. 1 is that the shape of the projecting pattern formed for the purpose of absorbing the depletion layer is rectangular in the first embodiment. However, in the second embodiment, a triangular shape is provided. Even if the shape of the protruding pattern is changed in this way, if care is taken not to increase the carrier density of the movement in the resistive element on the protruding pattern, the same as in the first embodiment can be obtained. The effect can be obtained. 1 and 6, the projecting pattern is formed at the same position on the opposite side, whereas in the embodiment shown in FIGS. 7 and 8, the projecting pattern 4 is formed. Are alternately laid out on opposite sides. When the protruding patterns are alternately arranged as described above, it is possible to alleviate the narrowing of the width of the carrier flow path with respect to the extension of the depletion layer, and to further suppress the bias dependence of the resistance value. In the above embodiment, the case where the width of the protruding pattern (the base portion of the protruding pattern) is equal to the length between the protruding patterns has been described. May be larger than the distance between the protruding patterns, and vice versa.

FIG. 9 is a cross-sectional view for explaining a fifth embodiment of the present invention. The layout pattern on the semiconductor substrate according to the fifth embodiment of the present invention includes first to fourth layout patterns.
Any of the above embodiments may be used. FIG. 9 is a cross-sectional view taken along line AA ′ of FIG. 1 or an equivalent part of another drawing. In the present embodiment, a projection 7 is added to the bottom surface of the second conductivity type diffusion layer 1 on the side where the potential difference from the first conductivity type semiconductor region 6 becomes large. This structure can be formed by selectively performing ion implantation with higher energy than the energy at the time of ion implantation when forming the second conductivity type diffusion layer which is a semiconductor resistance element. With this structure, in the original structure of the resistance element, the depletion layer formed on the bottom surface of the diffusion layer can be absorbed by the depletion layer formed on the tip of the projection 7, so that the depletion layer is formed near the bottom surface of the resistance element. Even when the carrier flow path is formed, the bias dependence of the resistance value can be suppressed.

[0014]

Next, an embodiment of the present invention will be described in detail. In this embodiment, the diffusion resistance of the layout pattern shown in FIG. 1 was formed. First, boron (B) ions are implanted into a silicon substrate so that the impurity concentration Na is about 7 × 10
A p-type semiconductor region (6) of ¹⁶ / cm ³ is formed, and then, phosphorus (P) is selectively ion-implanted into the region to form an impurity concentration Nd of about 4 × 10 ¹⁷ / cm ³ . An n-conductivity type diffusion layer (1) having a long side length L of 10 μm and a short side length of 1 μm was formed, and this was used as a resistance element. At this time, the width Wk of the depletion layer with respect to the voltage V applied between the p-type semiconductor region and the n-type diffusion layer can be calculated by the following equation. Wk = √ [2ε · ε ₀ · (Φd−V) · Na / ｛q · N
d · (Na + Nd)}] where ε is the relative dielectric constant of the substrate, ε ₀ is the dielectric constant of vacuum, Φ
d is the built-in potential of both conductivity type layers, and q is the unit charge. If this equation is described using an appropriate constant B, it can be written as Wk = B√ (Φd−V).

FIG. 10 is a graph showing the depletion layer width Wk with respect to the applied voltage V. The width of the depletion layer shown on the vertical axis of the graph is doubled in consideration of the depletion layers generated on both sides in the W direction of the resistance element in order to match the resistance value calculation of the resistance element later. is there. Even if the applied voltage is 0 V, the width of the depletion layer does not become 0 μm because of the built-in potential. Further, when the applied voltage is 6 V, the width of the depletion layer is as large as 0.1 μm.

FIG. 11 shows the rate of change of the resistance value of the resistance element having the conventional structure shown in FIG. 12 and the resistance element of this embodiment of the layout pattern shown in FIG. 1 using the voltage Vr applied to the electrode terminal 3 as a parameter. This is a graph (the voltage applied to the electrode 2 and the p-type semiconductor region is 0 V). The width of each resistance element is 1 μm. The protrusion pattern is 1 μm
The pitch, the width and the length were both 0.5 μm, and five pieces were formed on each side. The conventional resistance value R is as follows: R = ∫ρ _S / (W−2Wk) · dL = ρ _S / ｛W−2B · Ｂ (ΦdV)} · dL = ρ _S · L · [W · log [(W −2B · {Φd) / {W−2B · {(Φd−Vr)}] − 2B · {(Φd−Vr) − {Φd}] / (2Vr · B ² ). And this, the resistance value is expecting R ₀ = ρ _S · L /
By taking the ratio with W, the curve of the conventional example in FIG. 11 can be obtained. In the conventional example, when the applied voltage is 6 V, the variation rate of the resistance value is about 10%. On the other hand, in the embodiment of the present invention, since the generation of the depletion layer around the original resistor is absorbed by the protruding layout pattern, the dependency of the resistance value on the applied voltage is relaxed. Resistance value fluctuation can be suppressed to about 7%.

[0017]

As described above, the diffused resistor according to the present invention has a protruding pattern provided around the original resistance element, so that the depletion layer generated around the original resistance element is reduced in resistance value. Can be transferred to the tip of the protruding pattern where there is almost no carrier moving in the resistive element, and a semiconductor resistive element with less bias dependence than before can be realized. Further, according to the embodiment in which the protrusion is provided on the bottom surface of the resistance element, the bias dependence of the resistance value due to the extension of the depletion layer in the depth direction can be suppressed.

[Brief description of the drawings]

FIG. 1 is a layout pattern diagram showing a first embodiment of a resistance element of the present invention.

FIG. 2 is a cross-sectional view taken along line AA 'of FIG.

FIG. 3 is a diagram showing a state of a depletion layer in one embodiment of the resistance element of the present invention.

FIG. 4 is a diagram illustrating a state of a depletion layer according to an embodiment of the resistance element of the present invention.

FIG. 5 is an enlarged view near a protruding pattern for explaining the effect of the present invention.

FIG. 6 is a layout pattern diagram showing a second embodiment of the resistive element of the present invention.

FIG. 7 is a layout pattern diagram showing a third embodiment of the resistance element of the present invention.

FIG. 8 is a layout pattern diagram showing a fourth embodiment of the resistance element of the present invention.

FIG. 9 is a sectional view showing a fifth embodiment of the resistance element of the present invention.

FIG. 10 is a graph showing a bias dependence of a depletion layer width.

FIG. 11 is a graph showing the bias dependence of the normalized resistance value of the conventional example and the example of the present invention.

FIG. 12 is a layout pattern diagram of a conventional resistance element.

FIG. 13 is a plan view for explaining the operation of a conventional resistance element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 2nd conductivity type diffusion layer (semiconductor resistance element) 2, 3 electrode 4 Projection pattern 5 Depletion layer 6 1st conductivity type semiconductor region 7 Projection

Claims (4)

(57) [Claims] 1. A semiconductor device in which a second conductivity type diffusion layer is formed in a surface region of a first conductivity type semiconductor region, and wherein the second conductivity type diffusion layer is used as a resistance element. A semiconductor device, wherein one or more protruding patterns are formed only on the side of the side parallel to the carrier flow path where the potential difference from the first conductivity type semiconductor region is large . 2. The semiconductor device according to claim 1, wherein said protruding pattern has a rectangular shape or a triangular shape. 3. The semiconductor device according to claim 1, wherein the protruding patterns are formed alternately on opposite sides. 4. The method according to claim 1, further comprising: setting a potential difference between the bottom surface of the second conductivity type diffusion layer and the first conductivity type semiconductor region only in a portion where the potential difference is large.
2. The semiconductor device according to claim 1, wherein one or more protrusions are formed.