JP3080478B2 - Pedestal level addition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for adding a pedestal level to a video signal, which is one of the digital processes, when a television video signal is digitally processed.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a main part of a conventional pedestal level adding device. Hereinafter, a conventional method of adding pedestal level data will be described with reference to FIG. NT
An analog video signal 31 of the SC system or the like is subjected to pedestal clamp processing by a clamp circuit 32, and then converted from an analog to a digital video signal by an A / D conversion circuit 33. This digital video signal is input to the digital processing unit 34. The digital processing here includes a series of processing required as a video signal. For example, various arithmetic processing, storage, image processing (data interpolation, thinning), or
The digital processing referred to here includes time compression processing required when displaying a 4: 3 NTSC signal on a 16: 9 display. In the digital processing in the digital processing unit 34, the pedestal level data of the video signal existing in the input stage of the digital processing unit 34 is lost in the output stage. The reason is that the digital processing is simplified and the processing steps are convenient. Therefore, in order to add the lost pedestal level data to the digitally processed video signal, the pedestal level data output unit 35 outputs fixed pedestal level data. The reason why the pedestal level is fixed is that the pedestal level is fixed (clamped) by the clamp circuit 32, so that the digital level corresponding to the pedestal level is also fixed.

A block for adding the pedestal level data to the video signal from the digital processing section 34 is a pedestal level adding circuit 36. The specific configuration of the additional circuit 36 is a switching circuit. That is, the switching is made to the digital processing section 34 in the video period in one horizontal cycle, and to the pedestal level output section 35 in the pedestal period. Thus, pedestal level data is added to the digitally processed video signal. The video signal to which the pedestal level data is added is converted into an analog video signal 38 by a D / A conversion circuit 37.
And transmitted to a subsequent circuit or the like. The above is the basic operation of FIG. 3, but there is one problem here. next,
This problem will be described with reference to FIG.

In FIG. 4, (A) shows a video signal (analog) pedestal clamped by the clamp circuit 32 of FIG. 3 in relation to a voltage, and (A) in the figure shows a pedestal level, (B) ) Is a video component. This (A)
Is digitally converted by the A / D conversion circuit 33. During this digital conversion, if the power supply voltage supplied to the A / D conversion circuit 33 fluctuates, the reference voltage of the A / D conversion circuit 33 changes, causing the pedestal level of the input video signal (A) to change. Is constant, the A / D converted digital data differs from the original signal. In other words, if the reference voltage does not change, digital encoding is performed in the range of the hatched portion shown in FIG. 2B. However, if the reference voltage changes, it is shifted to the range of the hatched portion shown in FIG. This means that the pedestal level data is originally “40H” in (B),
This is "4CH" in (C), and does not mean that the original signal has been faithfully converted to digital. Note that the above (B) and (C) show hexadecimal notation when 8-bit conversion is performed as an example.
Will consist of the same data. The pedestal level data output from the pedestal level data output unit 35 of FIG. 3 is fixed data based on the state of FIG.
(B) 40H]. Therefore, as described above, when the A / D conversion output becomes as shown in (C) due to a change in the reference voltage or the like, the fixed data is inappropriate data. In this case, "4CH" must be output.

[0005]

As described above, in the case of FIG. 3 (prior art), since the pedestal level data output from the pedestal level data output unit 35 is a fixed value, the reference voltage When the A / D conversion output fluctuates due to a change or the like, there is a problem that a correct pedestal level cannot be added. In order to solve such a problem, the present invention provides a pedestal level adding device in which even when an A / D conversion output fluctuates, a pedestal level is accurately added according to the fluctuation. The purpose is to do.

[0006]

According to the present invention, there is provided a digital video signal processing circuit for extracting only pedestal level data from a digital video signal containing pedestal level data, and a pedestal from the means. The present invention provides a pedestal level adding device, comprising means for superimposing and adding level data to a video signal in which pedestal level data has disappeared after digital processing of the digital video signal. A means for extracting only the pedestal level data, a control signal generation circuit for generating a pulse rising in an existing section of the pedestal level data in the digital video signal using the input horizontal synchronization signal; And a D-flip-flop that outputs only the pedestal level data using a pulse from the control signal generation circuit as a clock signal.

[0007]

The present invention extracts only pedestal level data from a conventional A / D conversion output. For this reason, even if the A / D conversion output changes, the extracted data follows the change. Therefore, if the extracted data is added to the digitally processed video signal in the same manner as in the related art by a pedestal level adding circuit having the same configuration as in the related art, accurate pedestal level addition can be realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pedestal level adding device according to the present invention will be described below with reference to the drawings. FIG. 1 is a main part block diagram showing an embodiment of a pedestal level adding device according to the present invention. In the figure, components equivalent to those in FIG. 3 are denoted by the same reference numerals, and 1 is a pedestal level extraction circuit. FIG.
1A is a main block diagram showing an embodiment of the pedestal level extraction circuit 1 in FIG. 1, and FIG. 2B is an operation explanatory diagram of FIG. 1A, and FIG. 1A is an A / D conversion output with respect to time. , (B) is the output of the control signal generation circuit 2,
(C) is the output of D-FF3.

First, the operation of FIG. 1 will be described. The analog video signal 31 is pedestal-clamped by the clamp circuit 32 and converted to a digital video signal by the A / D conversion circuit 33, as in the case of FIG. The pedestal level extraction circuit 1 extracts only pedestal level data from the digital video signal. If the digital output shifts from normal due to a change in the reference voltage of the A / D conversion circuit 33 (FIG. 4C) as described with reference to FIG. 3, the extracted pedestal level data also follows the change. . The extracted pedestal level data is added by a pedestal level adding circuit 36 to the video signal from the digital processing section 34 as an accurate level. The basic configuration and operation of the pedestal level adding circuit 36 and the operation of the D / A conversion circuit 37 are the same as those in the case of FIG.

Next, FIG. 2 will be described. 2A indicates the pedestal level extraction circuit 1 in FIG. 1. The purpose of the control signal generation circuit 2 composed of a control signal generation circuit 2 and a D-FF (flip-flop) 3 is to input. That is, a control signal (b) for controlling the D-FF is generated from the horizontal synchronizing signal. On the other hand, from the A / D conversion circuit 33, a digital signal in which the pedestal level data and the video data shown in (a) are alternately input to the D terminal of the D-FF3. Then, the control signal (b) is input to the clock (CK) terminal of D-FF3. The control signal (b) acting as the clock signal of D-FF3 is a pulse that rises in the section where the pedestal level data exists in (a). This pulse period is naturally one horizontal period (H), and for that purpose, a horizontal synchronizing signal is used.

D-FF3 input by (a) and (b)
Outputs only the pedestal level data shown in (c) to the Q terminal from the basic principle operation. here,
The fact that the output data of the A / D conversion circuit 33 fluctuates (a)
Of the extracted data fluctuates, so that the extracted data (c) naturally follows. Although the video signal also fluctuates at the same time, the level relationship with the pedestal level data extracted as described above maintains the level of the original signal. Therefore, the addition of pedestal level data by the pedestal level adding circuit 36 becomes accurate even when the A / D conversion output fluctuates.

[0012]

As described above, according to the present invention, it is possible to accurately add pedestal level data to a video signal in a digital processing stage of the video signal.
That is, when the A / D conversion output of the video signal changes due to a power supply voltage fluctuation or the like, the addition following the fluctuation has not been made conventionally, but the present invention follows the fluctuation, so that the pedestal is accurate. Level data can be added, which contributes to improvement in performance such as image quality as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a pedestal level adding device according to the present invention.

2A is a main block diagram showing an embodiment of a pedestal level extraction circuit 1 in FIG. 1, and FIG. 2B is an operation explanatory diagram of FIG.

FIG. 3 is a main block diagram showing an embodiment of a conventional pedestal level adding device.

FIG. 4 is an explanatory diagram of FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 pedestal level extraction circuit 2 control signal generation circuit 3 D flip-flop 31 analog video signal 32 clamp circuit 33 A / D conversion circuit 34 digital processing section 35 pedestal level data output section 36 pedestal level addition circuit 37 D / A conversion circuit 38 Output analog video signal

Claims (2)

(57) [Claims] An analog video signal inputted is digitally converted.
Is converted to a video signal, and this converted digital video signal is
An analog signal different from the analog video signal
Means for extracting only the pedestal level data from the converted digital video signal containing pedestal level data, wherein the pedestal level is output from the digital video signal processing circuit. Means for superimposing and adding data to the predetermined processed video signal in which the pedestal level data has disappeared. 2. A control signal generating circuit for generating a pulse which rises in an existing section of pedestal level data in the digital video signal using an input horizontal synchronizing signal, wherein said means for extracting only the pedestal level data is used. And the digital video signal is input,
2. The pedestal level adding device according to claim 1, further comprising a D-flip-flop that outputs only the pedestal level data using a pulse from the control signal generation circuit as a clock signal.