JP3080719B2 - Read-only memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read only memory device of the present invention, and more particularly to an input circuit thereof.

[0002]

2. Description of the Related Art Conventionally, in this type of read-only memory device, a memory cell is selected according to an input signal of an address terminal or a control terminal, and stored information is read from the selected memory cell. Such read-only memory devices are classified into a synchronous type and an asynchronous type. Many read-only memory devices are of an asynchronous type which does not require an easy-to-use synchronous signal. In recent years, ATD (Address Transit) has been developed to prevent noise generation.
on Detect) or DTD (DataTran)
A read-only memory device adopting a position detect (DT) system has been developed.
In the D method, when a change in an address or data is detected, the operation of a sense amplifier or an output buffer is limited to prevent generation of noise.

[0003]

In a conventional read-only memory, when output data changes, a large current instantaneously flows through a power supply wiring and a ground wiring. As a result, noises dVCC and dGND occur in the power supply line and the ground line (see FIG. 3). When noise dVCC and dGND occur on the power supply line and the ground line,
If the input signal level of the input circuit, for example, the address input circuit has a small margin with respect to the logical threshold, the logical level of the input signal is inverted and an erroneous address is taken. The inversion of the logic level causes an error, and the conventional read-only memory device has a problem in that data corresponding to an incorrect address is output td time after normal data is fetched.

In the ATD system and the DTD system, only the operation of the output buffer and the sense amplifier is limited.
Data read from the wrong address was still read, and the effect on this type of noise was insufficient.

[0005]

The gist of the present invention is to address
From the address signal supply terminal and the address signal supply terminal.
In the read-only memory device having a memory circuit for outputting data designated by the address signal, before
Provided between the address signal supply terminal and the memory circuit.
When the input control signal is at the first logic level
Is an address input from the address signal supply terminal.
A signal is output to the memory circuit as it is, and the control signal
Is at a second logic level, the address signal supply
Holds the address signal input from the terminal, and
Address signal storage for outputting a dress signal to the memory circuit.
Holding means and the memory signal from the address signal holding means.
When a change in the address signal output to the path is detected,
The control signal output to the address signal holding means
Time to said second logic level, then said address
The control signal output to the signal holding means is converted to the first logic.
Level detection circuit, and switching of address signal
After that, the address signal supplied to the memory circuit is
Locations affected by power and ground noise
That is, the address signal is held for a fixed time .

[0006]

When the address signal changes, the address is changed.
Changed even signal outputted from the signal holding means, the signal change is supplied to the memory circuit and the detection circuit. Data is read from the memory circuit, and the detection circuit instructs the address signal holding unit to hold the address. Therefore, even if noise occurs at the time of data reading and the address signal changes, a correct address is continuously supplied to the memory circuit from the address holding means.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. The address terminal An supplies an address bit to the memory circuit 7 via the buffer circuit 100 including the inverter 1, the clocked inverter 2, the inverter 3 and the clocked inverter 4, and the other address terminals An +
1 is similarly configured. Outputs a0 (overline) to an + 1 (overline) of each buffer circuit 100 are input to a detection circuit 6 for detecting a change in signal. The output ae (overline) of the circuit 6 for detecting a change in the signal functions as a control signal for the clocked inverter 4 and further serves as an input of the inverter 5. The output of the circuit 6 controls the clocked inverter 2. That is, the buffer circuit 100, the clocked inverter 2, and the inverter 5 constitute a static latch circuit 101 that uses ae (an over-line) as a control signal.
Next, the operation of the circuit of FIG. 1 will be described. Detection circuit 6
Means that the input signal an (overline) does not change
The low-level control signal ae (over
Line). At this time, the clocked inverter
2, the control signal ae (overline) is inverted.
A “high level” control signal is input. Clock Doi
The inverter 2 receives a “high level” control signal.
Then, the input signal is inverted and output. Also, "Loulebe
Control signal ae (overline)
The output of the clocked inverter 4 input by
Impedance. Therefore, the signal an (over
Line) does not change, the address signal An
The inverted signal becomes the signal an (overline). Ad
When the address signal An changes, the signal an (overwrite
(Address signal An is inverted).
No. an (overline). Signal an (O
When the bar line changes, the signal an (overlay)
The detection circuit 6 for inputting the control signal ae
(Overline) for a predetermined time Th "high level"
I do. When the control signal ae (overline) is "high level
While the clocked inverter 2 is
Inverted control signal ae (overline)
Control signal is input, and the low-level control signal
Is output from the clocked inverter 2 to which
Impedance. In addition, the control signal of "high level"
ae (overline) is input as a control signal.
Locked inverter 4 inverts the input signal and outputs the inverted signal.
You. Therefore, the control signal ae (overline)
While the signal is at the “high level”, the address signal An
The signal an immediately after the address signal An changes without being transmitted
(Overline) is clocked in with inverter 3.
The data is held by the circuit composed of the inverter 4 and supplied to the memory circuit 7
I do. The control signal ae (overline) takes a predetermined time
After returning to "Low level" after Th, the clock
The inverter 2 has a counter signal of the control signal ae (overline).
The inverted "high level" control signal is input. Clock
Inverted inverter 2 receives a “high-level” control signal.
Then, the input signal is inverted and output. Also, "Row
Level ”control signal ae (overline) is the control signal
The clocked inverter 4 input as
It becomes an impedance. Therefore, the address signal A
The inverted version of n becomes the signal an (overline).
As described above, the control signal ae (overline)
Only during the predetermined time Th during which the
Address signal An is not transmitted, and the address signal An changes.
The signal an (overline) immediately after is connected to the inverter 3.
It is held by a circuit consisting of the clocked inverter 4 and
The address signal An during the other period.
The inverted signal becomes the signal an (overline),
It is supplied to the memory circuit 7.

Next, the operation of the embodiment will be described with reference to FIG. When the address signal changes, signal An (over line)
Also changes, and the signal an (over line) also changes. Signal an
When the detection circuit 6 detects a change in the (overline), the detection circuit 6 outputs a control signal ae (overline) for a time Th. The change of the address changes the data bit Dm read from the memory circuit 7. The charging / discharging current when the data bit Dm changes changes the noises dVCC and dGN to the power supply VCC and the ground GND.
D is generated. If the address signal has a small margin with respect to the logical threshold value of the inverter 1, the noise dVCC,
When dGND occurs, the inverter 1 outputs erroneous data. At this time, since the static latch circuit 101 composed of the inverters 3 and 5 and the clocked inverters 2 and 4 holds a correct address, the memory circuit 7 has no effect.

[0010]

As described above, according to the present invention, the address signal is generated by the noise of the power supply line and the ground line.
Changes, the memory circuit continues to output data from the memory cell at the address specified by the address signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment.

FIG. 2 is a waveform chart showing the operation of one embodiment.

FIG. 3 is a waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 1Inverter  2 Clocked inverter (first clocked inverter
3) Inverter (1st inverter4) Clocked inverter (second clocked inverter)
5) Inverter (Second inverter6 detection circuit 7 memory circuit 101 static latch circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-5492 (JP, A) JP-A-64-89098 (JP, A)

Claims (2)

(57) [Claims] An address signal supply terminal and an address signal supplied from the address signal supply terminal.
In the read-only memory device having a memory circuit for outputting data specified in, set between the address signal supply terminal and said memory circuit
When the input control signal is at the first logic level
The address input from the address signal supply terminal
The control signal is output to the memory circuit as it is, and the control signal is output.
When the signal is at the second logic level, the address signal
Holds the address signal input from the supply terminal and holds it
Address signal for outputting an address signal to the memory circuit
Holding means, output from the address signal holding means to the memory circuit.
When a change in the address signal is detected,
The control signal output to the signal holding means for a predetermined time.
2 and then the address signal holding means
Setting the control signal output to the first stage to the first logic level.
And a detection circuit which supplies the memory circuit after the switching of the address signal.
Address signal is affected by power supply noise and ground noise.
A read-only memory device, which holds the address signal for the predetermined time affected by 2. An address signal holding means, comprising: a first clocked terminal connected to the address signal supply terminal.
An inverter; the first clocked inverter;
A first inverter connected to a memory circuit;
The output node is connected to the input node of one inverter.
An input node is connected to an output node of the first inverter.
A second clocked inverter, the detection circuit and the second
Second inverter connected between one clocked inverter
And the control signal output by the detection circuit.
Are supplied to the second clocked inverter and the second inverter.
2. The read-only memory device according to claim 1, wherein the read-only memory device is a supplied static latch circuit.