JP3080930B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of storing information.

[0002]

2. Description of the Related Art Conventionally, as this kind of semiconductor memory device, the one shown in FIG. 6 is known. In FIG. 6, addresses A12 to A17 for designating memory cells are used.
Are input to an address buffer 903, and the output of the address buffer 903 is input to a block decoder 904. As a result of this input, a signal for designating a memory cell is output by the block decoder 904. .

FIG. 7 schematically shows the circuit of the block decoder 904 by symbols, and particularly shows the connection state of the highest address TA17. In the figure, the highest address TA17 is directly connected to NAND circuits 910a to 910d, and the NAND circuit 9 via a NOT circuit 912.
11a to 11d. Further, the NAND circuits 910a to 910d and the NAND circuits 911a to 911d include:
Address signals other than the top address TA17 are also input.

The outputs of the NAND circuits 910a to 910d and 911a to 911d are output as TBLA to H via a NOT circuit.
Further, in the process of fabricating the semiconductor memory device, the uppermost address TA17 can be switched to the aluminum master slice by changing the mask pattern and short-circuited to VCC.

The memory cell A group 901 has a
rA to D, and the memory cell B group 902 is Secto
The memory cell group A 901 and the memory cell B group 902 each have half the memory capacity of the semiconductor memory device.
To H, the X-D of the memory cells A 901 and B
It is determined whether the EC is activated or not.

In the above-described configuration, when the highest address TA17 is at a high level, at least one of the signals input to the NAND circuits 910a to 910d is always at a high level, and is input to the NAND circuits 911a to 911d. At least one of the signals is always low level,
In this situation, the NAND circuit 91 is involved in this logical calculation.
0a to d, and as a result, the memory cell A group 901 is activated.

Therefore, by fixing the highest address TA17 to VCC by using the aluminum master slice switching, only the memory cell group A 901 can be provided as a reduced bit cell capacity memory.

[0008]

The conventional semiconductor memory device described above has the following problems. That is, when the sector B and the sector E in the shaded portions of the memory cell group A and the memory cell B group are sector failures such as bit failure abnormality and cannot be repaired by the redundant circuit for bit repair , the memory cell group A and the memory cell B The flock becomes completely defective and must be discarded as a bad chip.

When only the memory cell group A is provided as a reduced-bit-cell-capacity memory, the above TA17 is set to VCC.
However, two mask reticles are required, which increases the manufacturing cost and the number of manufacturing steps.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which has been made in view of the above problems, can be manufactured easily, and can reduce the amount of discarded defective products.

[0011]

According to a first aspect of the present invention, there is provided an information storage apparatus for writing and erasing information to and from a memory cell designated by a predetermined address signal. A semiconductor memory device having a pair of memory cell groups constituted by a plurality of memory cells performing an operation, wherein the pair of memory cell groups includes
A selection signal output means for determining a memory cell group to be used as among main, specific one-signal and the selection of the address signals
Memory cell group based on a signal from the selection signal output means.
Group selection / address signal output means for outputting a selection signal ,
When one memory cell group is mainly used and there is a defective sector in this memory cell group, a normal sector of the other memory cell group is assigned instead of this defective sector.
A sector switching means for outputting the order control signal, the output signal from the group selecting address signal output means and said section
And a block decoding unit for outputting a signal for specifying the memory cell group to be used to the memory cell group in accordance with an output signal from the data switching unit .

That is, the selection signal output means is connected to the pair.
Use one of the memory cell groups
When a signal for selecting a memory cell group is output, the group selection / address signal output means inputs a predetermined one of the address signals and the selection signal to select the memory cell group. And outputs a signal for representing the address. When the group selection / address signal output means outputs a signal for representing the address of the memory cell,
The decoding means outputs a signal for specifying the memory cell to be used according to the output signal and the address signal to the memory cell group. When one of the memory cell groups is used and the memory cell group has a defective sector, the sector switching means allocates and uses a normal sector of the other memory cell group instead of the defective sector. The decoding means is controlled as described above.

The above-mentioned memory cell group is obtained by grouping a predetermined number of memory cells for writing and erasing data in one unit. A flip-flop circuit or the like may be used as long as it constitutes a so-called memory cell array. It is sufficient that the SRAM and the DRAM to be used are integrated, and the memory cell for writing and erasing is specified by the address signal.

The address signal designates one of the memory cells by a binary of a plurality of digits. One of the predetermined address signals inputted to the group selection / address signal output means is such that the memory cell has Any signal may be used as long as it indicates which digit of the pair of memory cell groups it belongs to, and it is preferable to use the highest address signal among the above address signals.

A specific example of a configuration for outputting a signal representing an address of the memory cell while selecting the memory cell group by inputting a predetermined signal of the address signal and the selection signal, The invention according to claim 2 is
2. The semiconductor memory device according to claim 1, wherein said group selection / address signal output means inputs said address signal and said selection signal to a NOR circuit, and outputs an output of said NOR circuit via a NOT circuit. There is a configuration.

That is, a predetermined one of the address signals and the selection signal are input to a NOR circuit, and furthermore,
By outputting via the T circuit, the output goes high when both the predetermined one of the address signals and the selection signal are low, and the output goes low otherwise.

Further, as a specific example of the configuration for outputting the selection signal, the invention according to claim 3 is the semiconductor memory device according to claim 1 or 2, wherein the selection signal output means is provided with a predetermined control signal. A first transistor and a second transistor having a control terminal for inputting a signal and one terminal and the other terminal, and a floating gate type fuse cell having a control terminal for inputting a predetermined write signal and one terminal and the other terminal. A predetermined voltage is applied to one terminal of the first transistor, the other terminal of the first transistor is connected to the one terminal of the second transistor, and an output is taken out as the selection signal. Connect the other terminal of the two transistors to one terminal of the floating gate type fuse cell, Certain other terminal of Ingugeto fuse cells configured so as to ground.

That is, by switching the floating gate type fuse cell to an ON cell or an OFF cell by the write signal, the selection signal as the output signal is set to a high level or a low level.

Further, as a specific example of a configuration for performing control by the sector switching means, the invention according to claim 4 is the semiconductor storage device according to any one of claims 1 to 3, wherein The means includes a first transistor and a second transistor having a control terminal for inputting a predetermined control signal, one terminal and the other terminal, and a floating terminal having a control terminal for inputting a predetermined write signal and one terminal and the other terminal. A gate type fuse cell, a predetermined voltage is applied to one terminal of the first transistor, the other terminal of the first transistor is connected to one terminal of the second transistor, and an output is taken out and branched. One of the two transistors has two outputs via a NOT circuit, and the other terminal of the second transistor is connected to the floating gate. While connecting the terminal type fuse cells is configured so as to ground the other terminal of the floating gate type fuse cell.

That is, by switching the floating gate type fuse cell to an ON cell or an OFF cell by the write signal, when one of the output signals is at a high level, the other output is at a low level. Is low level, the other output outputs two signals of high level.

Further, as a specific example of a configuration for outputting a signal for specifying the memory cell to be used to the memory cell group, the invention according to claim 5 is according to any one of claims 1 to 4. in the semiconductor memory device, the blanking
The lock decoding means is a signal state in which the output signal of the selection signal output means is for using one of the memory cell groups, and when a certain sector of the one memory cell group is defective, the lock signal is output from the sector switching means. The control is such that the path for uniquely identifying the defective sector is cut off, and the path for identifying a predetermined normal sector of the unused memory cell group is made conductive.

That is, this decoding means basically functions as a so-called decoder because it outputs a signal for uniquely identifying a certain memory cell by a signal representing an address. Decode to specify only the memory cells of one of the memory cell groups, and if there is a bad sector in one of the memory cell groups to be used, decode to allocate the other unused memory cell group I do.

Further, as a specific example of the actual configuration of the decoding means, the invention according to claim 6 is the semiconductor memory device according to any one of claims 1 to 5, wherein the block decoding means is An output of the group selection / address signal output means and the address signal are directly input to the NAND circuit, and an output of the group selection / address signal output means are input to the NAND circuit via the NOT circuit. Into two paths and output them via a transfer gate.
The output of the signal input to the NAND circuit via the T circuit is output via the transfer gate, this output is branched into two paths, and the output of the signal input directly to the NAND circuit is branched into two paths. Connected to one output via a transfer gate, and by controlling ON / OFF of these transfer gates by the sector switching means, the specified memory cell is specified by the signal output via the transfer gate. There is a configuration to do.

That is, by inputting a signal to the NAND circuit and outputting it through the NOT circuit, the input signal is eventually ANDed. Since the address signal and a NOT signal of the address signal necessary for designating the memory cell of the specific address are connected to the input of the NAND circuit, as a result, A signal is output from a circuit in a state where a flag necessary to specify a memory cell is satisfied, and decoding is performed by uniquely specifying a memory cell with this output signal.

Further, the transfer gate is turned on,
By turning OFF, the connection to the memory cell normally decoded and specified is cut off, and the connection to the other memory cell is made. Avoid specifying a sector.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, addresses A12 to A17 for designating a memory cell are input to an address buffer 103.
First output of 03 is input to a product changeover example circuit 105. This
The output of the product switching circuit 105 and the other output of the address buffer 103 are input to the block decoder 104. As a result of this input , the block
A signal for designating a memory cell is output by the decoder 104 .

FIG . 2 is a schematic circuit diagram of the block decoder 104.
Shows a substantially arrangement, in particular higher address TA17 outermost enters via the said address buffer 103 and product changeover example circuit 105, shown in detail such connection on the output of TBLB and TBLF. In the figure, an input signal is directly connected to a NAND circuit 110 and a NOT circuit 11
2 is connected to the NAND circuit 111. Note that address signals other than the input from the highest address TA17 are also input to the NAND circuits 110 and 111.

The output of the NAND circuit 110 is NO
The output of the NOT circuit 114 is provided via a transfer gate T.
It is output as TBLB through FG1 and N
It is connected to the channel transistor 113 . Also, NA
The output of the ND circuit 111 is adapted to be outputted through a NOT circuit 115, further, NAND circuit 111
TBL output of via a transfer gate TFG3
Output as F.

[0030] The block decoder 104 of FIG. 2 serves as an output signal S1 and S2 of the sector <br/> switching example fuse circuit 107 is input, one is branched output signal S1 to the fourth path is Nch The input is made to the gate of the transistor 113, and the remaining three are transfer gates TFG1,
It is input to each of TFG2 and TFG3. Further, the output signal S2 is branched into three paths, and the output signals from the transfer gates TFG1, TFG2, and TFG3 are output.
The input is made on the opposite side of S1 .

The memory cell A group 101 has a Secto
rA to D, and the memory cell B group 102
It has become a RE～H, the memory cell group A 101 and the memory cell group B 102 is turned by half of the memory capacity of the semiconductor memory device, respectively, the TBLA
X to X− of the memory cells A 101 and B 102
It is determined whether the DEC is active or not. Therefore, the block decoder 104 constitutes the decoding means.

FIG . 5 is a circuit diagram of the product selection fuse circuit 106.
1 shows the configuration. In the figure, the output of the write circuit 405 is connected to the drain of the Nch transistor 401 and the floating gate type fuse cell 403, so that a predetermined voltage is applied to the drain of the Nch transistor 401 and a write control signal is applied to the floating gate type fuse cell 403. To give to. The output of control circuit 406 is connected to the gates of Nch transistors 401 and 402, and Nc
A signal for controlling on / off of the h transistors 401 and 402 is input.

The source of the Nch transistor 401, N
The output G1 is taken out while being connected to the drain of the channel transistor 402 . Further, one terminal of the floating gate type fuse cell 403 is connected to the source of the Nch transistor 402 and the other terminal is grounded. Therefore, the product selection fuse circuit 106 constitutes the selection signal output means.

[0034] Figure 3 shows a circuit configuration of a product changeover example circuit 105, the output signal G1 of the highest address TA17 and product selection Hugh <br/>'s circuit 106 is input, so that the signal SEL is output Has become. In the figure, the highest addresses TA17 and G1 are input to a NOR circuit 201, and the output of the NOR circuit 201 is a NOT circuit 202.
The signal SEL is output via the. did
Therefore, this product changeover example circuit 105 constituting the group selection address signal output means.

FIG. 4 shows the configuration of the sector switching fuse circuit 107 . In the figure, the output of the write circuit 305 is connected to the drain of the Nch transistor 301 and the floating gate type fuse cell 303, and a predetermined voltage is applied to the Nch transistor 301.
And a write control signal to the floating gate type fuse cell 303. The output of the control circuit 306 is Nch
Connected to the gates of the transistors 301 and 302 to turn on the Nch transistors 301 and 302;
A signal for controlling turning off is input.

Further, the source of the Nch transistor 301 is connected to the drain of the Nch transistor 302 and an output is taken out. This output is branched, one of which is an output signal S1, and the other is NOT.
The output signal S2 is output via the circuit 304. Further, one terminal of the floating gate type fuse cell 303 is connected to the source of the Nch transistor 302, the other terminal is grounded. Normally, the floating gate type fuse cell 303 responds to the write control signal.
Has become more ON cell, output S1 is at a low level, out
The force S2 is a high-level output. Therefore,
Sector switching example fuse circuit 107 constitute the sector switching means.

Next, the operation of this embodiment configured as described above will be described. As described above, the floating gate type fuse cell 303 is normally an ON cell, the output S1 is at a low level, and the output S2 is at a high level .
ing. Therefore, the transfer gate T shown in FIG.
FG1 is ON, TFG2 is OFF, and TFG3 is ON.

At this time, if at least one of the highest address TA17 or the output G1 of the product selection fuse circuit 106 is at a high level, the product switching circuit 10
The output signal SEL of 5 is high level, at least one of the signal input to the NAND circuit 110 of the block decoder 104 shown in FIG. 2 is always high level. Then, at least one of the signals input to the NAND circuit 111 of the block decoder 104 shown in FIG. 2 via the NOT circuit is always at the low level. As a result, there is a possibility that a high level output is output from the NAND circuit of the block decoder 104 due to the logical calculation.
Only those that receive inputs such as 0 that do not go through NOT. Therefore, the memory cells A group 101 are activated by the TBLA to TBLA.

The highest address TA17 and product selection
When both the output G1 of the fuse circuit 106 is at a low level, the output signal SEL of the product switching circuit 105
Is at a low level, and at least one of the signals input to the NAND circuit 110 is always at a low level. At least one of the signals input to the NAND circuit 111 via the NOT circuit is always at a high level . I
Therefore, the block decoder 104 by the logical calculation
A high-level output may be output from the NAND circuit of only the NAND circuit 111 or the like that receives an input via NOT . This results in activating pre Symbol memory cell B group 102 by TBLE～H.

Therefore, when only the memory cell group A 101 is used as the reduced bit cell capacity memory, that is, when the group B 102 is not used, the output G1 of the product selection fuse circuit can be fixed at a high level. The most significant address 17 may be any signal (H / L), and this semiconductor memory device can be provided as a reduced bit cell capacity memory.

However, a sector in group A becomes defective.
When using the conventional semiconductor
Like a physical storage device, it causes problems and must be discarded.
No. In such a case, in the present invention, a pair of memory cells
Use one of the groups mainly and use it with signal control.
The normal sector of the memory cell group that is not
By switching the decoder circuit to assign
Can respond. For example, the hatched note in FIG.
Sector B of recell A group and sector E of memory cell B group
When defective, that is, when paired with sector B of group A
Memory cells that are not being used due to signal control.
When there is a normal sector F in the memory cell group, the floating gate type fuse cell 403 is set to the OFF cell, the output G1 of the product selection fuse circuit is set to the high level, the floating gate type fuse cell 303 is set to the OFF cell, and the S1 is set to the high level. Level, S2 is set to a low level output.

Therefore, the transfer gate TFG
1 has OFF, TFG2 becomes ON, TFG3 is the OFF, even if an attempt outputs TBLB by the high level signal of the output signal SEL of the above product changeover example circuit 105,
Since the transfer gate TFG1 is turned off and the transfer gate TFG2 is turned on, the output becomes TBLF. Further, TBLB is fixed to GND by the Nch transistor 113. Therefore, instead of selecting the defective SectorB, the normal SectorF
Can be selected.

As described above, the mask-like change for fixing the highest address TA17 at the high level is performed by the logic circuit, and even if there is a defective sector in the memory cell group, one of the paired memory cell groups is mainly used. I use it . Sand
By switching the decoder circuit so that a normal sector of an unused memory cell group is assigned to the defective sector by signal control, the semiconductor memory device can be easily manufactured and the amount of discarded defective products can be reduced. be able to.

[0044]

As described above, the present invention can provide a semiconductor memory device that can be easily manufactured and can reduce the amount of discarded products as defective. Further, according to the second aspect of the present invention, since a mask-like change is not required to fix the highest address to a high level, the manufacturing cost and the number of manufacturing steps can be reduced. Further, according to the third aspect of the present invention, it is possible to configure a circuit that outputs a signal for selecting a memory cell group by using an element suitable for integration. Further, according to the invention according to claim 4, it is possible to configure a circuit for switching a defective sector to a normal sector by using an element suitable for integration. Further, according to the fifth aspect of the present invention, it is possible to provide a semiconductor memory device capable of reducing the amount of discarded defective products. Furthermore, according to the invention of claim 6, the decoder can be configured using elements suitable for integration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a block decoder.

FIG. 3 is a circuit diagram of a product switching circuit.

FIG. 4 is a circuit diagram of a sector switching fuse circuit.

FIG. 5 is a circuit diagram of a product selection fuse circuit.

FIG. 6 is a block diagram showing a semiconductor memory device according to a conventional example.

FIG. 7 is a schematic circuit diagram of a conventional block decoder.

[Explanation of symbols]

 Reference Signs List 101 memory cell group A 102 memory cell B group 103 address buffer 104 block decoder 105 product switching circuit 106 product selection fuse circuit 107 sector switching fuse circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (6)

(57) [Claims] An information storage operation is performed by writing and erasing information to and from a memory cell designated by a predetermined address signal. a semiconductor memory device, mainly of the memory cell group to be the pair used with
A selection signal output means for determining a memory cell group to use, one predetermined signal and the selection signal output hands of the address signal
The memory cell group selection signal is output based on the signal from the stage.
When one memory cell group is mainly used and a defective sector exists in this memory cell group, a normal sector of the other memory cell group is used instead of the defective sector. allocation
A sector switching means for outputting the order control signal, the upper and the output signal from the group selecting address signal outputting means
A semiconductor memory device comprising: a block decoding unit that outputs a signal for specifying the memory cell group to be used to the memory cell group in response to an output signal from the sector switching unit . 2. The semiconductor memory device according to claim 1, wherein said group selection / address signal output means inputs said address signal and said selection signal to a NOR circuit, and
A semiconductor memory device which outputs an output of an R circuit via a NOT circuit. 3. The semiconductor memory device according to claim 1, wherein said selection signal output means includes: a first transistor having a control terminal for inputting a predetermined control signal, one terminal and the other terminal; A second transistor, a floating gate type fuse cell having a control terminal for inputting a predetermined write signal and one terminal and the other terminal, and applying a predetermined voltage to one terminal of the first transistor; The other terminal of one transistor is connected to one terminal of the second transistor and the output is taken out as the selection signal.The other terminal of the second transistor is connected to one terminal of a floating gate type fuse cell. Wherein the other terminal of the floating gate type fuse cell is grounded. Storage device. 4. The semiconductor memory device according to claim 1, wherein said sector switching means has a control terminal for inputting a predetermined control signal and a first terminal and a second terminal. A transistor and a second transistor, a floating gate type fuse cell having a control terminal for inputting a predetermined write signal and one terminal and the other terminal, and applying a predetermined voltage to one terminal of the first transistor; The other terminal of the first transistor is connected to one terminal of the second transistor, and the output is taken out and branched into one output via a NOT circuit, and the other terminal is floated with the other terminal of the second transistor. Connect to one terminal of the gate type fuse cell, and connect the other terminal of this floating gate type fuse cell The semiconductor memory device which is characterized in that ground. 5. The semiconductor memory device according to claim 1, wherein said block decoding means is arranged so that an output signal of said selection signal output means uses one memory cell group. In the signal state, when a certain sector of the one memory cell group is defective, the path for uniquely identifying the defective sector is cut off by the control of the sector switching means, and a predetermined state of the unused memory cell group is determined. A semiconductor memory device that conducts a path for specifying a normal sector. 6. The semiconductor memory device according to claim 1, wherein said block decoding means directly inputs an output of said group selection / address signal output means to a NAND circuit. A signal input to the NAND circuit via a NOT circuit, the output of the signal input directly to the NAND circuit is branched into two paths, and these are output via a transfer gate. Through N
The output of the signal input to the AND circuit is output via a transfer gate, the output is branched into two paths, and the output of the signal input directly to the NAND circuit is split into two paths, via the transfer gate. By controlling ON / OFF of these transfer gates by the sector switching means, the predetermined address is specified by a signal output through the transfer gate. Semiconductor storage device.