JP3081387B2 - Successive approximation type AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type AD converter.

[0002]

2. Description of the Related Art In order to control the operation of a device, a microcomputer incorporated in an electronic device, an industrial device, or the like fetches data when the device is in a certain state and performs predetermined arithmetic processing. The control to operate the equipment sequentially using the data is repeatedly performed. Here, it is common sense that the arithmetic processing by the microcomputer is performed in a binary number state. Therefore, there is no problem in performing the arithmetic processing by capturing a digital signal. However, the arithmetic processing is performed by capturing an analog signal. If input port and C
It is necessary to incorporate a so-called AD converter that converts an analog signal into a digital signal between the PU and a processing unit (PU).

There are types of AD converters, such as a successive approximation type and a batch comparison type, and among the successive approximation types, there are a type using a ladder resistor, a type using an integrator, and the like. Hereinafter, the successive approximation type AD converter using the latter integrator will be briefly described. For example, when converting an analog signal to an n-bit digital signal, a PWM signal generator capable of generating 2 ⁿ types of duty waveforms, an integrator for integrating the voltage Vdd according to the duty, and a comparison for comparing the analog signal and the integrated voltage Vessel. First, the PWM signal having a duty of 50% (high level 50%) is integrated, and the analog signal and the integrated voltage Vdd / 2 are compared. For example, when the analog signal is higher than the integration voltage Vdd / 2, the comparison result of "1" is held in the most significant bit of the n-bit register. Next, the analog signal is (Vdd / 2)
To Vdd), the duty is 75
% (High level 75%) of the PWM signal is integrated, and the analog signal and the integrated voltage 3Vdd / 4 are compared. For example, if the analog signal is smaller than 3Vdd / 4,
The comparison result of “0” is held in the upper 2 bits of the n-bit register. Next, the analog signal is (Vdd / 2-3V).
dd / 4), the duty 6
The 2.5% PWM signal is integrated, and the analog signal and the integrated voltage 5 Vdd / 8 are compared. For example, when the analog signal is larger than the integrated voltage 5Vdd / 8, the comparison result of "1" is held in the upper 3 bits of the n-bit register. Hereinafter, the same operation is repeated up to the least significant bit of the n-bit register to generate an n-bit digital signal. Then, the digital signal is taken into the CPU and predetermined arithmetic processing is performed.

When the voltage Vdd is integrated, it is desirable to generate an integrated voltage to be compared with an analog signal in a short time. For this purpose, the integration time constant may be reduced, but in this case, a large ripple is superimposed on the integration voltage during the integration process, and it takes a considerable time for the ripple to disappear from the integration voltage even after the integration is completed. There's a problem. That is,
There is a problem that accurate AD conversion cannot be performed because the integrated voltage is unstable. Therefore, conventionally, the time constant of the integrator is increased so that a stable integrated voltage can be supplied.

[0005]

However, when the time constant of the integrator is increased, there is a problem that the comparison time between the analog signal and the integrated voltage is prolonged and the AD conversion time is delayed. Therefore, an object of the present invention is to provide a successive approximation type AD converter that can surely perform AD conversion in a short time.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a successive approximation type AD converting an analog signal into an n-bit digital signal. In the converter, a PWM signal generator capable of generating 2 ⁿ types of duty waveforms, a first charging circuit having a first time constant and performing charging in accordance with the duty of the PWM signal, and charging the first charging circuit The second element has a second time constant (> first time constant), and the PWM
A second charging circuit that performs charging according to the duty of the signal;
A charging switching circuit that switches a charging operation from the first charging circuit to the second charging circuit in a charging process of the charging element;
A discharging circuit that discharges a charging voltage of the charging element, a comparator that compares the analog signal and a charging voltage of the charging element, and sequentially generates n types of control signals according to a comparison output of the comparator, Control for feeding back the control signal to the PWM signal generator, the charge switching circuit, and the discharge circuit in order to control the duty of the PWM signal, the switching of the charging time constant of the charging element, and the discharging of the charging element. A signal generator; and an n-bit register that sequentially holds the comparison output of the comparator from the upper bits in synchronization with the n types of control signals.

[0007]

According to the present invention, the charging operation is switched from the first charging circuit having a large time constant to the second charging circuit having a small time constant during the charging process of the charging element, so that a stable charging voltage can be supplied in a short time. As a result, reliable AD conversion can be performed in a short time.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a successive approximation type AD converter according to the present invention, which is an embodiment in which an analog signal is converted into an 8-bit digital signal. In FIG. 1, a capacitor (1) and a resistor (2) are a first charging circuit having a first time constant, and charge the power supply Vdd from time t0 to t1. The capacitor (1) and the resistor (3) are a second charging circuit having a second time constant.
Charge. Here, the value of the resistor (2) is set smaller than the value of the resistor (3), that is, the first time constant is smaller than the second time constant. (4) is a PWM signal generator capable of generating 256 (= 2 ⁸ ) kinds of duty waveforms. That is, the PWM signal generator (4)
PWM having a high period of an integral multiple of one cycle divided into 256
The signal is generated over a plurality of cycles. (5) is time t1
Is a charge switching circuit that switches the charging operation from the first charging circuit to the second charging circuit, generates a charge switching signal a of “1” at times t0 to t1, and a charge switching signal of “1” at times t1 to t2. b. The NAND gate (6) is opened when the charge switching signal a of “1” is generated, and the PW
Pass the M signal. Similarly, the NAND gate (7) is opened when the charge switching signal "b" of "1" is generated, and passes the PWM signal. The PMOS transistor (8) is connected to a power supply Vdd according to the output of the NAND gate (6).
And the first charging circuit is connected or disconnected. That is, when the PWM signal is high between times t0 and t1, the PMOS transistor (8) is turned on and the first charging circuit performs charging. Similarly, a PMOS transistor (9)
Is for connecting or disconnecting the power supply Vdd and the second charging circuit according to the output of the NAND gate (7). That is, when the PWM signal is high between times t1 and t2, P
When the MOS transistor (9) is turned on, the second charging circuit performs charging. Reference numeral (10) denotes a discharge circuit for instructing discharge of the charge stored in the capacitor (1), and a discharge instruction signal c of "1".
Occurs. The NMOS transistor (11) connects or disconnects the first charging circuit and the ground according to the discharge instruction signal c. That is, when the discharge circuit (10) instructs discharge, the electric charge stored in the capacitor (1) is discharged via the path of the resistor (2) and the NMOS transistor (11). Similarly, the NMOS transistor (12) connects or disconnects the second charging circuit and the ground according to the discharge instruction signal c. That is, when the discharge circuit (10) instructs discharge, the charge stored in the capacitor (1) is changed to the resistance (2) and N
Discharge occurs not only through the path of the MOS transistor (11) but also through the path of the resistor (3) and the NMOS transistor (12).

A comparator (13) compares the analog signal with the charging voltage of the capacitor (1). The analog signal is applied to the non-inverting input (+) terminal, and the inverting input (-).
The charging voltage of the capacitor (1) is applied to the terminal. That is, the comparator (13) generates a comparison output of "1" when the analog signal is higher than the charging voltage, and generates a comparison output of "0" when the analog signal is lower than the charging voltage. (14) is a control signal generator for sequentially generating eight types of control signals T1 to T8 in accordance with the comparison output of the comparator (13). The control signal generator converts the control signals T1 to T8 into a PWM signal generator (4) and a charge switch. It returns to the circuit (5) and the discharge circuit (10). Thus, every time the comparison output of the comparator (13) is generated, the PWM signal generator (4) determines the duty of the next PWM signal to be generated, and the charge switching circuit (5) switches the duty of the PWM signal from the second charge circuit. The charging operation is switched to the first charging circuit, and the discharging circuit (10) discharges the charging voltage of the capacitor (1). Also, AND gate (15)-
(22) opens when the timing signals T1 'to T8' go high in synchronization with the control signals T1 to T8, and passes the comparison output of the comparator (13). (23) is an 8-bit register which holds the outputs of the AND gates (15) to (22) sequentially from the upper bits.

The operation of FIG. 1 will be described below with reference to the characteristic diagram of FIG. In FIG. 2, the solid line indicates the charging voltage characteristic of the present embodiment, and the dashed line indicates the conventional charging voltage characteristic having a large time constant. First, at time t0, a PW with a duty of 50%
When the M signal is generated, the PMOS transistor (8) is turned on only during the high period of the PWM signal between times t0 and t1, so that the first charging circuit draws the steep solid line curve of FIG. Since the PMOS transistor (9) is turned on only during the high period of the PWM signal between times t1 and t2, the second charging circuit draws a gentle solid line curve in FIG. 2 instead of the first charging circuit to perform charging. As a result, a charging voltage of Vdd / 2 appears at both ends of the capacitor (1).
Here, in the charging process of the capacitor (1), the time constant is switched from small to large at the time t1 so that a stable charging voltage with a small ripple compared to the related art can be generated in a short time. After that, the analog signal and the charging voltage Vdd / 2
Are compared by a comparator (13). For example, when the analog signal is higher than the charging voltage Vdd / 2, the comparison result of "1" is output from the comparator (13), and the control signal generator (14)
Generates a control signal T1 corresponding to the comparison result. Then, a discharge instruction signal c of “1” is generated from the discharge circuit (10), and the electric charge stored in the capacitor (1) is changed to the resistance (2) and N
It is discharged through the path of the MOS transistor (11) and the path of the resistor (3) and the NMOS transistor (12). In addition, the PWM signal generator (4) outputs a duty of 75
% PWM signal is generated. After the discharge of the capacitor (1) is completed, the charge switching circuit (5) returns "1" again.
Is generated. On the other hand, the comparison result of "1" is output to the 8-bit register (2) through the AND gate (15).
3) is held in the most significant bit MSB.

Next, based on the PWM signal having a duty of 75%, the first and second charging circuits perform charging by drawing a solid line curve similar to that of FIG.
A charging voltage of 4 appears. Then, the analog signal and the charging voltage 3Vdd / 4 are compared by the comparator (13). For example, when the analog signal is smaller than the charging voltage 3Vdd / 4, the comparator (13) outputs a comparison result of "0", and the control signal generator (14) generates a control signal T2 corresponding to the comparison result. Then, the discharge instruction signal c of “1” is generated from the discharge circuit (10), and the accumulated charge of the capacitor (1) is transferred to the path of the resistance (2) and the NMOS transistor (11) and the resistance (3) and the NMOS transistor (12). ) Is discharged through the path. Further, a PWM signal having a duty of 62.5% is generated from the PWM signal generator (4). Also,
After the discharge of the capacitor (1) is completed, the charge switching circuit (5) generates a charge switching signal a of "1" again. On the other hand, the comparison result of "0" is held in the upper 2 bits of the 8-bit register (23) via the AND gate (16). By repeating the above operation up to the least significant bit LSB of the 8-bit register (23), an 8-bit digital signal can be formed.

As described above, in the charging process of the capacitor (1), the charging operation is switched from the first charging circuit (1) (2) having a large time constant to the second charging circuit (1) (3) having a small time constant. Thus, a stable charging voltage can be supplied in a short time, and as a result, reliable AD conversion can be performed in a short time.

[0013]

According to the present invention, the charging operation is switched from the first charging circuit having a large time constant to the second charging circuit having a small time constant during the charging process of the charging element. As a result, there is obtained an advantage that reliable AD conversion can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a successive approximation type AD converter of the present invention.

FIG. 2 is a characteristic diagram showing charging characteristics of FIG.

[Explanation of symbols]

 (1) Capacitor (2) (3) Resistance (4) PWM signal generator (5) Charge switching circuit (10) Discharge circuit (13) Comparator (23) 8-bit register

Claims (2)

(57) [Claims] 1. A successive approximation type A / D converter for converting an analog signal into an n-bit digital signal, comprising: a PWM signal generator capable of generating 2 ⁿ types of duty waveforms; A first charging circuit that performs charging in accordance with a duty; and a second time constant (>) sharing a charging element of the first charging circuit.
A second charging circuit having a first time constant) and performing charging in accordance with the duty of the PWM signal; and switching the charging operation from the first charging circuit to the second charging circuit during the charging of the charging element. A charge switching circuit; a discharge circuit that discharges a charge voltage of the charge element; a comparator that compares the analog signal and a charge voltage of the charge element; and n kinds of control signals according to a comparison output of the comparator. The control signal is generated in order to control the duty of the PWM signal, switching of the charging time constant of the charging element, and discharging of the charging element, and the control signal to the PWM signal generator, the charging switching circuit, and the discharging. A control signal generator that feeds back to a circuit; and an n-bit register that sequentially holds the comparison output of the comparator from the upper bits in synchronization with the n types of control signals. Successive approximation type AD converter. 2. The successive approximation type A / D converter according to claim 1, wherein the analog signal is built in a microcomputer for performing predetermined arithmetic processing on the analog signal.