JP3081515B2 - Analog-digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog-to-digital converter (A / D converter), and more particularly, to an A / D converter having a multi-stage pipeline (step flash) configuration.
It concerns a converter.

[0002]

2. Description of the Related Art In recent years, with the development of digital processing technology for video signals, the demand for A / D converters for video signal processing has increased. Since a high-speed conversion operation is required for an A / D converter for video signal processing, a two-step flash (two-step parallel) method has conventionally been widely used.

However, with the increase in the number of conversion bits, sufficient conversion accuracy cannot be obtained with the two-step flash method. LSB (Least Significant)
Bit) is represented using the input voltage range (FSR; Full Scale Range) of the analog input signal and the number of bits N as shown in Expression (1).

1 LSB = FSR / 2 ^N (1) For example, when the number of bits is 10 bits and the FSR is 2 V,
From equation (1), LSB is 2 mV. Thus, LSB
Is smaller, the resolution of each comparator constituting the two-step flash A / D converter is limited, and it is difficult to obtain sufficient conversion accuracy. As a practical matter, obtaining 9 bits or more by the two-step flash method is not practical.

Accordingly, an A / D converter having a multi-stage pipeline configuration in which each stage includes an A / D converter, a digital-analog conversion circuit (D / A converter), and a difference amplifier has been developed.

In the operation, first, A / D conversion is performed on an analog input signal using an A / D converter of the first stage. Next, the A / D conversion result of the first-stage A / D converter is added to the first-stage D / A converter to perform D / A conversion. Subsequently, the D / A conversion result of the first stage D / A converter and the analog input signal are added to the first stage difference amplifier,
Amplify the difference. The output of the first-stage difference amplifier is subjected to A / D conversion using the second-stage A / D converter. Next, the A / D conversion result of the second-stage A / D converter is added to the second-stage D / A converter to perform D / A conversion. Subsequently, the D / A conversion result of the second stage D / A converter and the output of the first stage difference amplifier are added to the second stage difference amplifier to amplify the difference. Thereafter, the same operation is sequentially performed in each stage. However, the last stage includes only an A / D converter, and A / D converts the output of the difference amplifier of the preceding stage.
For example, in a three-stage pipeline configuration, the A / D of the first to third stages
The number of bits (bit configuration) of the converter is a,
In the case of b and c, digital output of the upper a bits from the first-stage A / D converter, the middle b bits from the second-stage A / D converter, and the lower c bits from the third-stage A / D converter Is obtained.

In the pipeline operation, when the A / D converter in the m-th stage is performing A / D conversion sampling, the D / A converter in the (m + 1) -th stage performs D / A conversion. That is, in the pipeline operation, the operation of each adjacent stage is different, and the odd and even stages perform different operations.

In each stage, an A / D converter and D
The number of bits (bit configuration) n of the / A converter is set to be the same. In addition, the A / D converter of each stage has an A / D converter.
It is called a sub A / D converter to distinguish it from the whole D converter. The sub-A / D converter uses an all-parallel comparison (flash) system capable of high-speed conversion operation.

As described above, in the multi-stage pipeline configuration, in each stage, the difference between the analog input signal or the output of the difference amplifier of the preceding stage and the D / A conversion result of the digital output of the stage is determined by the difference of the stage. It is amplified by the difference amplifier. Therefore, even when the number of conversion bits increases and the LSB decreases, the resolution of each comparator constituting the A / D converter can be substantially improved, and sufficient conversion accuracy can be obtained.

[0010]

An A / D converter having a multi-stage pipeline configuration has the following problems. The output of the preceding stage difference amplifier is used as is in the next stage sub A / D
Transfer to converter and difference amplifier. Therefore, when the differential amplifier at the preceding stage enters the amplifier operation, there is a possibility that the differential amplifier is affected by switching noise from the sub-A / D converter or the differential amplifier at the next stage.

In the multi-stage pipeline configuration, since the characteristics of the differential amplifier greatly affect the A / D conversion, a differential amplifier that has a constant gain, high stability, high accuracy, and high-speed operation is required. Therefore, an operational amplifier having a negative feedback capacitance (capacitor in a closed loop) must be used as the difference amplifier.

Therefore, switching noise from the next-stage sub-A / D converter or difference amplifier tends to affect the negative feedback capacitance, causing a decrease in accuracy and operation speed of the difference amplifier.

In order to avoid this problem, it is necessary to make the output impedance of the difference amplifier sufficiently low. However, in order to lower the output impedance, the size of the output transistor of the difference amplifier must be increased. As a result, a through current flowing through the output transistor increases, and power consumption increases.

When an analog circuit such as a sub A / D converter, a D / A converter, and a difference amplifier is configured by CMOS logic, it is necessary to provide a bias generation circuit for the analog circuit.

For example, as shown in FIG. 4, an analog circuit 101 is a differential circuit 102 composed of CMOS logic.
Is provided, a bias generation circuit 103 for generating bias voltages Vb1 and Vb2 to be supplied to the differential circuit 102 is provided. That is, the PMOS of the differential circuit 102 is used as a load.
To operate the transistor 104, it is necessary to apply a bias voltage Vb1 to its gate. Further, in order to operate the NMOS transistor 105 as a constant current source of the differential circuit 102, it is necessary to apply the bias voltage Vb2 to its gate. Therefore, a bias generation circuit 103 having a replica configuration is provided for the differential circuit 102 to generate the bias voltages Vb1 and Vb2.

By the way, a multi-stage pipeline configuration A
In the / D converter, a bias voltage is supplied from one bias generation circuit to the analog circuits in each stage. Therefore, the bias voltage tends to become unstable under the influence of the switching noise generated by the analog circuit in each stage. When the bias voltage becomes unstable, the A / D conversion accuracy decreases.

In order to avoid this problem, it is necessary to sufficiently lower the output impedance of the bias generation circuit.
However, in order to reduce the output impedance of the bias generation circuit, the size of the transistors (the transistors 106 to 108 shown in FIG. 4) constituting the bias generation circuit must be increased. As a result, a through current flowing through a transistor constituting the bias generation circuit increases, and power consumption increases.

The present invention has been made to solve the above problems.
The purpose was to achieve high precision and low power consumption.
To provide a power-saving analog-to-digital conversion circuit
is there.

[0019]

According to the present invention, each stage has an analog
G-digital conversion circuit and digital-analog conversion circuit
Multistage pipeline consisting of differential amplifier with negative feedback capacitance
With a variable impedance unit between each stage.
The impedance variable means is provided at least in the preceding stage.
After the amplifier operation of the difference amplifier starts,
High impedance state until the output stabilizes
The main point is to take

In this case, the impedance variable means
Is constituted by a transmission gate,
The transmission gate is off during the period and output
It is desirable to turn on after stabilization.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block circuit of an A / D converter 1 having a four-stage pipeline configuration according to the present embodiment.

The A / D converter 1 includes a sample hold circuit 2, first to fourth stage circuits 3 to 6, a latch circuit 7,
It comprises an output circuit 8, a transmission gate 21, and a transmission gate control circuit 22.

The circuits 3 to 5 in the first to third stages include a sub A /
D converter 9, D / A converter 10, difference amplifier 1
1 is provided.

The fourth-stage (final-stage) circuit 6 includes only the sub A / D converter 9.

The first-stage (initial-stage) circuit 3 has a 4-bit configuration,
The circuits 4 to 6 in the second to fourth stages each have a 2-bit configuration.

In the first to third stage circuits 3 to 5, the sub A
The number of bits (bit configuration) n of the / D converter 9 and the D / A converter 10 are set to be the same. In addition, 2
Each of the circuits 4 to 6 in the fourth stage has one or more redundant bits.

The sub A / D converter 9 uses a flash method. The circuits 3 to 6 at each stage are connected by a transmission gate 21 composed of an NMOS transistor. The on / off operation of each transmission gate 21 is controlled by a transmission gate control circuit 22.
Is controlled by

The difference amplifier 11 is constituted by an operational amplifier OP, and has an input capacitance C1 and a negative feedback capacitance (closed loop capacitor) C2. Next, the operation of the A / D converter 1 will be described.

The sample hold circuit 2 samples the analog input signal Vin and holds it for a certain time. Analog input signal Vin output from sample and hold circuit 2
Is transferred to the first stage circuit 3.

In the first stage circuit 3, the sub A / D converter 9 performs A / D conversion on the analog input signal Vin. The upper 4 bits of the digital output (2 ⁹ , 2 ⁸ , 2 ⁷ , 2 ⁶ ) as the A / D conversion result of the sub A / D converter 9 are
The data is transferred to the D / A converter 10 and to the output circuit 8 via the four latch circuits 7. The difference amplifier 11 amplifies the difference between the D / A conversion result of the D / A converter 10 and the analog input signal Vin. The output of the difference amplifier 11 is transferred to the second stage circuit 4 via the transmission gate 21.

In the circuit 4 of the second stage, the same operation as that of the circuit 3 of the first stage is performed on the output of the difference amplifier 11 of the circuit 3 of the first stage. Then, a digital output (2 ⁵ , 2 ⁴ ) of the middle and upper 2 bits is obtained from the second stage circuit 4.
The output of the difference amplifier 11 of the second-stage circuit 4 is transferred to the third-stage circuit 5 via the transmission gate 21.

In the circuit 5 in the third stage, the same operation as in the circuit 3 in the first stage is performed on the output of the difference amplifier 11 of the circuit 4 in the second stage. Then, a digital output (2 ³ , 2 ² ) of middle and lower 2 bits is obtained from the third stage circuit 5.
The output of the difference amplifier 11 of the third-stage circuit 5 is transferred to the fourth-stage circuit 6 via the transmission gate 21.

In the circuit 6 of the fourth stage, the sub-A / D converter 9 performs A / D conversion on the output of the difference amplifier 11 of the circuit 5 of the third stage, and outputs the lower 2 bits of digital output (2 ¹ , 2 ⁰ ) are obtained.

The digital outputs of the circuits 3 to 6 of the first to fourth stages reach the output circuit 8 via the respective latch circuits 7 at the same time. That is, each latch circuit 7 is provided for synchronizing digital outputs of the circuits 3 to 6.

The output circuit 8 outputs 1 of the analog input signal Vin.
A 0-bit digital output Dout is output in parallel. FIG. 2 shows a timing chart of the A / D converter 1.

Each transmission gate 21 is turned off before the output of the differential amplifier 11 of the preceding circuits 3 to 5 is stabilized, and is turned on after the output is stabilized. That is, the nodes a and b between the circuits 3 to 6 in the first to fourth stages are in a high impedance state before the output of the differential amplifier 11 in the circuits 3 to 5 in the previous stage is stabilized, and the output is stabilized. It will be in a low impedance state later. Therefore, 1-4
The nodes a and b between the circuits 3 to 6 in the stage are connected to the differential amplifier 1 in the circuits 3 to 5 in the preceding stage with a delay of a predetermined time t defined by the OFF → ON operation of the transmission gate 21.
An output of 1 appears.

Therefore, when the difference amplifier 11 of the preceding circuits 3 to 5 enters the amplifier operation, even if the sub-A / D converter 9 or the difference amplifier 11 of the next circuits 4 to 6 generates switching noise, There is no possibility that the difference amplifier 11 of the circuits 3 to 5 in the preceding stage is affected by the difference amplifier.

FIG. 3 shows a connection relationship between the A / D converter 1 and the bias generation circuit 31. The A / D converter 1 and the bias generation circuit 31 are formed on one semiconductor chip 32 and are on-chip. The bias generation circuit 31 includes an internal circuit of the A / D converter 1 (2 to 6, 8,
22) The replica configuration is adopted, and a plurality of bias voltages required by the internal circuit are generated. Each bias voltage is supplied to the A / D converter 1 via each bias voltage line 33. That is, a bias voltage is supplied to each internal circuit of the A / D converter 1 via each common bias voltage line 33.

Each bias voltage line 33 is decoupled by each capacitor 34. Therefore, each bias voltage is fixed and stabilized by the capacitance of each capacitor 34.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) By adopting a multi-stage pipeline configuration, each stage circuit 3
5, the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage and the circuits 3 to 5 of that stage.
Is amplified by the difference amplifier 11. Therefore, even if the number of conversion bits increases and the LSB decreases, it is possible to substantially improve the resolution of each comparator constituting the flash sub-A / D converter 9 and obtain sufficient conversion accuracy. Can be

(2) Difference amplifier 11 of circuits 3 to 5 at the preceding stage
However, there is no possibility of being affected by switching noise from the circuits 4 to 6 in the next stage. Therefore, the above-mentioned problem can be avoided.

That is, in the multi-stage pipeline configuration, since the characteristics of the difference amplifier 11 greatly affect the A / D conversion, the difference amplifier 11 having a constant gain, high stability, high accuracy, and high-speed operation is required. is there. Therefore, the operational amplifier OP having the negative feedback capacitance C2 must be used as the difference amplifier 11. However, the sub-A of the next-stage circuits 4 to 6
When the / D converter 9 or the difference amplifier 11 generates switching noise, the negative feedback capacitance C2 of the difference amplifier 11 of the circuits 3 to 5 at the preceding stage is affected by the switching noise, and the accuracy and operation speed of the difference amplifier 11 may be reduced. There is.

However, in the present embodiment, the circuits 4 to
6 is not affected by the switching noise, the output impedance of the difference amplifier 11 does not need to be so low. Therefore, the difference amplifier 11
It is possible to reduce the size of the output transistor, and the through current flowing through the output transistor is reduced, so that power consumption can be reduced.

(3) Since the bias voltage is stabilized, A
The conversion accuracy of the / D converter 1 is improved. Therefore, the above-mentioned problem can be avoided. That is, in the present embodiment, since the bias voltage is fixed by the capacitor 34, the output impedance of the bias generation circuit 31 does not need to be so low. Therefore, it is possible to reduce the size of the transistor forming the bias generation circuit 31, and to reduce the through current flowing through the transistor, thereby reducing power consumption.

The capacity of the capacitor 34 is several pF.
Is enough. Therefore, the capacitor 34 can be formed using the parasitic capacitance between the metal wiring and the polysilicon wiring or between the metal wirings, or using the gate capacitance of the transistor forming the bias generation circuit 31. Therefore, there is no need to provide a special manufacturing process for forming the capacitor 34, and the manufacturing cost does not increase. Further, the provision of the capacitor 34 does not hinder high integration of the semiconductor chip 32. That is, A /
D converter 1, bias generation circuit 31, capacitor 3
4 can easily be made on-chip.

The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case. (1) The present invention is applied to a fully differential type difference amplifier 11. In this case, it is necessary to provide transmission gates 21 corresponding to the positive and negative outputs of difference amplifier 11, respectively.

(2) Set the transmission gate 21 to P
It is composed of MOS transistors or CMOS. As in the above embodiment, the transmission gate 21 is NM
In the case of using only the OS, although good characteristics are exhibited for low-level propagation, high-level propagation becomes a source follower type, and a voltage drop corresponding to the threshold voltage of the NMOS occurs. Further, when the transmission gate 21 is constituted only by the PMOS, the propagation at the high level is excellent, but the propagation at the low level is inferior. On the other hand, if the transmission gate 21 is formed of CMOS, excellent transmission characteristics are exhibited at both high and low levels.

(3) The sub A / D converter 9 is embodied by a method other than the flash method. (4) Not only an A / D converter having a multi-stage pipeline configuration but also an A / D converter including an analog circuit to which a bias voltage is supplied from a bias generation circuit is turned on by the bias generation circuit and the analog circuit. A capacitor 34 is provided as a chip.

[0050]

【The invention's effect】 According to the present invention as described in detail above,
Providing accurate and low power consumption analog-to-digital conversion circuit
Can be offered.

[0051]

[0052]

[0053]

[0054]

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment.

FIG. 2 is a timing chart of one embodiment.

FIG. 3 is a circuit diagram showing a connection relationship between a bias generation circuit and an A / D converter.

FIG. 4 is a circuit diagram of a bias generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... A / D converter 3 ... 1st stage circuit 4 ... 2nd stage circuit 5 ... 3rd stage circuit 6 ... 4th stage circuit 9 ... Sub A / D converter 10 ... D / A converter 11 ... Difference Amplifier 21 ... Transmission gate 31 ... Semiconductor chip 32 ... Semiconductor chip 33 ... Bias voltage line 34 ... Capacitor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (2)

(57) [Claims] 1. A each stage analog - digital converter and a digital - taking a multistage pipeline structure consisting of the difference amplifier with analog conversion circuit and a negative feedback capacitor, between the stages
An impedance variable means, the impedance
The changing means is that at least the amplifier operation of the preceding differential amplifier is
From the start until the output of this difference amplifier stabilizes
An analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit is in a high impedance state . 2. The method according to claim 1, wherein said impedance varying means includes a transformer.
The transmission gate
The output gate is off during the period and the output is stable
2. The analog according to claim 1, which is turned on later.
G-digital conversion circuit.