JP3082500B2 - Pattern superposition coding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-dimensional coding MH system (Modified Huffman system) or a two-dimensional coding MMR system (Modified, Modified) which is used for facsimile or the like by superimposing a plurality of still images. The present invention relates to an improvement of a pattern superimposition encoding circuit that performs encoding of a read method.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a main part of a conventional pattern superposition coding circuit. In FIG. 4, the processor 1
1 ′ reads the pattern 1 and the pattern 2 from the memories 3 ′ and 4 ′ of the superimposition processing unit 13 that store the pattern 1 and the pattern 2 respectively, performs a logical sum in the logical sum circuit 7, and stores the superimposed pattern data. The data is written to the memory 5 '.

The superimposed data stored in the memory 5 'is read out, and the encoding processing unit 8' performs an encoding process of the MH or MMR system.

[0004]

However, since the information amount of the data of the pattern 1, the pattern 2 and the superimposed pattern is generally large, the processor 11 'accesses the memories 3', 4 'and 5'. However, there is a problem that the load on the processor 11 'becomes heavy, and the amount of other processing performed by the processor 11' in parallel with the above processing is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern superimposition coding circuit which can reduce the load on a processor and increase the amount of other processing to be performed in parallel.

[0006]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG.
MA controller 12; first memory 1 storing pattern 1; second memory 2 storing pattern 2 having the same configuration as first memory 1; and sixth memory 6 for writing encoded data And third and fourth memories 3 and 4 for transferring patterns 1 and 2, a logical sum circuit 7 for performing a logical sum of data read from the third and fourth memories 3 and 4 and superimposing the same, And the processor 11 for writing the
When there is a start instruction, patterns 1 and 2 are transferred to the third and fourth memories 3 and 4, patterns 1 and 2 are read from the third and fourth memories 3 and 4, and the OR circuit is read. 7, an encoding circuit 10 having an encoding processing unit 8 for writing the superimposed data in the fifth memory 5 and encoding the superimposed data.
Instructed the DMA control unit 12 to transfer the contents of the first and second memories 1 and 2 to the third and fourth memories 3 and 4, and coded the data by the coding processing unit 8. An instruction to transmit and store the encoded data in the sixth memory 6 is output, and a start signal is output to the encoding circuit 10.

[0007]

According to the present invention, the processor 11 instructs the DMA controller 12 to transfer the contents of the first and second memories 1 and 2 to the third and fourth memories 3 and 4, and An instruction to transmit and store the encoded data encoded by the encoding processing unit 8 in the sixth memory 6 is sent, and a start signal is sent to the encoding circuit 10.

Then, the data of pattern 1 and pattern 2 stored in the first and second memories 1 and 2 are directly transferred to and stored in the third and fourth memories 3 and 4 under the control of the DMA controller 12. Is done.

At this time, since the encoding processing unit 8 is activated, the transferred pattern 1 and pattern 2 are read from the third and fourth memories 3 and 4 and the data superimposed by the OR circuit 7 is written. It is stored in the fifth memory 5 and encoded.

[0010] Once encoded, the encoded data is DM
The data is sent to and stored in the sixth memory 6 under the control of the A control unit 12. That is, since the processor 11 only issues an instruction and does not perform processing for accessing the memories 1, 2, and 5, the load is light and the amount of other processing to be performed in parallel can be increased.

Since the fifth memory 5 is provided in the encoding circuit 10, when the encoding processing unit 8 performs MMR encoding, it is possible to perform a process of referring to the data of the previous line.

[0012]

FIG. 2 is a block diagram of a pattern superposition encoding circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing a main part of the encoding operation sequence of FIG.

In FIG. 2, the microprocessor 11, DM
A control unit 12, memories 1 and 2 storing patterns 1 and 2 and a memory unit 14 having a memory 6 storing coded data, coding processing LSI 8, coding circuit control unit 15, pattern 1 , Memory for transferring pattern 2, memory for writing superimposed data 5, OR circuit 7, address counters 16, 17, selectors 18, 1
9, an encoding circuit 10 having an OR circuit 20.

An address bus and a data bus for controlling the DMA controller 12 and the encoding circuit 10 are connected to the microprocessor 11 respectively. The DMA control unit 12 receives DREQn as a data transfer request signal from the encoding circuit 10 and DACKn (n = 1 to 1) of a transfer permission signal.
The signal lines of 3) are respectively connected.

The processing procedure is as follows. 1. When the data of pattern 1 and pattern 2 are stored as superimposition processing data in the memories 1 and 2 of the memory unit 14, the setting from the microprocessor 11 to the DMA control unit 12 (memory 1, 2, the data transfer start address and the number of data transfer bytes are set for each DMA channel), and as shown in FIG. 3, the settings are made in the coding circuit control unit 15 [whether there is superimposition, the type of code (MH,
MMR), setting of encoding processing unit], and the encoding circuit 10 is started.

2. The activated encoding circuit 10 sends a data transfer request signal DREQn (n) to the DMA control unit 12.
= 1 and 2) to output patterns 1 and 2 in memories 1 and 2
Request for transfer.

3. As shown in FIG. 3, the DMA control unit 1
The data of the patterns 1 and 2 transferred by 2 are written to the memories 3 and 4 in the encoding circuit 10. At this time DMA
The address counters 16, 17 are counted up by the DACKn (n = 1, 2) signal output from the control unit 12 and given as addresses of the memories 3, 4. Then, the pattern data in the memories 1 and 2 is transferred from the address 0 to the memories 3 and 4.

4. When the transfer of the pattern data by the DMA control unit 12 is completed, the coding circuit control unit 15 enables the coding process LSI 8 to enable the coding process LSI.
8 (the DMA transfer ends when the DMA control unit 12
Transfer permission signal DACKn (n = 1, 2) output from
And a transfer end signal * EOP output at the same timing. ).

5. When the encoding process LSI 8 is started,
As shown in FIG. 3, address 0 is output to memories 3 and 4 via selectors 18 and 19,
4 to read data.

The data output from the memories 3 and 4 are input to the OR circuit 7 by being read by the encoding processing LSI 8, and are superimposed by the OR circuit 7 and are encoded.
Captured at I8.

At this time, the data fetched by the encoding processing LSI 8 is written into the memory 5 (memory for reference data at the time of MMR encoding). The encoding processing LSI 8 sequentially reads the addresses from addresses 0 of the memories 3 and 4, and supplies the addresses to the memory 5, and the superimposed data from the address 0 is sequentially written into the memory 5.

6. At the time of MMR encoding, the encoding process LSI 8 reads out the memory 5 (where superimposed data of the previous line written at the time of the previous line process is stored) and performs an encoding process to obtain a difference from the previous line (FIG. In the case of 2,
0000h of the address output by the encoding processing LSI 8
Addresses up to address 7FFFh are allocated as address areas of memories 3 and 4, and addresses 8000h to FFFFh are allocated as address areas of memory 5 so that memories 3 and 4 and memory 5 can be distinguished.

In the case of MH coding, the coding process is performed using the data taken in by the coding process LSI 8. 7. The encoded data is edited in the encoding process LSI 8 in byte units, stored in an output buffer, and outputs a data transfer request DREQ3 to the DMA control unit 12, as shown in FIG. The unit 12 reads the encoded data from the encoding processing LSI 8 and
When the coding is completed in the memory 6 of FIG. 4 and the coding is completed, an interrupt signal (INTR) is output from the coding processing LSI 8 to the microprocessor 11 as a processing completion notice, and the processing is terminated, as shown in FIG. I do.

8. If the pattern data stored in the memories 1 and 2 of the memory unit 14 is larger than the capacity of the memories 3 and 4 in the encoding circuit 10, the pattern data is divided into some blocks and transferred and superimposed from the memories 1 and 2. Since the encoding process LSI 8 completes the encoding process of one block of the pattern data stored in the memories 3 and 4, the encoding process LSI 8 An interrupt signal (IN
TR) is output to notify the microprocessor 11.

9. Microprocessor 11 that has been notified
Resets the address of the pattern data continued from the previously processed data and the number of transfer bytes to the DMA control unit 12, and executes the coding circuit control unit 15 and the coding process L.
The setting is also made for SI8.

In the case of FIG. 2, when performing the second or subsequent block processing, the coding start address is set to address 0 (always 〇 including the first processing), and the coding reference address is set to the previous block. An address obtained by adding 8000h (base address of the reference memory 5) to an address obtained by subtracting one line from the completed address is set in the encoding processing LSI 8, and re-processing is performed. This is repeated until the encoding process is completed.

As described above, the access to the memory unit 14 connected to the system bus can be minimized, and the processing of the microprocessor 11 can be reduced as compared with the conventional example. Can be increased.

[0028]

As described above in detail, according to the present invention, there is an effect that a pattern superposition encoding circuit capable of reducing the load on the processor and increasing the amount of other processing performed by the processor in parallel can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention;

FIG. 2 is a block diagram of a pattern superposition encoding circuit according to an embodiment of the present invention;

FIG. 3 is a diagram showing a main part of an encoding operation sequence in FIG. 2;

FIG. 4 is a block diagram of a main part of a conventional pattern superposition encoding circuit.

[Explanation of symbols]

1 to 6, 3 'to 5' are memories, 7 is an OR circuit, 8 is an encoding processing unit, an encoding LSI, 8 'is an encoding processing unit,
10 is an encoding circuit, 11 is a processor, a microprocessor, 11 'is a processor, 12 is a DMA control unit 13, a superposition processing unit, 14 is a memory unit, 15 is an encoding circuit control unit, 16 and 17 are address counters, 18 , 19 are selectors, and 20 is an OR circuit.

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 1/417 G06F 15/66 330A (72) Inventor Ryoetsu Nakajima 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) Document JP-A-4-267767 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/40-1/419 G06T 1/60 G06T 9/00 H03M 7/40 H04N 1 / 387

Claims (1)

(57) [Claims] 1. A processor (11), a DMA controller (12), and a first memory (1) storing a pattern 1
A second memory (2) having the same configuration as the first memory and storing pattern 2; and a sixth memory (2) for writing encoded data.
Memory (6), and third and fourth memories (3,
4) a logical sum circuit (7) for performing a logical sum of data read from the third and fourth memories (3, 4) and superimposing the logical sum;
When there is an activation instruction from the fifth memory (5) for writing superimposition data and the processor (11) and the patterns 1 and 2 are transferred to the third and fourth memories (3, 4), the Third, the patterns 1 and 2 are read from the fourth memory (3, 4), the data superimposed by the OR circuit (7) is written into the fifth memory (5), and the encoding process of the superimposed data is performed. Encoding unit (1) having an encoding processing unit (8)
0), and the DMA controller (12) is provided by the processor (11).
An instruction to transfer the contents of the first and second memories (1, 2) to the third and fourth memories (3, 4), and an encoding process performed by the encoding processing unit (8). A pattern superimposing encoding circuit characterized by outputting an instruction to transmit and store the encoded data in the sixth memory (6), and outputting a start signal to the encoding circuit (10). .