JP3082579B2 - Shield case - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for removing interference caused by harmonics of waveforms such as clocks and data generated from an LSI by using a ground pattern of a package and a main board.

[0002]

2. Description of the Related Art In recent years, with the increase in the speed of digital LSIs, it has been desired to improve the interference countermeasure technology by increasing the frequency of harmonics of waveforms such as clocks and data generated by the LSI and increasing the power.

Hereinafter, a conventional shield structure will be described. FIG. 5A shows a conventional shield structure. In FIG. 5A, reference numeral 1 denotes a circuit board on which an LSI is mounted, and 2 denotes a QFP (quad flat package).
e) Type LSI, 3 is a shield case, 4 is a feedthrough capacitor.

In FIG. 5B, the structure of the feedthrough capacitor 4 is shown by a signal electrode 7, a dielectric 5, and a ground electrode 6, and is soldered to the shield case 3 of FIG. With this structure, the cause of interference is shielded.

[0005]

However, in the above-mentioned conventional configuration, since the QFP type LSI 2 is used, it is necessary to cover the entire circuit board with a shield case as shown in FIG. The capacitor 4 needs to be soldered to the shield case 3, so that the workability is poor and a large shield case is required, so that it is difficult to reduce the cost.

The present invention solves the above-mentioned conventional problems, and has the same effect as the conventional shield case 3 by dividing the conventional shield case 3 into the package of the LSI 2 and the surface pattern of the circuit board 1. It is intended to provide a shielded configuration.

[0007]

In order to achieve this object, a shield case according to the present invention comprises a surface mount type multi-terminal LS.
I package (hereinafter referred to as BGA (ballgrid
array)), in a BGA package having two or more wiring pattern layers inside the package, connection terminals (solder balls) on four sides of the BGA outer peripheral portion.
Are all allocated to the ground terminals, and the ground pattern further covers the outer peripheral four sides of the wiring pattern on which the bare chip on the opposite side of the connection terminal is mounted, and the BGA
In a BGA package in which connection terminals on the four sides of the outer periphery and ground patterns on the four sides of the outer periphery on the wiring pattern on which the bare chip is mounted are connected by through holes,
A plurality of BGA packages each having a bare chip covered by shielding means are connected to a pattern in which the outer peripheral four sides are further covered with a ground pattern in a wiring pattern on which a bare chip on the opposite side of the connection terminal of the GA package is mounted. In the inner via board of three or more layers, the pattern on the front and back of the board is set as the entire ground (however, the inner terminals except for the ground connection terminals on the four sides of the outer periphery of the BGA of the pattern mounting the BGA package have three or more layers) Is connected to the inner layer pattern of the inner via type main substrate by the inner via.

In order to further enhance the effect of removing interference from the above structure, in a BGA package, a substrate for forming a pattern layer inside the package is removed from a pad of a bare chip by using a ceramic lamination technique and a ferrite lamination technique. Are formed between the connection terminals (solder balls).

[0009]

According to this configuration, in the two-layer or more wiring pattern mounting the bare chip inside the BGA package, the four sides of the outer periphery of the BGA on the surface where the bare chip is mounted are grounded. Connection terminals (solder balls) for connection to a main board on which a plurality of BGA packages are mounted are arranged on the wiring pattern surface opposite to the ground pattern on the wiring pattern surface. The connection terminals (solder balls) on the sides are connected to the outer peripheral ground of the surface on which the bare chip is mounted by through holes.

Further, in this BGA package, the outer peripheral ground pattern on the surface on which the bare chip is mounted is shielded by a shield means surrounding the bare chip, and connected to the outer peripheral ground, thereby forming a BGA.
The shield of the package is shielded except for the connection terminals (solder balls) except for the connection terminals (solder balls) on the outer peripheral portion with the main board.

Next, in a multi-layer board having three or more layers of the main board, the front and back patterns are entirely covered with a ground pattern (however, the connection terminals except for the connection terminals (solder balls) on the outer peripheral portion of the BGA package are used). The connection portion has a connection pattern.) Further, by using an inner via type through hole for connection of the main board, shielding can be performed without using a shield case on the board together with the BDA package. .

[0012]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1A, reference numeral 8 denotes a wiring board for forming a BGA, 9 denotes a bare chip, 10 denotes a ground pattern, 11 denotes connection terminals (solder balls), and 26 denotes through holes. In the BGA package configured as above, bare. The chip 9 is mounted with the substrate facing upward (when the substrate is connected to the ground), as shown in FIG. 1 (b) (FIG. 1 (a) viewed from the direction of A). The connection terminal (solder ball) 13 is shielded except for the portion.

However, unless the pitch of the ground connection terminals (solder balls) 14 (B in FIG. 1B) is narrow to some extent, there is no shielding effect. Normal BGA pitch (Fig. 1
P) of (b) has almost no problem because 1 to 1.5 mm is adopted.

(Embodiment 2) Referring to FIG.
In order to enhance the shielding effect of the BGA, a structure in which a metal shield case 12 is attached as an example of a shield means on the upper side of the bare chip is shown. Further, the same effect can be obtained by applying a conductive resin or paint to the surface of the bare chip 9 instead of the shield case.

(Embodiment 3) In FIG. 3A, 15 is a main board (three layers or more) on which a BGA package is mounted.
Reference numeral 16 denotes a ground plane on which the BGA package of the first embodiment is mounted. At this time, a signal / power supply connection terminal 18 inside a main board ground connection terminal 17 to be soldered to a ground connection terminal (solder ball) 14 on the outer peripheral portion of the BGA package.
Is insulated from the entire ground 16. further,
The through hole of the main board 15 is an inner via 19 as shown in FIG. Of course, the main board 15
Is connected to the front and back grounds 16 at a pitch of 1 to 1.5 mm.

(Embodiment 4) In FIG. 4, in order to further enhance the effect of removing interference, the wiring board 8 for forming the BGA of Embodiment 1 is formed by the ferrite lamination technology and the dielectric lamination technology, and the wiring for forming the BGA is formed. It is possible to attenuate harmonics by forming a filter inside the substrate 8. This structure will be described with reference to FIG.

Referring to FIG. 4, a case where a T-type filter is formed will be described. FIG. 4 is a cross-sectional view when the wiring board 8 forming the BGA is formed by a ferrite and dielectric lamination technology. This cross section is composed of 20, 21 ferrite layers and 21 dielectric layers.
The electrodes 23 for forming L are provided inside 0 and 21, the electrodes 24 for forming capacitors are provided inside the dielectric layer 21, each of which is connected by a through hole. Is led to the connection terminal (solder ball) through the filter.

[0019]

As described above, according to the present invention, since a large number of grounds formed by through holes are provided on the BGA substrate and the main substrate, and the main substrate is multi-layered, there is no need to provide a separate shield case for countermeasures against interference. Workability in the factory is improved, and the front and back of the main board is grounded, so the stray capacitance of the board enters the inner layer pattern.Thus, there is no need for a penetrating capacitor, so a shield structure that can reduce cost and reduce man-hours It can be realized.

[Brief description of the drawings]

FIG. 1A shows a structure of a BGA package according to an embodiment of the present invention. FIG. 1B is a layout view of a ball grid array when the BGA package is viewed from the bottom.

FIG. 2 is a diagram showing a structure when the BGA package shielding means is applied.

FIG. 3A is a diagram showing a structure of a main board according to an embodiment of the present invention. FIG. 3B is a cross-sectional view of the main board.

FIG. 4 is a diagram showing a structure of a shield case according to another embodiment of the present invention.

FIG. 5A is a diagram showing a configuration of a shield case of a conventional example. FIG. 5B is a diagram showing a structure of a feedthrough capacitor used in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 board 2 QFP type LSI 3 shield case 4 feedthrough capacitor 5 dielectric 6 ground electrode 7 signal electrode 8 wiring board forming BGA 9 bare chip 10 ground pattern 11 connection terminal (solder ball) 12 shield case (an example of shield means) 13 signal / power connection terminal (solder ball) 14 ground connection terminal (solder ball) 15 main board 16 whole ground pattern 17 ground connection terminal 18 signal power supply connection terminal 19 inner via (through hole which does not penetrate) 20 ferrite layer 21 dielectric Layer 22 Ferrite layer 23 L forming electrode 24 Capacitor forming electrode 25 Bonding wire 26 Through hole

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-225145 (JP, A) JP-A-7-202477 (JP, A) JP-A-4-79352 (JP, A) JP-A-7-207 240595 (JP, A) JP-A-5-182720 (JP, A) JP-A-7-86754 (JP, A) JP-A-6-52191 (JP, U) JP-A-1-160899 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H05K 9/00

Claims (4)

(57) [Claims] 1. A shield case, which is a BGA (ball grid array) which is a surface-mounted multi-terminal LSI package and further has a BGA package having two or more wiring pattern layers inside the package.
All of the connection terminals (solder balls) on the four sides of the outer periphery of the GA are allocated to the ground terminals, and the outer periphery of the wiring pattern on which the bare chip is mounted on the opposite side of the connection terminals is further covered by the ground pattern. A shield case, wherein connection terminals on four sides of an outer peripheral portion and ground patterns on four sides of an outer peripheral portion on a wiring pattern on which a bare chip is mounted are connected by through holes. 2. A wiring pattern on which a bare chip opposite to a connection terminal is mounted, wherein the bare chip is covered by a shielding means on a pattern in which four sides of the outer peripheral portion are further covered with a ground pattern. The shield case according to claim 1. 3. In an inner via type main board having three or more layers, the pattern on the front and back of the main board is used as the entire ground (however, except for the ground connection terminals on the four sides of the outer periphery of the BGA of the pattern mounting the BGA package). The inner terminals are connected to the inner layer pattern of the inner via type main board of three or more layers by the inner vias.) Furthermore, the outer peripheral part of the inner via type main board is connected by a large number of through holes connecting the front and back patterns. And a shield case. 4. A filter for forming a pattern layer inside a package, wherein a filter is formed between a bare chip pad and a connection terminal of a BGA package by using a ceramic lamination technique and a ferrite lamination technique. The shield case according to claim 1.