JP3083582B2 - Parallel processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing apparatus for performing high-speed information processing, and more particularly to a data flow type parallel processing apparatus and a plurality of processing means suitable for scientific and technical calculations for repeatedly processing a large amount of data. Regarding the network between.

[0002]

2. Description of the Related Art A plurality of processing means of a massively parallel computer (hereinafter, referred to as a plurality of processing means)
As a system for connecting a unit processing element (hereinafter referred to as PE: Processing Element), a bus type, a ring bus type, a hypercube type, a tree type, a lattice type, a star type, a network connection type, and the like are known.

[0003] Improvements regarding the ring bus type are described in "Loop S".
About tructured Computer ", Information Processing and Computer Architecture Workshop, 56-1 and" Loop Str
traffic characteristics of uctured Computer, ”IEICE Transactions '89 / 3 Vol. J72-DI No. 3, number 149
Page 156 to "Loop Structured Computer"
Characteristic Analysis ”, Parallel Processing Symposium JSPP'89
Known from pages 321 to 328.

FIG. 8 shows Loop Struc disclosed in the above-mentioned paper.
tured Computer (hereinafter referred to as LSC). 8, 710, 720, 730, and 740 are unit processing elements (PEs), 711, 721, 731, and 741 are shift registers, and 750 is configured by sequentially connecting inputs and outputs of shift registers in a plurality of PEs. This is a pipeline type ring bath. In particular, the PE 710 that constitutes a control unit for exchanging packets with the host computer is controlled by a CU (Control Un
call it). Since the PEs 720, 730, and 740 are not directly connected to the storage device, the PEs transfer packets with the PE 710 to access the storage device. An empty packet, a data packet, and a result packet are packed on the pipeline type ring bus 750, and each PE transmits a data packet and a result packet addressed to the own PE flowing on the pipeline type ring bus 710 to an empty packet or another packet. Exchange with result packet addressed to PE. The processing of each PE proceeds by processing a data packet addressed to the own PE and generating a result packet addressed to the other PE. There are the following three types of LSC processing methods according to the prior art.

(1) A method in which processing data of each PE is first fixed and then processing data is flowed in a pipeline.

(2) A method in which processing packets having both processing functions and processing data are flowed in a pipeline.

(3) A processing method in which the above (1) and (2) coexist.

A processing mode for connecting a plurality of pipeline ring buses via a CU is also known from the above-mentioned paper.

[0009]

In the above-mentioned prior art, if the number of PEs is increased to one pipeline type ring bus in order to improve the processing performance, the ring of the pipeline type ring bus becomes large, and the target PE is increased. However, there is a problem that the transfer time until the packet arrives becomes longer. Similarly, when the number of PEs is increased for the purpose of improving the processing performance, the traffic volume of data packets and result packets flowing through the pipeline-type ring bus increases, and the result packet in the PE cannot be output to the pipeline-type ring bus. As a result, a packet destined for the own PE cannot be captured in the PE, so that the processing is deadlocked. There is also a method in which a pipeline ring bus independent of other pipeline type ring buses is connected via a CU. However, the CU has a method of distributing packets between PEs that cross the pipeline type ring buses. Since a large load is applied to the processing, there is a problem that the packet transfer time between the pipeline type ring buses becomes long and the system performance is remarkably reduced.

[0010] It is an object of the present invention to provide a network configuration which can easily optimize the traffic volume of the data packet and the result packet of the pipeline type ring bus in order to secure the number of PEs which can cope with the multiple programming environment. And a processing method.

[0011]

In order to achieve the above object, a parallel processing apparatus according to the present invention comprises a plurality of one-layer pipeline-type ring buses in which a plurality of shift registers are connected in a ring shape. Providing processing means for taking in and processing packets flowing on the pipeline type ring bus for each shift register of each layer, further providing packet control means for sending and receiving packets to at least one processing means of each layer, The processing means is provided with a function of taking in the output of the processing means of the layer above the layer to which it belongs to the pipeline ring bus of its own layer.

The packet includes, for example, a program packet containing function information for designating a function to be assigned to each processing means, and a data packet containing data processed based on the function designated by the program packet.

Each processing means preferably determines whether or not a packet flowing on the pipeline type ring bus is a packet addressed to its own processing means, and takes in the packet in accordance with an output of the means. Means for switching whether or not to perform the operation. In this case, each processing means, when capturing a packet from the pipeline type ring bus, means for placing a packet from the processing means of an upper layer or an empty packet on the pipeline type ring bus instead of the packet. It is desirable to have.

The above-mentioned judging means is also provided with a function of detecting a packet allocated to the processing means of another layer, and a path for passing the packet through to the pipeline ring bus of the lower layer at the time of the detection is provided. Is also good.

Each processing means includes means for determining whether or not a packet flowing on the pipeline type ring bus is an empty packet, and, in accordance with an output from the means, a packet from a processing means in an upper layer is transmitted. Means for switching whether or not to put on the pipeline ring bus.

[0016] The packet control means preferably includes a first packet designating a first operation and a second packet designating a second operation performed using a result of the first operation. When allocating to the separate processing means, it has a mapping management function of allocating the second packet to processing means of a layer lower than the layer of the processing means allocating the first packet.

The other constitutions, functions and effects of the present invention will be apparent from the following description.

[0018]

The present invention has a plurality of layers each including a plurality of processing means, the packet control means can flow a packet to at least one processing means of each layer, and the processing means comprises upper and lower pipes. Since it is connected to the line-type ring bus, processing means can be used for packet transfer between the pipeline-type ring buses, so that the traffic volume of data packets and result packets of the pipeline-type ring bus in each layer is optimized. It can be.

[0019]

Embodiments of the present invention will be described below in detail.

FIG. 1 shows an example of the overall configuration of a parallel processing apparatus according to the present invention. In FIG. 1, 101 is a host computer, 102 is a packet control device, 103 is a high-speed packet processing device, and 104 is a storage device. Host computer 10
1 and the packet control device 102 share the storage device 104. Host computer 101 and packet control device 1
02, the host computer 101 instructs the packet control device 102 to start, and the packet control device 1
02 informs the host computer 101 that the processing has been completed. High-speed packet processing device 10
Reference numeral 3 denotes a plurality of data paths and a packet output request signal, which are connected to the packet control device 102. Data transfer between the host computer 101 and the packet control device 102,
All data transfer between the packet control device 102 and the high-speed packet processing device 103 is performed by packets. The packet control device 102 in FIG. 1 and the PEs (described later) in the first column of the high-speed packet processing device 103 correspond to a conventional CU. There are two packet formats, one for CU and the other for PE. One is a program written in a high-level language or the like, compiled in the host computer 101, and stored in the storage device 104.
The CU program packet and the CU data packet format stored in the storage device 104 and the CU program packet and the CU data packet stored in the storage device 104 are sent to the high-speed packet processing device 103 by the packet control device 102. PE program converted for
Packet and PE data packet format. The configuration of the latter packet format will be described later in detail. Less than,
An outline of the processing flow will be described.

The host computer 101 instructs the packet control device 102 to execute packet processing. In response to this instruction, the packet control device 102 reads out the CU program packet stored in the storage device 104 and sends the CU program packet to the high-speed packet processing device 103.
After the conversion into the packet, the PE program packet starts to flow to the high-speed packet processing device 103 in a pipeline manner. In the high-speed packet processing device 103, mapping is performed according to the contents of the PE program packet. Here, the mapping refers to a process of allocating each program packet specifying an arithmetic function to a specific PE. The PE that has received the program packet adds an assignment completion report to the program packet and returns it to the packet control device 102. The packet control device 102 counts the assignment completion report and recognizes that all mapping has been completed. At that time, the packet control device 10
2 reads the CU data packet stored in the storage device 104, converts it into a PE data packet to be sent to the high-speed packet processing device 103, and converts the PE data packet to the high-speed packet processing device 103 in a pipeline manner. Shed. When all data packets have been processed,
The packet control device 102 reports an end to the host computer 101, and at the same time, sends a program erasure packet to release the mapping of the program of the high-speed packet processing device 103, and the process of the program ends. The above is the general flow of the processing of the present apparatus.

Next, the operation inside the high-speed packet processing device 103 will be described. FIG. 2 shows a high-speed packet processing apparatus having three rows and four columns (referred to as a torus-type high-speed packet processing apparatus) 103.
Is shown together with the packet control device 102 and the storage device 104. 211, 212, 21
3,214,221,222,223,224,23
1,232,233,234 are PEs, respectively.
In FIG. 2, the pipeline type ring buses 10, 2 are respectively shown.
One row connected by 0, 30 is called a layer, and PE
(1, 1), PE (1, 2), PE (1, 3), PE
(1,4) is the first layer, PE (2,1), PE (2,
2), PE (2,3), PE (2,4) in the second layer, PE
(3,1), PE (3,2), PE (3,3), PE
(3, 4) is called a third layer. The first row of PEs in each layer (1,
1), PE (2, 1), and PE (3, 1) are connected to the packet control device 102, respectively. Further, these PEs have a function of transmitting a packet capture request signal to the packet control device 102. PE (1,
1), all P except PE (2,1), PE (3,1)
E captures packets from the upper pipelined ring bus, processes the packets, sends processed packets to the lower pipelined ring bus, and captures packets from the upper pipelined ring bus; It is possible to pass a packet to the lower pipeline ring bus. PE (1, 1), PE
The connection buses above and below (2, 1) and PE (3, 1) are connected to the packet controller 102, and packets are exchanged with the packet controller 102 via the connection bus.

The present invention can be extended to a torus-type high-speed packet processing apparatus having m rows and n columns. Further, a non-torus type embodiment in which a connection bus from the third layer to the first layer is removed is also conceivable. In this case, the transfer of the packet from the third layer to the first layer is performed via the packet control device 102.

FIG. 3 shows an example of the configuration of the PE. In FIG.
Latches 301, 302, and 303 constitute a shift register, 310 is an empty packet determination circuit, 320 is a processing packet determination circuit, 311, 321 and 322 are selection circuits,
23 is a through path, 330 is an empty packet generator, 340
Is a processing queue, 341 is a calculation input latch A, 342 is a calculation input latch B, 350 is a function determination information register, 360 is a calculation / processing unit, 370 is a data packet generation circuit, 380 is an output waiting packet queue,
72 is a packet transmission request signal. The packet transmission request signal 372 is the PE 211, 221, 2 in the first column of FIG.
Although the signal is required only for 31, it may be provided for all PEs so that each PE has the same configuration. Reference numeral 300 denotes a pipeline type ring bus input terminal connected to the latch 301, and reference numeral 304 denotes a pipeline type ring bus output terminal for receiving the output of the latch 303. Pipeline type ring bus input terminals 3 between adjacent PEs
By connecting 00 and the pipeline type ring bus output terminal 304, a pipeline type ring bus is configured. 371 is a PE data packet output terminal, 381
Is a PE program / data packet input terminal.
By cascading the PE data packet output terminal 371 and the PE program / data packet input terminal 381 mutually between vertically adjacent PEs in FIG. 2, PEs in the same row are connected in a ring. That is, PE
The data packet taken out (packet exchanged) from the internal pipeline type ring bus passes from the processing waiting packet queue 340 in the PE to the operation / processing unit 360, and the operation result is sent to the data packet generation circuit 370 by the data packet generation circuit 370. Becomes a packet, PE data packet output terminal 3
From 71, the packet is queued in the output waiting packet queue 380 of the adjacent lower layer PE, and is transferred (packet exchange) to the lower layer pipeline ring bus. Note that the output waiting packet queue 38 in one PE
0 may be provided at the subsequent stage of the data packet generation circuit 370 in the same PE, but by adopting a structure in which a pipeline type ring bus is incorporated in the PE as shown in FIG.
The physical distance between the output waiting packet queue 380 and the pipeline type ring bus and the physical distance between the processing waiting packet queue 340 and the pipeline type ring bus are shortened, and the speed of the pipeline type ring bus is increased. Can be achieved.

FIGS. 4 and 5 show one embodiment of the PE program / data packet format. 400, 42
0 is a task number (TN), and 401 and 421 are packet numbers (PN). Reference numerals 402 and 422 denote processing destination PE addresses (LN) that specify the PE to which the packet is assigned.
PE). 403 is an operation code (FC) indicating the function of the program packet, and 404 is a firing condition (E
C), 405 is an output data type (DT), 424 is an RT data type (DT) described later, 406 is the number of output results (OC), 407, 408, 409, 410 are output destination PE addresses (LNPE) ). 423 is a condition code (CC); 425 is a data serial number (DN) for data management by the CU;
Indicates operation data and result data (RT).
The output destination PE addresses 407, 408, 409, and 410 have any of a plurality of input ports (A side or B
Side) is also included. When the left bit of the firing condition 404 is “1”, the arithmetic inputs A are aligned, and when the right bit is “1”, the arithmetic inputs B are aligned. When the operation code 403 is “DATA” and the firing condition 404 is “10”, the 407 field and the 408 field are constants of the operation input A, and
When the operation code 403 is “DATA” and the firing condition 404 is “01”, the fields 409 and 410 are constants of the operation input B. An empty packet is when the task numbers 400 and 420 are “0”, and a program erasure packet is when the task number 420 of the PE data packet is other than “0” and the packet number 421
Is '0'. Condition code 42
When 3 is other than '0', it indicates that there is an operation error in the operation input data 426 of the PE data packet. The output data type 406 indicates whether the output data is a real number or an integer by 'F' and 'I', respectively.

FIG. 6 is an example of a program for explaining the operation of the PE. Figure (a) shows the high-level language FORTR.
A program for performing multiplication and addition of a one-dimensional array described in AN. FIG. 12B shows a packet controller 102 further converting a CU packet obtained by compiling the program shown in FIG. It shows a PE program packet obtained by performing the processing. Figure (c)
Is a P corresponding to the PE program packet shown in FIG.
5 shows an E data packet.

In FIG. 6B, the PE program packet 501 has a task number of “1”, a packet number of “1”, and an operation code of “*” (in this case, A (i)
* B (i)), which represents a packet to be output to the operation unit input A side of the PE address '23' with the operation result as a real number, and indicates that the packet is mapped to the PE address '12'. In the packet 502, the task number is “1”, the packet number is “2”, and the operation code is multiplication “*” (in this case, the calculation result * S of the packet 501). Represents a packet to be output to the device input A side, and indicates that the packet is mapped to the PE address '23'. The packet 503 has a task number of “1” and a packet number of “3”, and indicates that a constant S stored on the A side of the arithmetic unit having the PE address “23” is mapped to the PE address 23. In the packet 504, the task number is “1”, the packet number is “4”, the operation code is “+” (in this case, the calculation result of the packet 502 + C (i)), and the calculation result is a real number and the PE address 11 Indicates that the packet is output to the computing unit input A side, and is mapped to the PE address '34'. The packet 505 has a task number of “1”, a packet number of “5”, and, when the operation result of the packet 504 is sent to the B-side input of the arithmetic unit, the packet to be transferred to the packet control device 102. Represents, P
This indicates that the data is mapped to the E address 11.

In FIG. 6C, the packet 510 is
Task number is '1', packet number is '6', transfer destination P
The E address is “12” on the A side, which indicates that the type of the RT data on the input A side of the processing unit in the PE is a real number.
The packet 511 indicates that the task number is “1”, the packet number is “7”, the transfer destination PE address is “B”, the B side, and the type of RT data on the B input side of the PE in the PE is a real number. Represents. The packet 512 indicates that the task number is “1”, the packet number is “8”, and the destination PE address is “34” on the B side, and that the type of RT data on the B input side of the PE in the PE is a real number. Represents. 510,51
The PE data packet in the format of 1,512 is A
(1), B (1), C (1) to A (100), B (1
00) and C (100) are generated by the packet control device 102. Finally, the program erase packet 51
3 is generated.

FIG. 7 shows a state in which the group of PE program packets shown in FIG. That is, the PE program packets 501, 502, 503, 504, 505
Are the PE addresses' 12 ',' 23 'and' 2, respectively.
3 ',' 34 ', and' 11 '. The packet control device 102 normally causes each packet to flow to the pipeline-type ring bus via the PE in the first row of the layer to which the PE to which the packet is assigned, but waits for the output queue of the PE in the first row of the layer. If 380 is crowded, it is also possible to flow from another layer. Packet processing device 10
The PE data packet flowing from 2 flows mainly on a solid line. Packets that are not taken in because the processing queue in the PE queue 340 are full continue to rotate around the pipeline ring bus indicated by the dotted line until the processing queue in the PE becomes empty.

The specific mapping operation will be described with reference to the configuration of the PE in FIG. 3, the PE program packet format in FIG. 4, and the flowchart in FIG.

(1) First, the packet control device 102 reads a CU program packet from the storage device 104 and converts it into a PE program packet (S
1) According to the processing destination PE address 402, the PE program packet is transferred to one of the PEs connected to the packet control apparatus 102 (S2).

(2) This PE program packet is
It is stored in the output waiting packet queue 380 of the PE.

(3) The empty packet determination circuit 310 constantly monitors the pipeline type ring bus (S3), and when detecting that the task number is "0", that is, an empty packet, sets the selector 311 to the pipe. The flow from the line-type ring bus is switched to the output of the output-waiting packet queue 380 (S15), and the PE program packet stored in the output-waiting packet queue 380 is put on the pipeline-type ring bus. When the output waiting packet queue 380 is empty (S14), switching of the selector 311 does not occur.

(4) The processing packet judgment circuit 320 constantly monitors the pipeline type ring bus (S4).
When the PE address is equal to the PE address stored in the function determination information register 350, the selector 321 is moved from the flow of the pipeline type ring bus to the packet queue 340 to be processed, and the selector 322 is moved to the pipeline ring bus. The flow is simultaneously switched from the flow to the empty packet generator 330 (S8), and the queued packet queue 3 for processing is processed.
At the same time as storing the PE program packet in 40, an empty packet is put on the pipeline type ring bus.
In the PE address field of the function determination information register 350, the PE address of the PE is stored when the system is started, or is fixedly set. When placing an empty packet on the pipeline ring bus, if there is a packet in the output waiting packet queue 380 (S9),
The selector 311 is switched from the flow of the pipeline type ring bus to the output waiting packet queue 380 (S1).
2) instead of the empty packet, the packet queue 380
The packets in the pipeline ring bus. The processing packet determination circuit 320 also determines whether or not the layer of the PE to which the packet (latched by the latch 301) flowing on the pipeline type ring bus is assigned is different from its own layer (S5). If it is determined that they are different, the selector 3
21 is switched from the flow of the pipeline ring bus of the own layer to the through path 323 (S7), and the packet is flowed into the pipeline ring bus of the lower layer via the output queue queue 380 of the lower layer.

(5) If the operation code 403 of the PE program packet stored in the processing waiting packet queue 340 in the above processing (4) is other than 'DATA' (S10)
The PE program packet is stored in the function determination information register 350 (S11). Operation code 403 is' D
If it is ATA ', the constant is stored in the operation input latch A341 or the operation input latch B342 according to the firing condition 404 of the PE program packet (S13).

(6) Under the control of the packet controller 102, until there is no CU program packet (S
6) The above processes (1) to (5) are repeated in parallel, and all program packets are allocated to each PE in each layer.

The above is the mapping operation. Next, FIG.
Configuration of PE, PE program packet format of FIG. 4,
A specific mapping operation will be described with reference to FIG.

(1) The packet control device 102 reads out a CU data packet from the storage device 104, converts it into a PE data packet (S21), and, based on the processing destination PE address 422, communicates with the packet control device 102. The PE data packet is transferred to one of the connected PEs (S22).

(2) The PE data packet is
E is stored in the output queue queue 380.

(3) The empty packet determination circuit 310 constantly monitors the pipeline type ring bus (S23).
When detecting that the task number is '0', that is, an empty packet, the selector 311 is switched from the flow of the pipeline type ring bus to the output of the output waiting packet queue 380 (S39) and stored in the output waiting packet queue 380. The loaded PE data packet is put on a pipeline type ring bus. When the output waiting packet queue 380 is empty (S38), the switching of the selector 311 does not occur.

(4) The processing packet judgment circuit 320 constantly monitors the pipeline type ring bus (S24).
When the PE address is equal to the PE address stored in the function determination information register 350, the selector 321 is moved from the flow of the pipeline type ring bus to the packet queue 340 to be processed, and the selector 322 is moved to the pipeline ring bus. The flow is simultaneously switched to the empty packet generator 330 (S25), and the PE program packet is stored in the processing waiting packet queue 340, and at the same time, the empty packet is put on the pipeline type ring bus. At this time, if there is a packet in the output waiting packet queue 380 (S26), the selector 311 is switched from the flow of the pipeline type ring bus to the output waiting packet queue 380 (S35), and the packet in the packet queue 380 is piped. Put it on a line-type ring bath. When the layer to which the assignment destination PE belongs is different from the own layer (S36), the processing packet determination circuit 320 determines the selector 321 from the flow of the pipeline ring bus of the own layer to the through path 3
23 (S37), and the packet is sent to the lower-layer pipeline-type ring bus via the lower-layer output waiting packet queue 380.

(5) When the packet number 421 of the PE data packet stored in the processing waiting packet queue 340 in the above process (4) is '0' (S27), the function determination information register 350 is initialized (S34). ). The condition code 423 of the PE data packet is '0'
If (S29), the RT data 426 is input to the operation input side of the operation / processing unit 360 designated by the PE address 422.
Pour in. If the condition code 423 is other than “0”, that is, if there is an operation error in the previous processing, exception processing defined in the condition code 423 is performed (S33). Note that the function determination information register 350
The '0' bit of the firing condition is changed to '1' when the operation data is taken into a predetermined input side.

(6) When the firing condition in the function determination information register 350 has become “11” (S 28), that is, when the operation data is complete, the PE data packet is processed by the operation / processing section 360. (S30) The calculation result is sent to the data packet generation circuit 370 to generate a PE data packet (S31).

(7) Data packet generation circuit 370
Is the number 406 of output of the operation result of the function determination information register 350, and the output destination PE addresses 407, 408, 4
09, 410, the number of PE data to be output
Generate a packet. These PE data packets are stored in the output waiting packet queue 380 of the lower layer PE.

(8) The above operations (3) to (7) are performed for all PEs.
Are performed in parallel. However, the function determination information register 3
In the PE where the operation code 403 of 50 is the OUT function,
When the firing condition in the function determination information register 350 is “11”, the data packet generation circuit 370 sends a packet transmission request 372 to the packet control device 102 and the P generated by the data packet generation circuit 370.
The E data packet flows into the packet controller 102. Then, the packet control device 102
To store the result.

(9) Under the control of the packet controller 102, until there are no more CU data packets (S32)
The above processes (1) to (8) are repeated in parallel, and when the packet control device 102 receives all the processed data packets, it sends the program erasure packet 513 and the PE used in the program concerned. Frees up for other tasks.

[0047]

According to the present invention, a structure in which a plurality of PEs are connected to a pipeline type ring bus is formed as one layer,
By performing inter-layer connection via, packets flow from one pipeline-type ring bus to another without using a packet control device, so that the load on the packet control device is reduced, and as a result, The packet controller can pass more data packets to the high-speed packet processor, and many tasks can be efficiently multiplexed in parallel.

Further, the data packet enters from the pipeline ring bus in the upper layer of the PE, is processed by the arithmetic unit in the PE, and flows to the pipeline ring bus in the lower layer of the PE. Is not output to the pipeline type ring bus and the risk of deadlock is reduced.

By providing a through path between layers, a packet of a different layer can be quickly transferred to a target layer. Of course, by connecting the PE and the CU of each layer, even when the PE of the continuous layer cannot be allocated, the data can flow into the target layer via the CU, and the utilization efficiency of the packet control device (and the PE) can be improved. Is easy to increase.

Further, by incorporating a register constituting a part of the pipeline type ring bus into the PE, the register between the pipeline type ring bus and the output waiting packet queue, and between the pipeline type ring bus and the processing waiting packet can be obtained. Since the physical distance from the queue is short, the speed of the pipeline type ring bus can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a torus-type high-speed packet processing apparatus having three rows and four columns according to the present invention.

FIG. 3 is a block diagram showing a configuration example of a unit processing element (PE) in FIG. 2;

FIG. 4 is an explanatory diagram illustrating an example of a PE program packet format used in the apparatus according to the embodiment;

FIG. 5 is an explanatory diagram illustrating an example of a PE data packet format used in the apparatus according to the embodiment;

FIG. 6 is an explanatory diagram of a program example for explaining a PE operation according to the embodiment;

FIG. 7 is an explanatory diagram of an example of program mapping in the embodiment.

FIG. 8 is a block diagram of a configuration of a conventional high-speed packet processing device.

FIG. 9 is a flowchart of program mapping in the embodiment.

FIG. 10 is a flowchart of a calculation process in the embodiment.

[Explanation of symbols]

101: Host computer, 102: Packet controller, 1
03: High-speed packet processing device, 104: Storage device, 21
1,212,213,214,221,222,22
3, 224, 231, 232, 233, 234: unit processing element, 300: pipeline type ring bus input terminal
Reference numerals 301, 302, 303: latch, 304: pipeline type ring bus output terminal, 310: empty packet determination circuit, 311, 321, 322 ... selector, 320: processing packet determination circuit, 323: through path, 330: empty packet generator 340... Queue for processing, 34
1 ... operation input latch A, 342 ... operation input latch B, 3
50: Function determination information register, 360: Operation / processing unit
370: data packet generation circuit; 371: PE data packet output terminal; 372: packet transmission request;
80: output waiting packet queue, 381: PE program / data packet input terminal, 400, 420: task number, 401, 421: packet number, 402, 42
2: Processing destination PE address, 403: Operation code, 404
... ignition condition, 405 ... output data type, 406 ... output number, 407,408,409,410 ... output destination PE address and operation unit input port designation 423 ... condition code 424 ... RT data type 425 ... data number , 426 ... operation data and result data, 501
502, 503, 504, 505 ... PE program
Packets, 510, 511, 512: PE data packet, 513: program erase packet, 710: control unit, 720, 730, 740: processing element, 711, 71
2,713,714... Shift register.

Continuation of the front page (56) References Parallel Processing Symposium JSPP'89 Papers Feb. 2-4 1989 pp. 321-328 Yoshio Yoshioka "Characteristic analysis of Loop Structured Computer" Transactions of the Institute of Electronics, Information and Communication Engineers D- ▲ I VOL. J72 NO. 3 MARCH 1989, p.149-156 Yoshio Yoshioka, "Traffic Characteristics of Loop Structured Computer" (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/16 610 G06F 13/36 530 G06F 15/82 JICST file ( JOIS)

Claims (11)

(57) [Claims] 1. A single-layer pipeline-type ring bus in which a plurality of shift registers are connected in a ring shape is provided in a plurality of layers, and processing means for receiving and processing packets flowing on the pipeline-type ring bus is provided in each layer. A shift register; and a packet control unit for transmitting and receiving a packet to and from at least one processing unit of each layer, wherein the processing unit outputs an output of a processing unit of a layer above the layer to which the unit belongs. A parallel processing device characterized by adding a function of taking in a pipeline type ring bus. 2. The method according to claim 1, wherein the packet is a program packet including function information designating a function to be assigned to each processing means.
2. The parallel processing device according to claim 1, comprising a data packet including data processed based on a function specified by the program packet. 3. Each of the processing means determines whether or not a packet flowing on the pipeline type ring bus is a packet addressed to its own processing means, and determines whether or not to take in the packet according to the output of the means. 3. The parallel processing device according to claim 1, further comprising means for switching whether or not the parallel processing is performed. 4. When each processing means takes in a packet from the pipeline type ring bus, it places a packet from the processing means of an upper layer or an empty packet on the pipeline type ring bus instead of the packet. 4. The parallel processing apparatus according to claim 3, further comprising: means. 5. The determining means has a function of detecting a packet assigned to a processing means of another layer, and further provides a path through which the packet is passed through to a pipeline ring bus of a lower layer at the time of the detection. 4. The parallel processing device according to claim 3, wherein: 6. A processing means for determining whether or not a packet flowing on the pipeline type ring bus is an empty packet, and in response to an output of the means, a signal from a processing means of an upper layer. parallel packet processing apparatus according to claim 1 or 4 further characterized in that a means for switching whether placed on the pipelined ring bus a. 7. The packet control means separates a first packet designating a first operation and a second packet designating a second operation performed using a result of the first operation. 2. The parallel processing according to claim 1, further comprising a mapping management function for allocating the second packet to a processing unit in a layer lower than a layer of the processing unit allocating the first packet when allocating the second packet. apparatus. 8. An m × n processing means arranged in m rows and n columns, and an n number of shift registers connected to said processing means on a one-to-one basis in each row in a ring shape. Transfer means for transferring the result of the processing means of the i-th row to the pipeline-type ring bus connected to the processing means of the (i + 1) -th row; A parallel processing device comprising: packet control means having a function of placing a packet to be processed and a function of receiving a processed packet from a pipeline type ring bus of each row. 9. The parallel processing according to claim 8, wherein said transfer means transfers the result of the processing means in the m-th row to a pipeline type ring bus connected to the processing means in the first row. apparatus. 10. The parallel processing apparatus according to claim 8, wherein the transfer by said transfer means is performed between processing means in the same row. 11. A processing system comprising: a shift register forming a part of the pipeline type ring bus; a first packet queue storing packets fetched from the shift register; 9. The parallel processing device according to claim 1, further comprising a second packet queue for storing a packet to be captured in the shift register.