JP3084255B2 - LSI layout design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design technique in LSI design, and more particularly to an LSI layout design method for designing an LSI layout so that timing constraints are reliably satisfied.

[0002]

2. Description of the Related Art In a layout design of an LSI incorporated in a high-performance information device, a so-called timing-driven arrangement in which cells are arranged so as to satisfy timing constraints for guaranteeing a high-speed clock operation of a synchronous circuit is important. Is coming.

[0005] Conventional timing-driven placement methods include a placement evaluation function for evaluating a circuit area and a wiring length.
Added a term for evaluating the length of wiring related to the maximum delay path (critical path) that affects timing among the signal paths of the combinational circuit, and repeatedly improved cell placement so that the value of this placement evaluation function was minimized The way of doing was central.

[0004]

However, in the conventional method in which the term of the length of the wiring length related to the critical path is added to the placement evaluation function, not only the timing but also the circuit area and the like are evaluated at the same time. There is no guarantee that the constraints will always be met, and timing constraints violations may lead to placement results that remain partially. For this reason, in order to ensure that the timing constraints are satisfied, it is necessary to repeat the logic design by resynthesis after the layout design.

[0005] In order to obtain an optimum arrangement result as a whole, precise arrangement improvement is required, and the processing takes an enormous amount of time. Therefore, it has been difficult to improve the efficiency of LSI design.

In order to solve this problem, the inventor has considered the following method.

Whether or not the timing constraint is satisfied is determined by the cell arrangement and wiring between the flip-flops which are the start and end points of each critical path. Paying attention to this point, the connection relationship between the flip-flops related to the timing constraint is obtained in advance, the layout position of each flip-flop is first determined so as to optimize the timing, and then the layout design is performed. According to this method, an arrangement of a huge number of cells constituting an LSI is not designed at once, but an arrangement of only a small number of flip-flops is designed first, so that the processing time can be greatly reduced. In addition, it is considered that an arrangement satisfying the timing constraint can be realized.

However, it is not easy to determine the connection relation between flip-flops related to the timing constraint and to express the obtained connection relation in a form that can be handled by a computer.

Further, for example, when a connection relationship between flip-flops is obtained from a netlist of logic levels as shown in FIG. 15A, signals are input to various flip-flops from one combinational circuit. Fifteen
A connection relationship close to a complete graph (a graph in which each node branches to all other nodes) as shown in (b) is obtained. For this reason, even if it is desired to determine the arrangement position of each flip-flop so that the timing becomes optimal, it cannot be actually determined.

That is, the fact that the connection relation between flip-flops is close to a perfect graph means that each flip-flop has a signal input / output relation with most of the other flip-flops. On the other hand, in order to satisfy timing constraints, flip-flops serving as a start point and an end point of a signal flow are collected as close as possible. For this reason, when the connection relationship between flip-flops is close to a complete graph, the flip-flops are gathered near each other. However, since the area near each flip-flop is finite, all flip-flops are located at optimal positions. It is not guaranteed to be deployed. Therefore, it is necessary to prevent the connection relation between the flip-flops from being close to a perfect graph.

In view of the above problems, the present invention provides a method for designing an LSI layout which requires a short
It is an object to ensure that the timing constraint of I is satisfied.

[0012]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is an LSI laser.
LSI layout setting that performs layout design using a computer
As a measurement method, flip-flops in the circuit to be designed
Based on the netlist that represents the connections of the cells containing
Between flip-flops related to timing constraints
Generate a flip-flop netlist representing the connection relationship
First processing, and within a given arrangement area,
Flip-flop net generated in the first processing
Place each flip-flop according to the list and
Then, for each flip-flop,
Flip-flop area where cells related to
A second process for determining each of the regions, and
In each flip-flop area determined in
The cells that are associated with the flip-flops
And a process performed in the third process.
Layout design based on the layout of files,
In the first process, a critical path between each flip-flop is regarded as a wiring, and for each critical path, a cell belonging to the critical path is deleted from a netlist, and the sum of the areas of the deleted cells corresponds to the critical path. Flip-flop comprising a process of setting a weight of a wiring to be performed, a process of deleting a cell not belonging to any critical path from a netlist, and adding an area to a weight of a wiring corresponding to a critical path in the vicinity of the cell. And a flip-flop netlist composed of flip-flops and weighted wiring.

[0013] Further , a solution taken by the invention of claim 2
Is an LS that performs LSI layout design using a computer.
As an I layout design method, in a circuit to be designed,
Netries that represent the connection relationships of cells including flip-flops
Flip-flops related to timing constraints
A flip-flop network that represents the connection between
A first process of generating a list, and
The flip-flop generated in the first processing.
Arrange each flip-flop according to the drop net list
And for each flip-flop,
Flip, the area where cells related to flip-flops are placed
A second process for determining each flop area;
In each flip-flop area determined in the processing of step 2
And the cells associated with the corresponding flip-flop
And a third process for arranging, wherein in the third process,
Perform layout design based on cell placement
In the first processing, the flip-flop is seeded.
Flip-flop network by clustering
And a cell belonging to a critical path between each flip-flop and a cell incorporated in each flip-flop cluster while incorporating the cell belonging to the critical path between the flip-flops into a flip-flop cluster using the flip-flop serving as a starting point of the critical path as a seed. And the cell that does not belong to any critical path is transferred to one of the flip-flop clusters so that the area of each flip-flop cluster becomes equal. In addition to the area of the flip-flop cluster, the flip-flop cluster is incorporated.

[0014] Further , a solution taken by the invention of claim 3
Is an LS that performs LSI layout design using a computer.
As an I layout design method, in a circuit to be designed,
Netries that represent the connection relationships of cells including flip-flops
To strike based on, for about two related timing constraints flip
A flip-flop network that represents the connection between
A first process of generating a list, and
The flip-flop generated in the first processing.
Arrange each flip-flop according to the drop net list
And for each flip-flop,
Flip, the area where cells related to flip-flops are placed
A second process for determining each flop area;
In each flip-flop area determined in the processing of step 2
And the cells associated with the corresponding flip-flop
And a third process for arranging, wherein in the third process,
Perform layout design based on cell placement
In the first processing, the flip-flop is seeded.
Flip-flop network by clustering
A cell belonging to a critical path between the flip-flops and a flip-flop cluster using a flip-flop serving as a starting point of the critical path or a flip-flop serving as an ending point of the critical path. And a process in which the sum of the areas of the cells incorporated in each flip-flop cluster is set as the area of the flip-flop cluster, and a cell that does not belong to any critical path is set in each flip-flop cluster. A process of adding the area to one of the flip-flop clusters and incorporating the area into one of the flip-flop clusters so that the area is equalized.

[0015] A solution taken by the invention of claim 4
Is an LS that performs LSI layout design using a computer.
As an I layout design method, in a circuit to be designed,
Netries that represent the connection relationships of cells including flip-flops
Flip-flops related to timing constraints
A flip-flop network that represents the connection between
A first process of generating a list, and
The flip-flop generated in the first processing.
Arrange each flip-flop according to the drop net list
And for each flip-flop,
Flip, the area where cells related to flip-flops are placed
A second process for determining each flop area;
In each flip-flop area determined in the processing of step 2
And the cells associated with the corresponding flip-flop
And a third process for arranging, wherein in the third process,
Perform layout design based on cell placement
And than, the first process is for generating a flip-flop netlist having an area information of the cell relating to each flip-flop, the second process, the flip-flop that is generated in the first process A process of arranging the flip-flops evenly on an arrangement area given according to a netlist, and dividing the arrangement area according to area information of cells related to each flip-flop included in the flip-flop netlist. And a process for determining a flip-flop area.

[0016] Further , a solution taken by the invention of claim 5 is as follows.
Is an LS that performs LSI layout design using a computer.
As an I layout design method, in a circuit to be designed,
Netries that represent the connection relationships of cells including flip-flops
Flip-flops related to timing constraints
A flip-flop network that represents the connection between
A first process of generating a list, and
The flip-flop generated in the first processing.
Arrange each flip-flop according to the drop net list
And for each flip-flop,
Flip, the area where cells related to flip-flops are placed
A second process for determining each flop area;
In each flip-flop area determined in the processing of step 2
And the cells associated with the corresponding flip-flop
And a third process for arranging, wherein in the third process,
Perform layout design based on cell placement
In the third process, a process for finding the shortest path between the flip-flops arranged in the second process and a process for connecting a cell belonging to a critical path between flip-flops serving as a start point and an end point of the critical path are performed. The process includes a process of arranging cells on the shortest path and a process of arranging a cell that does not belong to any critical path in an empty area in a flip-flop area corresponding to a flip-flop to which the cell belongs .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a flowchart showing a flow of processing of an LSI layout design method according to a first embodiment of the present invention.
Here, for simplicity, the standard cell type LSI
Will be described as an example.

First, in step S10, a standard cell level netlist, a standard cell library, and arrangement conditions are input. As the placement condition, a placement region condition, a timing constraint condition, and the like are given. The placement area condition describes the number of cell columns, the ratio of the length and width of the placement area, and the like. The timing constraint condition describes the delay constraint value of the critical path between each flip-flop in the netlist. Step S10 constitutes the first process of claim 2.

Next, in step S20, a flip-flop netlist (FF netlist) representing a connection relation between flip-flops and related to timing constraints is generated from a standard cell level netlist. Cells other than flip-flops are deleted from the flip-flop netlist.

Next, in step S30, step S
According to the flip-flop netlist generated in step 20, each flip-flop is arranged in a given arrangement area, and a flip-flop area (FF), which is an area in which a cell related to the flip-flop is arranged for each flip-flop. Area).

Next, in step S40, step S
Each cell other than the flip-flop, which has been deleted from the flip-flop netlist at 20, is initially placed in the flip-flop area corresponding to the flip-flop to which the cell belongs. In step S50, the arrangement of the flip-flops performed in step S30 and the arrangement of cells other than the flip-flops performed in step S40 are improved in the entire arrangement region.

Finally, in step S60, an LSI layout is generated based on the cell arrangement obtained in step S50, and the generated LSI layout is output.
The process ends.

Step S20 of generating a flip-flop netlist will be described in more detail.

FIG. 2 is a flow chart showing the processing in step S20. FIG. 2A shows a case where a wiring corresponding to a critical path is weighted to delete cells, and a flip-flop netlist including flip-flops and weighted wiring is generated. (B) and (c) show a process of generating a flip-flop netlist by cluster generation (clustering) using flip-flops as seeds.

First, the processing of FIG. 2A will be described with reference to FIG. Now, based on the standard cell level netlist input in step S10, FIG.
Assume that a circuit as shown in FIG. FIG.
In (a), 11a and 11b are flip-flops, 21a, 21b, 21c and 22a are cells,
It is assumed that the critical path between the flip-flops 11a and 11b is a path passing through the cells 21a to 21c. In this specification, cells belonging to the critical path such as cells 21a to 21c are referred to as critical path cells, and cells not belonging to the critical path such as cell 22a are referred to as non-critical path cells.

In step S21a, the critical path cells are wired, that is, the critical path cells are deleted, and the sum of the areas of the deleted critical path cells is set as the weight of the wiring corresponding to the critical path. By step S21a, the circuit shown in FIG. 3A becomes as shown in FIG. In FIG. 3B, the critical path cells 21a to 21c are replaced by wirings 30, and the critical path cells 21a to 21c
If the area of 21c is S, the weight of the wiring 30 is 3S. As can be seen from FIG. 3B, the non-critical path 22a is isolated by this processing.

Next, in step S21b, the non-critical path cell is deleted by adding the area of the non-critical path cell to the weight of the wiring belonging to the critical path in the vicinity thereof. By step S21b, FIG.
The circuit shown in FIG. 3 is as shown in FIG. In FIG. 3C, the non-critical path cell 22a is deleted, and the weight of the wiring 30 becomes 4S by adding the area S of the non-critical path cell 22a. By such processing, a flip-flop netlist including flip-flops and weighted wirings in which the area of all cells is considered as the weight of wirings can be generated.

Next, the processing of FIG. 2B will be described with reference to FIG. Now, based on the standard cell level netlist input in step S10, FIG.
Assume that a circuit as shown in FIG.

In step S22a, clustering of the critical path cells between the flip-flops is performed using the flip-flop that outputs a signal to the critical path, that is, the flip-flop that is the starting point of the critical path. FIG. 4A is a diagram illustrating clustering for the circuit shown in FIG. 3A, and a broken line indicates a cluster (flip-flop cluster) using the flip-flop 11a as a seed. Critical path cells 21a-2
1c is clustered, and a flip-flop cluster 13a is generated. At this time, the sum of the areas of the incorporated critical path cells is set as the area of each flip-flop cluster.

Next, in step S22b, a new cluster is generated by adding a non-critical path cell to the flip-flop cluster generated in step S22a. In FIG. 4B, reference numerals 13a and 13b denote flip-flop clusters, and broken lines show new clustering using the flip-flop cluster 13a as a seed. A non-critical path 22a is added to newly form a flip-flop cluster 13A. Has been generated. At this time, the clustering of the non-critical path cells is performed so that the area of the flip-flop cluster becomes equal.

As a result, a cluster-level flip-flop netlist as shown in FIG. 4C can be generated. In FIG. 4C, flip-flop clusters 13A and 13B have area information of clustered cells.

Next, the processing of FIG. 2C will be described with reference to FIG. Now, based on the standard cell level netlist input in step S10, FIG.
Assume that a circuit as shown in FIG.

In step S23a, a flip-flop that outputs a signal to the critical path, that is, a flip-flop that is the starting point of the critical path, and a flip-flop that inputs a signal from the critical path, that is, the flip-flop that is the ending point of the critical path, are used as seeds. The clustering of the critical path cells between them is performed. FIG. 5A is a diagram illustrating clustering for the circuit illustrated in FIG. 3A, and broken lines indicate clustering using the flip-flops 11a and 11b as seeds. The critical path cell 21a is clustered using the flip-flop 11a as a seed to generate a flip-flop cluster 14a, while the critical path cells 21b and 21c are clustered using the flip-flop 11b as a seed to generate the flip-flop cluster 14b. . At this time, the sum of the areas of the incorporated critical path cells is set as the area of each flip-flop cluster.

Next, in step S23b, a non-critical path cell is added to the flip-flop cluster generated in step S23a to newly generate a flip-flop cluster. In FIG. 5B, 14
a and 14b are flip-flop clusters, and broken lines indicate clustering using the flip-flop clusters 14a and 14b as seeds. The non-critical path 22a is added to the flip-flop cluster 14a to newly generate a flip-flop cluster 14A. And
Further, a flip-flop cluster 14B is generated. At this time, clustering of non-critical path cells is performed so that the areas of the clusters are equal.

As a result, a cluster-level flip-flop netlist as shown in FIG. 5C can be generated. In FIG. 5C, flip-flop clusters 14A and 14B have area information of clustered cells.

Next, step S30 of determining the flip-flop area will be described in more detail.

FIG. 6 is a flowchart showing the processing in step S30. First, in step S30a, the flip-flops (or flip-flop clusters) are evenly arranged according to the flip-flop netlist obtained in step S20. This uniform arrangement can be obtained, for example, using a dynamic model evaluation function as shown in Expression (1). Evaluation function = Σ (wiring length) ² ... (1)

Next, in step S30b, the layout area is divided according to the cell area belonging to each flip-flop area, and the flip-flop area is determined. here,
A method for determining a flip-flop area from a cluster-level flip-flop netlist will be described with reference to FIG.

Now, at step S30a, FIG.
It is assumed that the position of each flip-flop cluster is determined as shown in FIG. In FIG. 7A, 10A, 1
Reference numerals 0B and 10C denote flip-flop clusters, each having information on the area of the clustered cells. As shown in FIG. 7B, a straight line 15 connecting the flip-flop clusters is divided by the ratio of the cell area of each flip-flop cluster, and a straight line passing through the dividing point 16 and perpendicular to the straight line 15 is drawn. Regions separated by the drawn straight line are each flip-flop region as shown in FIG.

When a flip-flop area is determined from a flip-flop netlist composed of flip-flops and weighted wiring, for example, each flip-flop is arranged at intervals according to the weight of the wiring, and each flip-flop is placed. May be defined as a flip-flop region defined by a vertical bisector of a straight line connecting.

Next, step S40 for performing the initial arrangement in the flip-flop area will be described in more detail.

FIG. 8 is a flowchart showing the processing in step S40. First, in step S40a, the shortest path between the flip-flops is obtained. Next, in step S40b, the cells belonging to the critical path are arranged on the shortest path obtained in step S40a between the flip-flops serving as the start point and the end point of the critical path. Finally, in step S40c, the non-critical path cell is arranged in a free area in the flip-flop area corresponding to the flip-flop to which the non-critical path cell relates.

An LSI layout design method according to the present embodiment will be specifically described with reference to FIGS.

FIG. 9A is a circuit diagram showing an example of the net list input in step S10. FIG.
In (a), each block represents a cell, and a line connecting the blocks represents a wiring between the cells. The cells 51a, 51b, 51c, and 51d with hatching are flip-flops, and the cells without hatching are cells other than flip-flops, that is, combinational logic cells. Here, it is assumed that the layout is designed based on the netlist shown in FIG.

In step S20, a flip-flop netlist is generated based on the netlist shown in FIG. Here, as shown in FIG. 2C and FIG. 5, it is assumed that the clustering of the critical path cells is performed using the flip-flops serving as the start point and the end point of the critical path as seeds. FIG. 9B shows FIG.
FIG. 7A is a diagram illustrating a result of clustering for the netlist illustrated in FIG.
Flip-flop clusters 52A, 52B, 52C, and 52D using seeds b, 51c, and 51d are generated.
Next, a flip-flop netlist is generated from FIG. 9B. Here, a process for deleting a critical path that does not require a timing constraint is performed so that the flip-flop netlist does not become close to a complete graph. For example, among critical paths between flip-flops, those having less than two cell stages are deleted from the flip-flop netlist as those requiring no timing constraint. As a result, a flip-flop netlist as shown in FIG. 9C is generated. In FIG. 9C, a broken line indicates a deleted critical path.

Next, in step S30, FIG.
The flip-flop area is determined based on the flip-flop netlist shown in FIG. First, the flip-flop clusters 52A, 52B, 52C, 52D are evenly arranged in the arrangement area. FIG. 10A shows the result of the uniform arrangement. Next, a flip-flop region is determined according to the area information of each flip-flop cluster. Here, a Voronoi diagram representing the sphere of influence of each flip-flop cluster is created based on the flip-flop netlist shown in FIG. 9C, and the sphere of influence of each cluster, that is, the Voronoi region is determined as the flip-flop region. FIG.
(B) is a diagram showing the determined flip-flop area.

Next, in step S40, cells clustered in the corresponding flip-flop cluster are initially arranged in each flip-flop region. FIG.
(A) is a figure which shows the result of initial arrangement, and 52a, 52
b, 52c and 52d are flip-flops corresponding to the respective flip-flop regions. Step S
At 50, the layout is improved for fine adjustment of the cell row and cell position, and the layout design is completed. FIG.
(B) is a diagram showing a result of the layout design.

As described above, L according to the present embodiment is
According to the SI layout design method, a flip-flop netlist representing a connection relation between flip-flops related to timing constraints is generated, and layout positions are determined according to the flip-flop netlist to perform layout design. It becomes possible to design an LSI layout that satisfies the constraints.

In an LSI that has been layout-designed by the LSI layout design method according to the present embodiment, in some or all of the circuits, cells logically connected to the flip-flop are arranged around the flip-flop, and The characteristic feature is that cells belonging to a critical path are arranged in a region near a straight line connecting a flip-flop serving as a start point and an flip-flop serving as an end point of the critical path.

Further, according to the present embodiment, the flip-flops can be arranged along the signal flow, so that the scan path wiring after the layout design does not have useless bends and is determined by the logic design. It almost matches the shape of the scan path. For example, assuming that a scan path as shown in FIG. 12A is defined for the netlist shown in FIG. 9A, if the layout is designed by the LSI layout design method according to the present embodiment, As shown in FIG. 12B, the scan path wiring substantially matches the shape of the scan path shown in FIG. On the other hand, according to the conventional method, FIG.
As shown in (c), the scan path wiring does not match the shape of the scan path determined by the logical design, and has a useless bend. Thus, according to the present embodiment,
Since the scan path wiring has no unnecessary bends,
The increase in the circuit area can be suppressed as compared with the related art, and the adjustment of the delay of the scanning signal becomes easy.

Further, according to the present embodiment, since flip-flops are not arranged in a concentrated manner, it is possible to prevent power consumption accompanying the flip-flop operation from being locally concentrated in an LSI layout. Therefore, an effect is also obtained that a malfunction of the LSI due to the voltage drop can be prevented.

(Second Embodiment) The solution taken by the invention according to the second embodiment of the present invention is an LS which performs LSI layout design using a computer.
The I layout design method includes a cell rearrangement process for rearranging a cell belonging to the critical path when there is a critical path that does not satisfy the timing constraint after the layout design. A first process for obtaining a shortest path from a flip-flop that outputs a signal to a path to a flip-flop that inputs a signal from the critical path, and a cell that belongs to a critical path that does not satisfy the timing constraint is obtained in the first process. And a second process of moving to the vicinity of the shortest route obtained.

In addition, the cell relocation processing includes a flip-flop that outputs a signal to a critical path that does not satisfy a timing constraint and a signal from the critical path so that the shortest path obtained in the first processing is shortened. It is assumed that a third process for moving the input flip-flop is further provided.

According to the present invention, when there is a critical path that does not satisfy the timing constraint after the layout design,
By rearranging the cells belonging to the critical path in the cell rearrangement processing, the signal delay time of the critical path can be reduced, and the timing constraint can be satisfied.

The second embodiment of the present invention relates to a method of rearranging cells belonging to a critical path for which a timing violation has been found by critical path analysis after designing the layout of an LSI.

FIG. 13 is a flowchart showing processing for rearranging cells in the LSI layout design method according to the present embodiment.

Now, according to the layout design of the LSI,
It is assumed that a layout including a plurality of cell columns as shown in FIG. In FIG. 14A, 100
a and 100b are flip-flops, 101a and 101
b and 101c are cells belonging to a critical path between the flip-flops 100a and 100b.

In step S71, the shortest path between flip-flops is obtained for a critical path for which a timing violation has been found. Flip-flops 100a and 10
Assuming that a timing violation has been found in the critical path between 0b, the shortest path 109 is obtained. Step S71 constitutes the first process.

Next, in step S72, flip-flops at both ends of the critical path are stored in step S71.
Is arranged and moved along the shortest path obtained in the step so that the shortest path becomes shorter. By step S72, the layout of the LSI becomes as shown in FIG. Step S72 constitutes the third process.

Finally, in step S73, the cells on the critical path are moved to the vicinity of the shortest path.
By the step S73, the layout of the LSI is changed as shown in FIG.
(C). Step S73 constitutes the second process.

By such a cell rearrangement process, the signal delay time of the critical path for which a timing violation has been found can be reduced, so that the timing constraint can be satisfied.

In the present embodiment, step S7
2 may be omitted.

[0063]

As described above, according to the present invention, the layout design is performed after the layout positions of the flip-flops are determined so as to optimize the timing according to the flip-flop netlist. An LSI layout that satisfies the requirement can be designed.

Further, even when there is a critical path that does not satisfy the timing constraint after the layout design, the timing constraint can be satisfied by rearranging the cells belonging to the critical path.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow of an LSI layout design method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a process of creating a flip-flop net list in the LSI layout design method according to the first embodiment of the present invention, where (a) is a flip-flop net composed of flip-flops and weighted wiring; Shows the process of generating the list,
(B) and (c) show a process of generating a flip-flop netlist by clustering using flip-flops as seeds.

FIG. 3 is a diagram for explaining the processing of FIG. 2 (a);
(A) is a given standard cell logic circuit, (b)
FIG. 3C is a diagram illustrating wiring of a critical path cell, and FIG. 3C is a diagram illustrating wiring of a non-critical path cell.

FIG. 4 is a diagram for explaining the process of FIG. 2 (b);
(A) is a diagram showing clustering of critical path cells, (b) is a diagram showing clustering of non-critical path cells, and (c) is a diagram showing a flip-flop netlist obtained by clustering.

FIG. 5 is a diagram for explaining the process of FIG. 2 (c);
(A) is a diagram showing clustering of critical path cells, (b) is a diagram showing clustering of non-critical path cells, and (c) is a diagram showing a flip-flop netlist obtained by clustering.

FIG. 6 is a flowchart illustrating a process of determining a flip-flop region in the LSI layout design method according to the first embodiment of the present invention.

FIGS. 7A to 7C are diagrams for explaining a process of determining a flip-flop region, and are diagrams illustrating positions of flip-flops in an arrangement region and flip-flop regions;

FIG. 8 is a flowchart showing a process for performing initial placement in a flip-flop region in the LSI layout design method according to the first embodiment of the present invention.

FIGS. 9A to 9C are views for explaining a process of generating a flip-flop netlist in the LSI layout design method according to the first embodiment of the present invention.

FIGS. 10A and 10B are diagrams for explaining a process of determining a flip-flop region in the LSI layout design method according to the first embodiment of the present invention.

FIGS. 11A and 11B are diagrams for explaining a process of arranging each cell in a flip-flop region and improving the arrangement in the LSI layout design method according to the first embodiment of the present invention; FIGS. is there.

12A is a diagram illustrating an example of a netlist in which a scan path is determined in a logical design, and FIG. 12B is an example of a layout designed according to the present embodiment based on the netlist of FIG. FIG.
(C) is a diagram showing an example of a layout designed by a conventional method based on the netlist of (a).

FIG. 13 is a flowchart showing processing for rearranging cells in the LSI layout design method according to the second embodiment of the present invention.

FIG. 14 is a diagram for explaining the method of FIG. 13;
(A)-(c) is a figure which shows the change of the layout of LSI.

15A and 15B are diagrams for explaining the reason why it is difficult to determine an arrangement position of a flip-flop so as to optimize timing; FIG. 15A is an example of a logic-level netlist; FIG. ) Is a connection relation of flip-flops having a shape close to a complete graph obtained from the netlist shown in FIG.

[Explanation of symbols]

11a, 11b flip-flops 21a, 21b, 21c critical path cell 22a non-critical path cell 30 wiring 13a, 13b, 13A, 13B flip-flop clusters 14a, 14b, 14A, 14B flip-flop clusters 10A, 10B, 10C flip-flop cluster 51a, 51b, 51c, 51d Flip-flop 52A, 52B, 52C, 52D Flip-flop cluster 100a, 100b Flip-flop 101a, 101b, 101c Critical path cell 109 Shortest path

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (5)

(57) [Claims] 1. An LSI layout design using a computer.
An LSI layout design method, which includes a method of designing a cell including a flip-flop in a circuit to be designed.
A timing system based on the netlist representing the connection relationship
Represents the connection relationship between flip-flops related to about
First processing for generating a flip-flop netlist
In the first processing in the given arrangement area.
According to the generated flip-flop netlist,
Each flip-flop is arranged, and each flip-flop is
For the flip-flop,
Each flip-flop area to be placed is determined.
And a flip-flop determined in the second process.
In the area, the cell related to the corresponding flip-flop is
And a third process for arranging the cells, respectively, based on the cell arrangement performed in the third process.
In the first process, a critical path between each flip-flop is regarded as a wiring, and for each critical path, a cell belonging to the critical path is deleted from a netlist.
The process of setting the sum of the area of the deleted cells as the weight of the wiring corresponding to the critical path, deleting the cells not belonging to any of the critical paths from the netlist, and reducing the area of the critical path near the relevant cell. An LSI layout design method, comprising: generating a flip-flop netlist including flip-flops and weighted wirings. 2. An LSI layout design using a computer.
An LSI layout design method, which includes a method of designing a cell including a flip-flop in a circuit to be designed.
A timing system based on the netlist representing the connection relationship
Represents the connection relationship between flip-flops related to about
First processing for generating a flip-flop netlist
In the first processing in the given arrangement area.
According to the generated flip-flop netlist,
Each flip-flop is arranged, and each flip-flop is
For the flip-flop,
Each flip-flop area to be placed is determined.
And a flip-flop determined in the second process.
In the area, the cell related to the corresponding flip-flop is
And a third process for arranging the cells, respectively, based on the cell arrangement performed in the third process.
Te, which performs layout design, the first process, by clustering the flip-flop as a seed,
Generate a flip-flop netlist,
In addition , a cell belonging to a critical path between each flip-flop is incorporated into a flip-flop cluster whose seed is a flip-flop serving as a starting point of the critical path, and the sum of the areas of the cells incorporated in each flip-flop cluster is represented by the flip-flop cluster. And adding cells that do not belong to any critical path to one of the flip-flop clusters so that the area of each flip-flop cluster becomes equal, And an incorporation process. 3. An LSI layout design is performed by using a computer.
An LSI layout design method, which includes a method of designing a cell including a flip-flop in a circuit to be designed.
A timing system based on the netlist representing the connection relationship
Represents the connection relationship between flip-flops related to about
First processing for generating a flip-flop netlist
In the first processing in the given arrangement area.
In accordance with the flip-flop netlist generated Te,
Each flip-flop is arranged, and each flip-flop is
For the flip-flop,
Each flip-flop area to be placed is determined.
And a flip-flop determined in the second process.
In the area, the cell related to the corresponding flip-flop is
And a third process for arranging the cells, respectively, based on the cell arrangement performed in the third process.
Te, which performs layout design, the first process, by clustering the flip-flop as a seed,
Generate a flip-flop netlist,
A cell belonging to a critical path between each flip-flop is incorporated into a flip-flop cluster seeded with a flip-flop serving as a starting point of the critical path or a flip-flop cluster seeded with a flip-flop serving as an ending point of the critical path. Processing the sum of the areas of the cells incorporated in each flip-flop cluster as the area of the flip-flop cluster; and selecting the cells that do not belong to any critical path so that the area of each flip-flop cluster is equal. An LSI layout design method comprising: adding an area of one of the clusters to an area of the flip-flop cluster and incorporating the flip-flop cluster. 4. A layout design of an LSI using a computer.
An LSI layout design method, which includes a method of designing a cell including a flip-flop in a circuit to be designed.
A timing system based on the netlist representing the connection relationship
Represents the connection relationship between flip-flops related to about
First processing for generating a flip-flop netlist
In the first processing in the given arrangement area.
According to the generated flip-flop netlist,
Each flip-flop is arranged, and each flip-flop is
For the flip-flop,
Each flip-flop area to be placed is determined.
And a flip-flop determined in the second process.
In the area, the cell related to the corresponding flip-flop is
And a third process for arranging the cells, respectively, based on the cell arrangement performed in the third process.
The first processing is to generate a flip-flop netlist having cell area information related to each flip-flop, and the second processing is to perform the first processing. A process of evenly arranging each flip-flop on a given arrangement area in accordance with the flip-flop netlist generated in the process; Deciding a flip-flop region by dividing the placement region in accordance with the layout region. 5. An LSI layout design using a computer.
An LSI layout design method, which includes a method of designing a cell including a flip-flop in a circuit to be designed.
A timing system based on the netlist representing the connection relationship
Represents the connection relationship between flip-flops related to about
First processing for generating a flip-flop netlist
In the first processing in the given arrangement area.
According to the generated flip-flop netlist,
Each flip-flop is arranged, and each flip-flop is
For the flip-flop,
Each flip-flop area to be placed is determined.
And a flip-flop determined in the second process.
In the area, the cell related to the corresponding flip-flop is
And a third process for arranging the cells, respectively, based on the cell arrangement performed in the third process.
Te, which performs layout design, the third process, the the process of obtaining the shortest path between the flip-flops arranged in the second processing, the cells belonging to the critical path, the starting point of the critical path And arranging a cell that does not belong to any critical path in an empty area in the flip-flop area corresponding to the flip-flop to which the cell is related. An LSI layout design method, comprising: