JP3085067B2 - Wiring board and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for various electronic devices.

[0002]

2. Description of the Related Art As electronic devices become smaller and have higher performance, higher density and higher reliability are also required for wiring boards used therein. In order to increase the density, the width of the wiring on the wiring board has become smaller, and the wiring has a higher hierarchy with an insulating layer interposed. As described above, as the electrode material of the wiring board, Cu, which has a lower resistance and is advantageous in terms of cost, is often used, and C is placed above and below the Cu layer to adhere to the insulating substrate and the upper insulating film.
A three-layer conductor layer having an r layer is used.

An example of the above-described conventional wiring board will be described below with reference to the drawings. FIG. 13 shows a cross-sectional configuration of a conventional wiring board. In FIG. 13, 6
1 is an insulating substrate such as glass, 62 is a first Cr layer, 63
Is a Cu layer, 64 is a second Cr layer, and 65 is a Si-based insulating layer. The Cu layer 63 is a conductive layer, and the Cr layers 62 and 64
Plays a role of a Cu migration prevention layer and an adhesion layer.

[0004]

However, in the above configuration, after forming the conductor layer by a vacuum process or the like,
Since a process such as etching is performed to form a wiring pattern, the outermost second Cr layer 64 is covered with an oxide or the like. For this reason, when placed in a high-temperature, high-humidity environment or the like, peeling may occur at the interface between the Si-based insulating layer 65 and the second Cr layer 64.

The present invention has been made in view of the above problems, and has been made in consideration of the problems described above.
The present invention provides a wiring board having sufficient reliability without causing separation between Cr layers.

[0006]

In order to solve the above-mentioned problems, a wiring board according to the present invention comprises an insulating substrate, a first Cr layer provided on the insulating substrate, and a first Cr layer provided on the first Cr layer. , A second Cr layer provided on the Cu layer, and an insulating layer covering the first Cr layer, the Cu layer, and the second Cr layer. Is the first Cr
And a diffusion layer formed by subjecting the Cu layer to a heat treatment in a vacuum or a reducing atmosphere.

[0007]

According to the present invention, as described above, a first Cr layer and a Cu layer are sequentially formed on an insulating substrate, and a pattern is formed. By diffusing Cr on the surface, a second Cr layer having an active surface can be formed. By forming the insulating layer without breaking the vacuum as it is, the active element C
A chemical bond is formed between r and an element constituting the insulating layer, whereby the adhesion between the insulating layer and the second Cr layer can be improved and separation can be prevented.

[0008]

(Embodiment 1) A wiring board according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 2 shows a cross-sectional configuration of a wiring board according to a first embodiment of the present invention. In FIG. 1, 1 is an insulating substrate such as glass, 2 is a first Cr layer, 3 is a Cu layer, 4 is a second Cr layer formed by vacuum heat treatment, and 5 is an insulating layer such as SiO _2. .

FIG. 2 shows a process of forming a wiring board in this embodiment. First, a first Cr layer 2 and a Cu layer 3 are formed on an insulating substrate 1 such as glass by a method such as vapor deposition or sputtering. Next, a pattern is formed on this electrode by a method such as etching. After that, heat treatment is performed in vacuum to
Is formed, and an insulating layer 5 is formed on the substrate while maintaining the vacuum state. Therefore, this heat treatment is desirably performed in the film formation chamber for the insulating layer 5.

The second Cr layer 4 is formed by diffusing Cr atoms of the first Cr layer 2 in the Cu layer 3 and depositing on the surface, and has a very small thickness. . The heat treatment conditions at this time are affected by the conditions of the thickness of the Cu layer 3, the processing temperature, the time, and the degree of vacuum.
The temperature must be 0 ° C. or higher, and the degree of vacuum must be 1 × 10 ⁻³ to 1 × 10 ⁻⁷ Torr. In the case of this embodiment, the thickness of the Cu layer 3 is 400 ° C. to 3000 Å, 3 hours, 1 × 10 ^-4 ~
By performing a vacuum heat treatment at 1 × 10 ⁻⁶ Torr, C
The second Cr layer 4 having a thickness of about 200 ° was formed on the surface of the u layer 3.

FIG. 3 shows the distribution of elements at the interface between the second Cr layer 4 and the insulating layer 5 in the present embodiment using SiON for the insulating layer 5. As shown in the figure, it can be seen that an extremely thin second Cr layer 4 exists at this interface. This second Cr layer 4
Since a Cr surface having few impurities such as oxygen can be obtained on the surface thereof, an interface having extremely good adhesion can be obtained by forming the insulating layer 5 on the substrate while maintaining the vacuum state after the vacuum heat treatment.

In addition, this method requires less wiring layers in the film forming process than in the conventional example. Further, the second Cr layer 4 is formed on the pattern of the Cu layer 3 by performing a vacuum heat treatment after the pattern formation.
The r layer 4 does not require pattern formation, and can simplify the etching process at the time of pattern formation as compared with the conventional example.

As described above, according to this embodiment, the insulating layer 5
Prior to the formation of the second layer, a vacuum heat treatment is applied to the two-layered wiring of the Cu layer 3 and the first Cr layer 2 to form a second Cr layer 4 on the surface of the Cu layer 3, and the insulating layer 5 is maintained while maintaining the vacuum. By this, the adhesion between the wiring layer and the insulating layer 5 can be greatly improved, and at the same time, the film forming step and the pattern forming step can be simplified.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view of a wiring board according to a second embodiment of the present invention. FIG.
, 11 is an insulating substrate such as glass, 12 is a first Cr layer, 13 is a Cu layer, 14 is a second Cr layer, and 15 is S
It is an insulating layer such as iO ₂ . In this embodiment, the first Cr layer 12, the Cu layer 13, and the second Cr layer 14 are all formed by a film forming method such as vapor deposition or sputtering. Is formed.

FIG. 5 shows a process of forming a wiring board in the second embodiment. First, a first Cr layer 12, a Cu layer 13, and a second Cr layer 14 are formed on an insulating substrate 11 such as glass. Next, a pattern is formed on this electrode by a method such as etching. Thereafter, by performing a heat treatment in a reducing atmosphere, an adsorbed substance such as an oxide layer and water on the surface of the second Cr layer 14 is removed, and a surface of Cr which is an originally active element is formed. While keeping this state, the insulating layer 15 is formed by using the same chamber or the like.

Since the second Cr layer 14 undergoes a process such as etching after its formation, its surface is covered with an adsorbate such as water or an inert oxide. When the insulating layer 15 as a protective film is formed on the inactive surface, strong adhesion between the two may not be obtained, which may cause peeling. Therefore, in this embodiment, before forming the insulating layer 15, the wiring substrate is subjected to a heat treatment in a reducing atmosphere to clean and activate the surface of the second Cr layer 14 so that the insulating layer 15 and the second
This improves the adhesion between the Cr layers 14. The heat treatment temperature is suitably 300 ° C. or higher, and in this embodiment, the heat treatment was performed at 400 ° C. for 1 hour. Hydrogen was used as the reducing gas, and the degree of vacuum was about 1 mTorr. After this heat treatment, the insulating layer 15 was formed without exposing the substrate to the air to maintain an active surface. Therefore, it is desirable that this heat treatment be performed in the film formation chamber for the insulating layer 15.

As described above, according to the present embodiment, the insulating layer 1
By performing a heat treatment in a reducing atmosphere before forming 5, an adsorbed substance or the like on the surface of the second Cr layer 14 is removed to form an active surface, and the insulating layer 1 is maintained while maintaining the surface state.
5 to form the second Cr layer 14 and the insulating layer 15.
Greatly improves adhesion to

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In FIG.
21 is an insulating substrate such as glass, 22 is a first Cr layer, 2
3 is a Cu layer, 24 is a second Cr layer, and 25 is an insulating layer such as SiO ₂ .

FIG. 7 shows a process of manufacturing a wiring board according to the third embodiment. First, the first Cr layer 22 and C are deposited on an insulating substrate 21 such as glass by a film forming method such as evaporation or sputtering.
A u layer 23 and a second Cr layer 24 are formed. Next, a pattern is formed on this electrode by a method such as etching. Thereafter, the surface of the second Cr layer 24 is removed by a method such as sputter etching to remove adsorbed substances, oxide layers, and the like on the surface.
Form an active surface of r. While maintaining this state, the insulating layer 25 is formed on the substrate by using the same chamber or the like.

Since the steps up to the second Cr layer 24 are the same as those in the second embodiment, the surface of the second Cr layer 24 is covered with the adsorbed material as described above. When the insulating layer 25 is formed as a layer, it may cause peeling. In this embodiment, before forming the insulating layer 25, the surface of the wiring substrate is sputter-etched to remove an inactive layer such as adsorbed substances and oxides on the surface of the second Cr layer 24 to obtain an active surface. As a result, the insulating layer 25 and the second Cr layer 2
4 could be significantly improved. In the case of this embodiment, Ar is used as the sputtering gas, and the second Cr
After the substrate surface formed up to the layer 24 is sputter-etched for several minutes, the insulating layer 2 is continuously maintained while maintaining a vacuum state.
5 was formed.

As described above, according to the present embodiment, the insulating layer 2
By performing dry etching such as sputter etching on the surface of the second Cr layer 24 before the formation of
By removing an inactive layer such as adsorbate and oxide on the surface of the Cr layer 24 to form an active surface and forming the insulating layer 25 while maintaining the surface state, the wiring layer and the insulating layer 25 are formed.
Greatly improves adhesion to

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows a sectional structure of a wiring board according to a fourth embodiment of the present invention. FIG.
, 31 is an insulating substrate such as glass, 32 is a first Cr layer, 33 is a CuCr alloy layer, 34 is a second Cr layer,
Reference numeral 35 denotes an insulating layer such as SiO ₂ . CuCr of this embodiment
The alloy layer 33 is formed by a film forming method such as evaporation or sputtering, and the Cr concentration in the CuCr alloy layer 33 is 0.1 to 1
It is about 0%. For the alloying of Cu and Cr, a sputtering target of an alloy of Cu and Cr was used, and in the case of vapor deposition, an evaporation source of an alloy of Cu and Cr was used.
And Cr may be simultaneously sputtered on separate targets or simultaneously evaporated using different evaporation sources.

First Cr layer 32 and second Cr layer 34
Is formed by forming a CuCr alloy layer 33 and then performing a heat treatment thereon. Since Cu and Cr are metals that hardly form a solid solution, Cr in the CuCr alloy layer 33 is C
It exists in the crystal grain boundary of u and is in a relatively unstable state, and is easily moved by heating or the like. Therefore, by heating this, Cr in the grain boundaries becomes more stable CuC
The first Cr layer 32 and the second Cr layer 34 are deposited on the surface of the r alloy layer 33 and formed.

The thicknesses of the first Cr layer 32 and the second Cr layer 34 are small, and are affected by conditions such as the thickness of the CuCr alloy layer 33, the processing temperature, and the time. First Cr layer 3
In order to form the second and second Cr layers 34, the temperature is 300 ° C. or more and the degree of vacuum is 1 × 10 ⁻³ to 1 × 10 ⁻⁷ Torr.
The condition of r is required. In the case of the present embodiment, 3000
Ｃｕ, 3 hours, 1 ×
The first Cr layer 32 and the second Cr layer 34 were formed by performing a vacuum heat treatment at 10 ^-4 to 1 × 10 ^-6 Torr.

FIG. 9 shows a process of forming a wiring board according to the fourth embodiment. First, C is placed on an insulating substrate 31 such as glass.
The uCr alloy layer 33 is formed using the method described above. Next, a pattern is formed on this electrode by a method such as etching. Then, by performing vacuum heat treatment on this substrate,
A first Cr layer 32 and a second Cr layer 34 are formed. After the formation of the first and second Cr layers 32 and 34, an insulating layer 35 is formed on the substrate while maintaining the vacuum state. As described above, the first Cr layer 32 and the second Cr layer
The layer 34 is formed in a vacuum, and its surface is an active surface free of oxides and the like.
The adhesion with No. 1 is good. In addition, since the film formation and pattern formation need only be performed with the CuCr alloy layer 33, simplification of the process can be achieved.

It should be noted that by using this configuration, a relatively good result can be obtained with respect to the adhesion since a certain amount of Cr is precipitated on the surface of the CuCr alloy layer 33 without heat treatment. However, in this configuration, since a large amount of Cr remains in the CuCr alloy layer 33, its electrical resistance is higher than that of Cu, and it is not very suitable as a wiring layer. Therefore, by performing vacuum heat treatment on this substrate and depositing Cr in the CuCr alloy layer 33 on the surface as in the present embodiment, the adhesion strength is further improved, and
By reducing the electric resistance, a structure suitable for a wiring layer can be obtained.

As described above, according to the present embodiment, a CuCr alloy is used for the wiring layer provided on the insulating substrate 31 and the insulating layer 3 is used.
By performing a vacuum heat treatment before the formation of CuC5, the CuC
a first Cr layer 32 and a second C layer
An r layer 34 is formed, and the insulating layer 3
By forming 5, a wiring substrate having good adhesion between the insulating substrate 31, the wiring layer, and the insulating layer 35 can be realized, and at the same time, the film forming step and the pattern forming step can be simplified. it can.

(Embodiment 5) Hereinafter, an embodiment of the present invention will be described with reference to the drawings of Embodiment 1. FIG.
1 shows a cross-sectional configuration of the wiring board according to the first embodiment of the present invention, wherein 1 is an insulating substrate such as glass, and 2 is a first Cr substrate.
Layer 3, a Cu layer, 4 a second layer formed by vacuum heat treatment.
The Cr layer 5 is an insulating layer such as SiO ₂ . In this embodiment, a CuNi alloy layer is used instead of the Cu layer 3 of the wiring board.

The CuNi alloy layer 3 of this embodiment was formed by sputtering using a CuNi alloy target.
It may be formed by an evaporation method using a CuNi alloy evaporation source. The CuNi alloy layer 3 can be formed by using separate targets and evaporation sources of Cu and Ni. However, since the CuNi alloy layer 3 can be formed by exactly the same method as the case of forming the Cu layer, the present embodiment Used a CuNi alloy target.

When the wiring board using pure Cu for the conductor layer is placed in a bad environment such as a high-temperature high-humidity environment or a corrosive environment as in the first embodiment, it is possible to peel off between the Cu layer and the Cr layer. there were. This is because Cu and Cr are both metals, but they hardly form a solid solution, so their bonding is weak at this interface. Therefore, if moisture penetrates through pinholes in the insulating layer at this part, it will peel off at this interface. May occur. On the other hand, Ni is completely dissolved in both Cu and Cr and easily forms an alloy. CuNi alloy is a corrosion-resistant alloy, and CNi
Corrosion resistance can be improved by adding Ni to u. Therefore, in the present embodiment, by adding Ni to Cu, alloying was promoted at the interface between the Cu layer and the Cr layer to improve the adhesion, and the above problem was solved.

FIG. 10A shows the interface between the Cu layer and the Cr layer.
FIG. 10B shows a SIM at the interface between the CuNi alloy layer and the Cr layer.
It is an S analysis result. Ni concentration in CuNi alloy layer is 5%
In the figure, the Ni count number is drawn above the concentration ratio due to the difference in the analytical sensitivity between Cu and Ni. In both cases, the conditions are the same as those after the film formation of the insulating layer 5.
After the formation of the Cu layer or the CuNi alloy layer, heat treatment is performed in a vacuum. From these results, it was found that the CuNi alloy layer was
It can be seen that alloying is progressing at the interface with the layer. In this analysis, heat treatment was performed to facilitate the alloying in order to make the results easier to understand.However, even when heat treatment was not performed, improvement in adhesion was observed. It seems that alloying is progressing.

Table 1 shows the results of a reliability test of a wiring board prepared by changing the Ni concentration in the CuNi alloy. In the test, the wiring board was left for 500 hours under conditions of a temperature of 65 ° C. and a humidity of 90%, and then an adhesion test was performed to evaluate the ratio of the peeled sample. From these results, it was found that instead of the Cu layer, C
By using the uNi alloy layer, the reliability is greatly improved, and the effect of this embodiment is recognized.

[0033]

[Table 1]

From the results shown in Table 1, it was confirmed that the effect was obtained even with a Ni concentration of about 1%. In this embodiment, C
Although a CuNi alloy layer was used instead of the u layer, CuNiC
Similar effects can be obtained by using an r alloy layer.

Embodiment 6 Hereinafter, a wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG.
Shows a sectional configuration of a wiring board according to a sixth embodiment of the present invention. In FIG. 11, reference numeral 41 denotes an insulating substrate such as glass, reference numeral 42 denotes a first Cr layer of a lower wiring, reference numeral 43 denotes a Cu layer of a lower wiring, reference numeral 44 denotes a second Cr layer of a lower wiring, and reference numeral 45 denotes a lower Cr wiring.
Is an insulating layer of SiO ₂ or the like, 46 is a Cr layer of an upper wiring, 47
Is a Cu layer of the upper wiring.

The lower wiring in this embodiment is the same as that in the first and second embodiments.
It is formed using the methods of 2, 3, 4 and 5. An insulating layer 45 is formed between the lower wiring and the upper wiring, and a hole (hereinafter, referred to as a via hole) 48 for connecting upper and lower wirings is formed in the insulating layer 45. In this embodiment, after forming a resist pattern on the insulating layer 45 by photolithography, the via hole 48 is formed by wet etching. This hole may be formed using dry etching. After the formation of the via hole 48, the second Cr layer 44 of the lower wiring is etched to expose the Cu layer 43. Thereafter, an upper layer wiring is formed. The reason why the second Cr layer 44 is removed is that this forms an oxide layer on the surface and lowers the connection resistance with the upper layer wiring. The upper layer wiring is formed by a method such as sputtering or vapor deposition like the lower layer wiring,
The pattern is formed by photolithography technology.
In place of the Cu layer 47, a CuNi alloy layer having good adhesion to the Cr layer or a CuNiC
An r alloy layer may be used.

FIG. 12 shows an application example of the wiring board of the present invention. This is an application example to a multi-chip module (hereinafter, referred to as MCM). 12, 51 is a wiring board of the present invention, 52 is an IC chip, 53 is a chip component, 5
Reference numeral 4 denotes a lead frame for connecting the wiring board 51 to an external board. The above is made into one module unit and mounted on a motherboard 55 such as a printed wiring board.
This MCM integrates a plurality of components and requires a high level of technology for mounting, and therefore has a high added value. Therefore, high reliability is required for the wiring board. Can be satisfied.

[0038]

As described above, the present invention provides an insulating substrate,
A first Cr layer provided on the insulating substrate, a Cu layer provided on the first Cr layer, and a second Cr layer provided on the Cu layer.
A first Cr layer, a Cu layer, and a second
And an insulating layer covering the Cr layer of
Adhesion between the insulating layer and the second Cr layer is provided because the first Cr layer and the Cu layer have a diffusion layer formed by heat treatment in a vacuum or a reducing atmosphere. It is possible to realize a wiring substrate that can improve the performance and prevent peeling.

[Brief description of the drawings]

FIG. 1 is a sectional view of a wiring board according to a first embodiment of the present invention.

FIG. 2 is a view showing a process of manufacturing a wiring board according to the first embodiment;

FIG. 3 is an element distribution diagram in a depth direction of a wiring portion of the wiring board in the first embodiment.

FIG. 4 is a sectional view of a wiring board according to a second embodiment of the present invention;

FIG. 5 is a drawing showing a manufacturing process of a wiring board according to a second embodiment.

FIG. 6 is a sectional view of a wiring board according to a third embodiment of the present invention.

FIG. 7 is a drawing showing a manufacturing process of a wiring board according to a third embodiment.

FIG. 8 is a sectional view of a wiring board according to a fourth embodiment of the present invention.

FIG. 9 is a view showing a manufacturing process of a wiring board according to a fourth embodiment.

FIG. 10 (a) shows a conventional example of a wiring board with a Cu layer and C
Element distribution diagram in the depth direction of the interface of the r layer (b) CuN of the wiring substrate in the fifth embodiment of the present invention
Element distribution diagram in the depth direction at the interface between i-alloy layer and Cr layer

FIG. 11 is a sectional view of a wiring board according to a sixth embodiment of the present invention.

FIG. 12 is a perspective view of one application example of a wiring board according to a sixth embodiment.

FIG. 13 is a cross-sectional view of a conventional wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Insulating substrate 12 1st Cr layer 13 Cu layer 14 2nd Cr layer 15 Insulating layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-133402 (JP, A) JP-A-3-3298 (JP, A) JP-A-62-51775 (JP, U) 51076 (JP, B2) JP 59-46311 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 1/09 H05K 3/38 H05K 3/46

Claims (9)

(57) [Claims] 1. An insulating substrate, a first Cr layer provided on the insulating substrate, a Cu layer provided on the first Cr layer, and a second Cr layer provided on the Cu layer And an insulating layer covering the first Cr layer, the Cu layer, and the second Cr layer, wherein the second Cr layer includes the first Cr layer and the Cu layer.
A wiring substrate comprising a diffusion layer formed by heat-treating the Cu layer in a vacuum or a reducing atmosphere. 2. An insulating substrate, a first Cr layer provided on the insulating substrate, and a CuC provided on the first Cr layer.
r alloy layer and a second Cr layer provided on the CuCr alloy layer.
And an insulating layer covering the first Cr layer, the CuCr alloy layer, and the second Cr layer. The first and second Cr layers are formed by heat-treating the CuCr alloy layer in a vacuum. Wiring board made of a diffusion layer. 3. The method according to claim 1, wherein a CuNi alloy layer or a CuNiCr alloy layer is used instead of the Cu layer.
The wiring board as described. 4. The method according to claim 1, wherein CuNiCr is used instead of the CuCr alloy layer.
3. The wiring board according to claim 2, wherein an alloy layer is used. 5. Instead of a Cr layer, Ti or Ti and Cr
3. The wiring board according to claim 1, wherein an alloy of the above is used. 6. A step of forming a first Cr layer on an insulating substrate, a step of forming a Cu layer on the first Cr layer, and a step of forming a second Cr layer on the Cu layer. Forming,
Forming an insulating layer so as to cover the first Cr layer, the Cu layer, and the second Cr layer;
The method for manufacturing a wiring board, wherein the r layer is formed by heat-treating the first Cr layer and the Cu layer in a vacuum or a reducing atmosphere. 7. The insulating layer is formed by heat treatment of the second Cr layer.
Vacuum state or reducing atmosphere state when formed
7. The wiring according to claim 6, wherein the wiring is formed in a state.
Substrate manufacturing method. 8. A process for forming a CuCr layer on an insulating substrate.
By heat-treating this CuCr layer in a vacuum,
First and second C layers are respectively formed on the upper and lower surfaces of this CuCr layer.
forming an r layer, and forming these first Cr layer and C
forming an insulating layer so as to cover the uCr layer and the second Cr layer
And a method of manufacturing a wiring board. 9. The insulating layer according to claim 1, wherein said first and second Cr layers are heat-treated.
It is formed while maintaining the vacuum state when forming by
9. The method for manufacturing a wiring board according to claim 8, wherein
Law.