JP3085362B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a delay circuit, and more particularly to a delay circuit using a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent semiconductor technology, hundreds of thousands of elements are housed in one chip, and various functional circuits such as logical operation circuits are formed in a semiconductor. Delay circuits are widely used in clock circuits, synchronization signal generation circuits, timing match circuits, and the like that require the delay time, and are also used in various other fields.

FIG. 6 shows an example of a conventional delay circuit. 6, MP1 and MP2 are P-channel MOS transistors, MN1 is an N-channel MOS transistor,
R1 is a resistor and C1 is a capacitor. The signal input from IN passes through the first P-channel MOS transistor MP1. At this time, only when the signal rises, the signal is delayed by the time constant of R1 and C1, and the output stage inverter (MP
1, MN1) and is output in phase with the input signal.

[0004]

However, in the conventional delay circuit shown in FIG. 6, since the delay time is set by a time constant circuit composed of the resistor R1 and the capacitor C1, the element fluctuation is not changed. Appears as fluctuations. That is, the delay time greatly fluctuates due to variations in devices and fluctuations in conditions such as temperature and humidity.

An object of the present invention is to provide a delay circuit capable of obtaining a constant delay while minimizing the influence of fluctuations in device conditions.

[0006]

The delay circuit according to the present invention is configured as follows to achieve the above-mentioned object. The delay circuit according to the present invention comprises a first P-channel MOS
The transistor has a source connected to a positive power supply, and a resistor R1 and a capacitor C1 connected in parallel between the drain and the negative power supply. The drain of the first P-channel MOS transistor is connected to the fourth P-channel MOS transistor.
The gate of the channel MOS transistor is connected to the gate of the second N-channel MOS transistor. First
The N-channel MOS transistor has a gate connected to a positive power supply, a resistor 2 connected between the drain and the positive power supply, and a source connected to a negative power supply. The second P-channel MOS transistor has a source connected to a positive power supply, a gate connected to a negative power supply, and a drain connected in series to the resistor 3. The drain of the second N-channel MOS transistor is connected to the fourth P-channel MOS transistor.
Connected to the drain of the channel MOS transistor,
The source is connected to the drain of the third N-channel MOS transistor, and the gate is connected to the drain of the first P-channel MOS transistor. The third N-channel MOS transistor has a source connected to a negative power supply, a gate connected to the drain of the second P-channel MOS transistor, and a drain connected to the source of the second N-channel MOS transistor. The third P-channel MOS transistor has a source connected to a positive power supply and a gate connected to the first N-channel MOS transistor.
The drain and the drain of the S transistor are connected to the source of the fourth P-channel MOS transistor. The fourth P-channel MOS transistor has a source connected to the drain of the third P-channel MOS transistor and a gate connected to the first P-channel MOS transistor.
Is connected to the drain of the second N-channel MOS transistor. With the configuration as described above, the input from the gate of the first P-channel MOS transistor
Channel MOS transistor and second N-channel M
It is output from the drain of the OS transistor.

In this delay circuit, first and third N-channel MOS transistors and second and third P-channel M transistors are provided.
A variation adjustment unit including an OS transistor and second and third resistors suppresses variation in delay time due to element variation.

The fluctuation adjusting section adjusts the threshold level and the switching speed of the output stage inverter section so as to keep the delay value constant with respect to the resistance value and the condition fluctuation of each transistor, thereby suppressing the fluctuation of the delay value and stabilizing it. A delay time is added to the rising edge of the input signal. still,
The term “condition variation” particularly refers to variations in the transistor manufacturing process and environmental changes in temperature and humidity.

Also, the present invention provides an input signal for delaying an input signal.
A power unit and an output inverter having an output from the input unit as an input
In the delay circuit having:
Connected to the input terminal, the source connected to the positive power supply,
The drain is a first P channel connected to a resistor and a capacitor.
Transistor and the other terminal of the resistor and the capacitor are negative.
A delay adding section connected to a power supply;
The inverter is connected between the output inverter and the positive power supply.
A third P-channel transistor,
A third N channel connected between the inverter and the negative power supply.
Change in the resistance value of the resistor
The first and second directions in which the output voltage changes in the same direction as the
And a second fluctuation range adjusting unit, wherein the third P channel
Transistor and the third N-channel transistor
The first and second fluctuation ranges
The output voltage of the adjustment unit is supplied to suppress fluctuations in the amount of delay
It is characterized by the following. Also, the delay circuit is characterized in that before Ki抵 <br/> anti Gajo current source.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] Next, Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, and is an example in which a delay circuit is configured by a CMOS transistor.

First, the configuration will be described. In FIG. 1, the delay circuit includes a delay adding unit, a fluctuation width adjusting unit, and an output stage inverter unit.

The delay adding section is composed of a P-channel MOS transistor MP1, a resistor R1, and a capacitor C1. In this delay adding section, the delay increases when the resistance R1 and the capacitance C1 increase, and decreases when the resistance R1 and the capacitance C1 decrease. In the circuit of FIG. 1, a large delay is added only to the rise of the input signal. P channel MO
The source of the S transistor MP1 is connected to the positive power supply VDD, the drain is connected to R1 and C1, the other terminals of R1 and C1 are connected to the negative power supply VSS, and the P-channel
A signal is input from the gate of S transistor MP1.

The fluctuation width adjusting section is composed of P-channel MOS transistors MP2 and MP3, N-channel MOS transistors MN1 and MN3, and resistors R2 and R3.
The drain of the N-channel MOS transistor MN1 is connected to the resistor R2, and the other of the resistor R2 is connected to the positive power supply VD.
D, its source is connected to the negative power supply VSS, and its gate is connected to the positive power supply VDD. P channel MO
The source of the S transistor MP2 is a positive power supply, the gate is a negative power supply, the drain is a resistor R3, and the resistor R3
Is connected to the negative power supply VSS. The source of the P-channel MOS transistor MP3 is a positive power supply VDD.
And its gate is an N-channel MOS transistor MN
1 is connected to the source of the P-channel MOS transistor MP4. The source of the N-channel MOS transistor MN3 is a negative power supply VSS.
And its drain is an N-channel MOS transistor M
The source of N2 is connected at its gate to the drain of P-channel MOS transistor MP2.

The output stage inverter section is a P-channel MO
It comprises an S transistor MP4 and an N channel MOS transistor MN2. The source of the P-channel MOS transistor MP4 is a P-channel MOS transistor M
The drain of P3 has its gate connected to the drain of P-channel MOS transistor MP1, and its drain connected to the source of N-channel MOS transistor MN2 and output OUT.
Connected to. N-channel MOS transistor MN2
Has a source connected to the drain of the N-channel MOS transistor MN3, a gate connected to the drain of the P-channel MOS transistor MP1, and a drain connected to the P-channel MOS transistor MN3.
The drain of the transistor MP4 is connected to the output OUT. The resistors R1 to R3 are generally diffusion resistors, and the resistance decreases as the environmental temperature rises, similarly to the semiconductor. Further, it is preferable that the resistance values of the resistors R1 to R3 are close to each other, and the method of forming the resistors is preferably the same, but is not limited to the same.

The details of the operation will now be described. In the delay adding unit, MP1 has a source of a positive power supply and a gate of an input terminal IN
, And the drain is connected to a negative power supply via a resistor R1 and a capacitor C1. When the input terminal voltage rises,
MP1 is turned off, and the voltage between the drain of MP1 and the negative power supply tends to drop to the 0 level, but the voltage drops gently due to the time constant of the resistor R1 and the capacitor C1. Since the time constant τ at this time is represented by τ = C1 × R1, the delay obtained by the circuit becomes slow as the resistance value increases. Due to this time constant, a delay is added only when the input signal rises. This state is shown in FIG. In response to the input signal at the input terminal IN, a signal whose phase is inverted is obtained at the drain of the P-channel MOS transistor MP1, and the delay time varies depending on the threshold value of the inverter circuit with respect to the waveform at the time of startup.

Time until the voltage between the drain of MP1 and the negative power supply VSS decreases to the threshold (threshold) level of the output stage inverter section composed of the P-channel MOS transistor MP4 and the N-channel MOS transistor MN2. The switching speed of the output stage inverter is a major factor that determines the delay time.

If the resistance component fluctuates in a direction in which the resistance component increases due to variations in the transistor or resistance due to a process change in semiconductor manufacturing, or fluctuations in conditions such as environmental temperature in use,
Since the resistance value of the resistor R2 similarly increases, the voltage between the gate and the source of the P-channel MOS transistor MP3 increases. Similarly, since the resistance value of the resistor R3 also increases, the voltage between the gate and the source of the N-channel MOS transistor MN3 increases, and both the on-resistances of MP3 and MN3 decrease. And the output stage inverter section (MP4 and MN
The switching speed of 2) is increased, which acts to increase the delay value of the delay circuit. However, if the resistance component fluctuates to the increasing side, the delay time of the circuit itself largely fluctuates, so that the fluctuation of the operation speed of the output-stage inverter becomes faster.

If the resistance component fluctuates to a smaller value, the resistance value of the resistor R2 becomes smaller.
The voltage between the gate and the source of the OS transistor MP3 decreases. The resistance value of the resistor R3 also decreases, and the N-channel M
The voltage between the gate and the source of the OS transistor MN3 decreases. This increases the on-resistance of MP3 and MN3,
The switching speed of the output-stage inverter section decreases. When the resistance component decreases, the delay time of the circuit itself fluctuates to a small extent, so that the fluctuation of the operation speed of the output-stage inverter is suppressed.

When the on-resistance of the P-channel MOS transistor increases due to environmental fluctuations, the on-resistance of MP2 increases, so that the voltage between the gate and source of MN3 decreases. As a result, the ON resistance of MN2 increases. MP3
Since the resistance also fluctuates greatly, the fluctuation of the threshold level of the output stage inverter is suppressed, and the delay amount is kept constant. Conversely, when the on-resistance of the P-channel MOS transistor decreases, the on-resistances of MN2 and MP3 also decrease at the same time, so that the delay amount is kept constant.

Similarly, when the N-channel MOS transistor fluctuates, the N-channel MOS transistor MN1 affects the voltage between the gate and the source of the P-channel MOS transistor MP3, and the P-channel MOS transistor M3
It works in the direction of correcting the deviation of the threshold level due to the fluctuation of P3 and MP4.

As described above, a stable delay can always be obtained by reducing the influence of the fluctuation of the resistance component and the fluctuation of the transistor.

[Embodiment 2] FIG. 2 is a circuit diagram of the circuit shown in FIG. MN1 and MP
2 is connected to another positive power supply (VDD2) instead of the positive and negative power supplies. Another positive power supply VDD2
Is set to an intermediate potential between the positive and negative power supplies VDD and VSS.
Therefore, the power supply VDD2 may be the ground potential of the virtual reference potential.

The operation is the same as in FIG. That is,
For example, when the temperature rises due to a change in environmental conditions, when the resistance value of the resistor R1 decreases, the resistances R2 and R3 also decrease, the gate-source voltage of the P-channel MOS transistor MP3 decreases, and the N-channel MOS transistor MP3 decreases.
The voltage between the gate and the source of the S transistor MN3 decreases. As a result, the on-resistances of MP3 and MN3 increase, and the switching speed of the output-stage inverter decreases.
When the resistance component decreases, the delay time of the circuit itself fluctuates to a small extent, so that the fluctuation of the operation speed of the output-stage inverter is suppressed. Also, the operation of the first embodiment is the same when the resistance value of the resistor R1 increases.

[Embodiment 3] FIG. 3 shows the resistors R1 and R shown in FIG.
2 and R3 are replaced with constant current sources.

In this configuration, there is no influence of the change in the condition of the resistance component, and there is a function of suppressing the change with respect to the change in the environmental condition of the transistor.

The case where the P channel fluctuates will be described.
When the ON resistance of the P channel increases, the ON resistance of MP2 increases and the voltage between the gate and source of MN3 decreases. As a result, the ON resistance of MN3 increases,
Since the ON resistance of N2 also increases, the threshold level deviation of the inverter (comprising MP4 and MN2) is corrected.

When the on-resistance of the P-channel decreases, the on-resistance of MP2 decreases, and the voltage between the gate and source of MN3 increases. As a result, the ON resistance of MN3 decreases, the ON resistance of MN2 decreases, and the threshold level of the inverter (composed of MP4 and MN2) is corrected so as to approach the positive power supply / 2.

In the case of N-channel fluctuation, the same operation is performed by N-channel MOS transistors MN1, MP3 and MP3.
Get up on MP4.

[Embodiment 4] FIG. 4 shows MN1 and MP shown in FIG.
2 is connected not to the positive power supply and the negative power supply but to another positive power supply (VDD2) and the resistance components R1 and R2 are connected.
2 and R3 are all replaced by constant current sources.

The operation is the same as in the third embodiment. For example,
The case where the P-channel MOS transistors MP1, MP2 and the like fluctuate will be described. When the ON resistance of the P channel increases, the ON resistance of MP2 increases and MN3
, The voltage between the gate and the source becomes lower. MN3
And the ON resistance of MN2 also increases, so that the threshold level deviation of the inverter (comprising MP4 and MN2) is corrected.

[0031]

As described above, the delay circuit according to the present invention is subject to variations in manufacturing and conditions due to temperature.
This has the effect of suppressing the fluctuation of the delay amount with respect to the fluctuation of the resistance value and the condition of each transistor. Further, since the delay time of the present delay circuit is determined by the time constant of the resistance and the capacitance, a larger delay time can be obtained as compared with a case where the inverter is simply connected in cascade.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment according to the present invention.

FIG. 3 is a circuit diagram of a third embodiment according to the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment according to the present invention.

FIG. 5 shows input / output waveforms for explaining the present invention.

FIG. 6 is a circuit diagram of a conventional delay circuit.

[Explanation of symbols]

 R1 resistor 1 R2 resistor 2 R3 resistor 3 C1 capacitance MN1 N-channel MOS transistor 1 MN2 N-channel MOS transistor 2 MN3 N-channel MOS transistor 3 MN4 N-channel MOS transistor 4 MP1 P-channel MOS transistor 1 MP2 P-channel MOS transistor 2 MP3 P-channel MOS transistor 3 MP4 P-channel MOS transistor 4 VDD1 Positive voltage source VDD2 Positive voltage source VSS Negative voltage source IG1 Constant current source IG2 Constant current source IG3 Constant current source

Claims (5)

(57) [Claims] An input is connected to a gate of a first P-channel MOS transistor, and an input is connected to the first P-channel MOS transistor.
The source of the OS transistor is connected to the positive power supply, the drain is connected to the gates of the fourth P-channel MOS transistor and the second N-channel MOS transistor, and the drain of the first P-channel MOS transistor is connected to the negative power supply. A first resistor is connected therebetween, a first capacitor is connected in parallel to the first resistor, a gate of the first N-channel MOS transistor is connected to a positive power supply, and a source thereof is connected to a negative power supply. , The drain of which is connected to the gate of a third P-channel MOS transistor, the second resistor is connected between the drain of the first N-channel MOS transistor and a positive power supply,
The gate of the OS transistor is a negative power supply, the source is a positive power supply, and the drain is a third N-channel MOS.
A third P-channel MOS transistor connected between the drain of the second P-channel MOS transistor and a negative power supply;
Is connected, the source of the third P-channel MOS transistor is connected to the positive power supply, the drain is connected to the source of the fourth P-channel MOS transistor, and the drain of the fourth P-channel MOS transistor is connected to the positive power supply. The source of the second N-channel MOS transistor is connected to the drain of the second N-channel MOS transistor, the source of the second N-channel MOS transistor is connected to the drain of the third N-channel MOS transistor, and the source of the third N-channel MOS transistor is connected. Connected to a negative power supply,
A delay circuit, wherein a drain of the fourth P-channel MOS transistor and a drain of the second N-channel MOS transistor are connected to an output. 2. The delay circuit according to claim 1, wherein said first N-channel MOS transistor is connected to said second N-channel MOS transistor.
The gate voltage with the P-channel MOS transistor of
A delay circuit, wherein an intermediate voltage between the positive and negative power supply voltages is used . 3. The delay circuit according to claim 1, wherein said first , second, and third resistors are each a constant current source. 4. An input section for delaying an input signal;
And an output inverter having the output of the power section as an input.
In the Ray circuit, the input unit has a gate connected to an input terminal, and a source connected to the input terminal.
Connected to positive power supply, drain connected to resistance and capacitance
A first P-channel transistor, the resistor and the
The other terminal of the capacitor is composed of a delay addition unit connected to the negative power supply.
Made, the output inverter, said output inverter and a positive power supply and
A third P-channel transistor connected between
A third connected between the output inverter and a negative power supply;
An N-channel transistor, and outputs in the same direction and the opposite direction as the direction in which the resistance value of the resistor changes.
A first and a second fluctuation range adjusting unit for changing a force voltage;
For example, the third P-channel transistor and said third N
The gate of each channel transistor is
The output voltages of the second and first fluctuation width adjustment units are supplied and delayed.
A delay circuit characterized by suppressing fluctuations in the amount of delay. 5. A delay circuit as claimed in claim 4, the delay circuit which is a pre Ki抵 anti Gajo current source.