Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP3086014B2 - Method of forming GaAs semiconductor active layer - Google Patents
[go: Go Back, main page]

JP3086014B2 - Method of forming GaAs semiconductor active layer - Google Patents

Method of forming GaAs semiconductor active layer

Info

Publication number
JP3086014B2
JP3086014B2 JP03193949A JP19394991A JP3086014B2 JP 3086014 B2 JP3086014 B2 JP 3086014B2 JP 03193949 A JP03193949 A JP 03193949A JP 19394991 A JP19394991 A JP 19394991A JP 3086014 B2 JP3086014 B2 JP 3086014B2
Authority
JP
Japan
Prior art keywords
active layer
emission
annealing
forming
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03193949A
Other languages
Japanese (ja)
Other versions
JPH0536616A (en
Inventor
末広 杉谷
文明 日向
和義 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
NTT Inc USA
Original Assignee
Nippon Telegraph and Telephone Corp
NTT Inc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, NTT Inc USA filed Critical Nippon Telegraph and Telephone Corp
Priority to JP03193949A priority Critical patent/JP3086014B2/en
Publication of JPH0536616A publication Critical patent/JPH0536616A/en
Application granted granted Critical
Publication of JP3086014B2 publication Critical patent/JP3086014B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はイオン注入と熱処理(ア
ニール)とにより GaAs 結晶基板上に能動層を形成する
方法に係り、特に、高キャリア濃度で厚さの薄い能動層
を形成することが可能な GaAs 半導体能動層形成方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an active layer on a GaAs crystal substrate by ion implantation and heat treatment (annealing). A possible method for forming a GaAs semiconductor active layer.

【0002】[0002]

【従来の技術】GaAs 結晶基板にイオン注入することに
よって電界効果トランジスタ(FET)や集積回路を形成す
る場合に、注入不純物を電気的に活性化させて能動層を
形成する上で、アニール工程は不可欠な工程であり、注
入不純物の活性化率(注入不純物濃度に対するキャリア
濃度の割合)を向上させることは FET の特性向上の上で
重要な要素となる。
2. Description of the Related Art When a field effect transistor (FET) or an integrated circuit is formed by ion implantation into a GaAs crystal substrate, an annealing step is required to electrically activate implanted impurities to form an active layer. Improving the activation rate of implanted impurities (the ratio of carrier concentration to implanted impurity concentration) is an essential step in improving FET characteristics.

【0003】現在、GaAs FET のn形能動層形成には、
注入元素として Si が最も一般的に用いられている。Si
は IV 族元素であるために、III族元素である Ga の格
子位置を置換してドナーとなるが、一方、V 族元素であ
る As の格子位置を置換してアクセプターとなる。従っ
て、キャリア濃度はドナー濃度とアクセプター濃度との
差となる。ここで、アニール時間を一定とした場合に
は、比較的低いアニール温度では、イオン注入により失
われた結晶性が温度上昇とともに回復して、Ga格子位
置を占める Si が増加する。すなわち、アニール温
度とともにキャリア濃度が増大する。しかし、高温側で
は、As 格子位置を置換する Si が急激に増大するた
め、キャリア濃度は逆に減少する。従って、高活性化率
を得るためには、最適アニール温度で熱処理を行うこと
が必要となる。
At present, the formation of an n-type active layer of a GaAs FET requires:
Si is the most commonly used implantation element. Si
Is a group IV element, it becomes a donor by substituting the lattice position of Ga, a group III element, while it becomes an acceptor, substituting the lattice position of As, a group V element. Therefore, the carrier concentration is the difference between the donor concentration and the acceptor concentration. Here, when the annealing time is fixed, at a relatively low annealing temperature, the crystallinity lost by the ion implantation recovers with the temperature rise, and the Si occupying the Ga lattice position increases. That is, the carrier concentration increases with the annealing temperature. However, on the high temperature side, the amount of Si substituting the As lattice position increases rapidly, so that the carrier concentration decreases. Therefore, in order to obtain a high activation rate, it is necessary to perform heat treatment at an optimum annealing temperature.

【0004】最近、GaAs FET に対する高性能化の要請
が強く、この要請に応えるためには、高キャリア濃度で
厚さの薄い能動層を形成することが必須要件となってい
る。このような能動層を実現するためには、イオン注入
エネルギーを低減(30keV未満)し、高活性化率が得られ
る条件でアニールを行う必要がある。この最適アニール
条件はイオン注入条件に強く依存し、例えば、注入エネ
ルギーの減少とともに低温側または短時間側にシフトす
る。すなわち、厚い能動層に対する最適アニール条件と
薄い能動層に対する最適条件とは異なることになる。
Recently, there is a strong demand for high performance GaAs FETs, and in order to meet this demand, it is essential to form an active layer having a high carrier concentration and a small thickness. In order to realize such an active layer, it is necessary to reduce the ion implantation energy (less than 30 keV) and perform the annealing under the condition that a high activation rate can be obtained. This optimum annealing condition strongly depends on the ion implantation condition, and for example, shifts to a lower temperature side or a shorter time side as the implantation energy decreases. That is, the optimum annealing condition for the thick active layer is different from the optimum condition for the thin active layer.

【0005】[0005]

【発明が解決しようとする課題】最適アニール条件を決
めるための能動層評価の方法としては、従来、一般に、
ホール効果を利用した測定及び容量‐電圧(C‐V)測定の
電気的測定方法が用いられていた。能動層の表面付近に
は上記電気的測定では評価し得ない空乏層領域が存在す
るが、従来の厚い能動層においては表面空乏層領域の占
める割合が少ないため、上記測定方法で十分評価するこ
とが可能であった。しかし、30keV未満の低い注入エネ
ルギーで形成された能動層の場合には、能動層の厚さが
極めて薄いことから、能動層のかなりの部分が表面空乏
層領域で占められるため、上記の測定方法では十分に評
価できないという問題があり、従って、アニールの最適
条件が正確に求められないために、高キャリア濃度で薄
い能動層を形成することは極めて困難であった本発明の
目的は、上記従来技術の有していた課題を解決して、高
キャリア濃度で厚さの薄い能動層を実現することの可能
な GaAs 半導体能動層形成方法を提供することにある。
Conventionally, as a method of evaluating an active layer for determining an optimum annealing condition, conventionally, generally,
Electrical measurement methods using Hall effect measurement and capacitance-voltage (CV) measurement were used. Although there is a depletion layer region near the surface of the active layer that cannot be evaluated by the above electrical measurement, since the ratio of the surface depletion layer region in a conventional thick active layer is small, it should be sufficiently evaluated by the above measurement method. Was possible. However, in the case of an active layer formed with a low implantation energy of less than 30 keV, since the thickness of the active layer is extremely small, a considerable portion of the active layer is occupied by the surface depletion layer region. However, it is difficult to form a thin active layer with a high carrier concentration because the optimum conditions for annealing cannot be accurately determined. An object of the present invention is to provide a method for forming a GaAs semiconductor active layer capable of realizing a thin active layer with a high carrier concentration by solving the problems of the technology.

【0006】[0006]

【課題を解決するための手段】上記目的は、GaAs 結晶
基板上に注入した Si イオンをアニールすることにより
活性化させて能動層を形成する方法において、所定波長
領域の光を照射して能動層から放射されるルミネッセン
ス光を分光測定することにより能動層の特性を評価し、
波長1.3μmの発光のピーク強度が十分に小さく、かつ、
波長0.835μmの発光がほとんど現われない条件でアニー
ルを行うことによって達成することができる。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for forming an active layer by activating Si ions implanted on a GaAs crystal substrate by annealing to form an active layer. The characteristics of the active layer are evaluated by spectroscopically measuring the luminescence light emitted from
The peak intensity of the emission at a wavelength of 1.3 μm is sufficiently small, and
This can be achieved by performing annealing under the condition that light emission of a wavelength of 0.835 μm hardly appears.

【0007】[0007]

【作用】まず、Si イオン注入とアニールとにより形成
した能動層の評価方法について説明する。図2は評価に
使用する光学測定装置の概略構成を示す構成図で、レー
ザ光源1から励起光2を試料室3に保持した試料に照射
し、試料から放射されるルミネッセンス光4を分光器5
によって分光し、その強度を検知器6によって測定する
ものである。測定の際、試料は液体ヘリウムによって4.
2Kに冷却する。測定試料が Si 注入 GaAs の場合、図
3に示すように、波長域0.8〜2.4μmの範囲に四つの主
要な発光が観測される。このうち、発光(A)はバンド間
発光、発光(B)は As 格子位置を占める炭素の関与した
発光で、この二つの発光はイオン注入のない GaAs 基板
においても観測されることから、能動層の評価に使用す
ることは難しい。一方、0.835μmの発光(C)はAs 格子位
置を置換した Si の関与する発光で、この発光が強いほ
どアクセプター濃度の高いことを示す。また、1.3μmの
発光(D)は Ga 空孔に関与した発光で、Si が Ga 格子位
置を占めることにより減少する。すなわち、ドナーの生
成とともに減少する。従って、1.3μm発光強度が十分小
さく、かつ、0.835μm発光がまだ現われないアニール条
件の下でアニールを行うことによってキャリア濃度すな
わち活性化率を最大とすることができる。
First, a method of evaluating an active layer formed by Si ion implantation and annealing will be described. FIG. 2 is a configuration diagram showing a schematic configuration of an optical measuring device used for evaluation. A laser light source 1 irradiates a sample held in a sample chamber 3 with excitation light 2 and emits luminescence light 4 emitted from the sample into a spectroscope 5.
And the intensity is measured by the detector 6. During the measurement, the sample was filled with liquid helium.
Cool to 2K. When the sample to be measured is Si-implanted GaAs, as shown in FIG. 3, four main luminescences are observed in a wavelength range of 0.8 to 2.4 μm. Of these, emission (A) is inter-band emission and emission (B) is emission involving carbon occupying the As lattice position.These two emissions are also observed on a GaAs substrate without ion implantation. Difficult to use for evaluation. On the other hand, emission (C) at 0.835 μm is emission involving Si in which the As lattice position has been substituted, and the stronger the emission, the higher the acceptor concentration. The 1.3 μm emission (D) is emission associated with Ga vacancies, and is reduced by Si occupying the Ga lattice position. That is, it decreases with generation of the donor. Therefore, the carrier concentration, that is, the activation rate can be maximized by performing annealing under the annealing condition in which the emission intensity of 1.3 μm is sufficiently small and emission of 0.835 μm does not yet appear.

【0008】[0008]

【実施例】厚い能動層の試料について、C‐V測定から得
られたキャリア濃度と、1.3μm及び0.835μmにおける発
光強度との関係を調べた結果を図1に示す。ここで、ア
ニール条件としてはアニール時間を一定(0.1秒)とし
た。
EXAMPLE FIG. 1 shows the result of examining the relationship between the carrier concentration obtained from the CV measurement and the emission intensity at 1.3 μm and 0.835 μm for a thick active layer sample. Here, the annealing time was constant (0.1 seconds) as the annealing condition.

【0009】図1の結果から下記のことがわかる。すな
わち、低温領域(925℃以下)では、1.3μmの発光強度の
減少とともにキャリア濃度は増大している。一方、高温
領域(925℃以上)では、1.3μmの発光強度は十分小さく
なっているが、0.835μm発光強度の増大とともにキャリ
ア濃度は減少している。このことから、1.3μm発光強度
が十分小さく、かつ、0.835μm発光がまだ現われないア
ニール温度(925℃)でアニールを行うことによって高活
性化率を実現できることがわかる。
The following can be seen from the results of FIG. That is, in the low temperature region (925 ° C. or lower), the carrier concentration increases as the emission intensity of 1.3 μm decreases. On the other hand, in the high-temperature region (925 ° C. or higher), the emission intensity at 1.3 μm is sufficiently small, but the carrier concentration decreases as the emission intensity at 0.835 μm increases. From this, it is understood that a high activation rate can be realized by performing annealing at an annealing temperature (925 ° C.) at which the emission intensity of 1.3 μm is sufficiently low and emission of 0.835 μm does not yet appear.

【0010】なお、アニール温度を一定とした場合に
は、上記と同様にして、発光特性からアニール最適時間
を求めることができ、その条件でアニールすることによ
って高活性化率を得ることができる。
When the annealing temperature is fixed, the optimum annealing time can be obtained from the light emission characteristics in the same manner as described above, and a high activation rate can be obtained by annealing under the conditions.

【0011】[0011]

【発明の効果】以上述べてきたように、GaAs 半導体能
動層形成方法を本発明構成の方法とすることによって、
従来技術の有していた課題を解決して、最適条件で熱処
理を行うことにより高キャリア濃度でかつ厚さの薄い能
動層を形成する方法を提供することができた。また、こ
の能動層形成方法を FET 製造に適用することによっ
て、FET の大幅な特性向上を得ることができる。
As described above, by forming the GaAs semiconductor active layer forming method according to the present invention,
It has been possible to provide a method for forming an active layer having a high carrier concentration and a small thickness by performing a heat treatment under optimal conditions by solving the problems of the prior art. Applying this method of active layer formation to FET fabrication can also result in significant FET performance improvements.

【図面の簡単な説明】[Brief description of the drawings]

【図1】キャリア濃度、0.835μm発光強度、1.3μm発光
強度のアニール温度依存性を示す図。
FIG. 1 is a diagram showing annealing temperature dependence of carrier concentration, 0.835 μm emission intensity, and 1.3 μm emission intensity.

【図2】能動層の評価に用いた光学測定装置の概略構成
を示す構成図。
FIG. 2 is a configuration diagram showing a schematic configuration of an optical measurement device used for evaluating an active layer.

【図3】液体ヘリウム温度(4.2K)下で測定した Si 注
入 GaAs の代表的なルミネッセンススペクトル。
FIG. 3 is a typical luminescence spectrum of Si-implanted GaAs measured at a liquid helium temperature (4.2 K).

【符号の説明】[Explanation of symbols]

1…レーザー光源、2…励起光、3…試料室、4…ルミ
ネッセンス光、5…分光器、6…検知器。
DESCRIPTION OF SYMBOLS 1 ... Laser light source, 2 ... Excitation light, 3 ... Sample chamber, 4 ... Luminescence light, 5 ... Spectroscope, 6 ... Detector.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−16726(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/265 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-16726 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/265

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】GaAs 結晶基板上に注入した Si イオンを
熱処理することにより活性化させて能動層を形成する方
法において、所定波長領域の光を照射して能動層から放
射されるルミネッセンス光を分光測定することにより能
動層の特性を評価し、波長1.3μmの発光のピーク強度が
十分に小さく、かつ、波長0.835μmの発光がほとんど現
われない条件で熱処理することを特徴とする GaAs 半導
体能動層形成方法。
A method for forming an active layer by activating Si ions implanted on a GaAs crystal substrate by heat treatment to form an active layer, wherein the luminescent light emitted from the active layer is dispersed by irradiating light in a predetermined wavelength region. GaAs semiconductor active layer formation characterized by evaluating the characteristics of the active layer by measuring, and performing heat treatment under the condition that the peak intensity of the emission at 1.3 μm is sufficiently small and the emission at 0.835 μm hardly appears. Method.
JP03193949A 1991-08-02 1991-08-02 Method of forming GaAs semiconductor active layer Expired - Fee Related JP3086014B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03193949A JP3086014B2 (en) 1991-08-02 1991-08-02 Method of forming GaAs semiconductor active layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03193949A JP3086014B2 (en) 1991-08-02 1991-08-02 Method of forming GaAs semiconductor active layer

Publications (2)

Publication Number Publication Date
JPH0536616A JPH0536616A (en) 1993-02-12
JP3086014B2 true JP3086014B2 (en) 2000-09-11

Family

ID=16316441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03193949A Expired - Fee Related JP3086014B2 (en) 1991-08-02 1991-08-02 Method of forming GaAs semiconductor active layer

Country Status (1)

Country Link
JP (1) JP3086014B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7216387B2 (en) * 2018-01-09 2023-02-01 学校法人立命館 METHOD AND APPARATUS FOR MANUFACTURING CURRENT CONFIDENTIAL HIGH POWER VERTICAL HETEROJUNCTION FET

Also Published As

Publication number Publication date
JPH0536616A (en) 1993-02-12

Similar Documents

Publication Publication Date Title
Yacobi et al. Cathodoluminescence scanning electron microscopy of semiconductors
US4743569A (en) Two step rapid thermal anneal of implanted compound semiconductor
US5581194A (en) Method and apparatus for passive optical characterization of semiconductor substrates subjected to high energy (MEV) ion implantation using high-injection surface photovoltage
DE69323884T2 (en) Solid state electroluminescent device and process for its manufacture
Assimos et al. The photoelectric threshold, work function, and surface barrier potential of single‐crystal cuprous oxide
JP2005538561A (en) Method for improving the photoconductive properties of a semiconductor and method for manufacturing a semiconductor having improved photoconductive properties
Spitzer et al. Electrical and optical properties of proton‐bombarded gallium phosphide
Vesaghi Electrical properties of neutron-transmutation-doped GaAs below 450 K
Ku et al. Injection Electroluminescence in (Al x Ga1− x) As Diodes of Graded Energy Gap
Singh et al. Effect of beam energy and anneal history on trivalently bonded silicon defect centers induced by ion beam etching
Matsuda et al. Electroluminescence of MOS capacitors with Si-implanted SiO2
JP3086014B2 (en) Method of forming GaAs semiconductor active layer
Mantovani et al. Thermal diffusion of Pt in silicon from PtSi
Iwai et al. Emission spectra in CdS under high excitation by electron beam
Hwang Effect of Heat Treatment with Excess Arsenic Pressure on Photoluminescence of p‐Type GaAs
Lee et al. Measurement time reduction for generation lifetimes
Elsaesser et al. Er‐related deep centers in GaAs doped with Er by ion implantation and molecular beam epitaxy
Kalyadin et al. Silicon light-emitting diodes with luminescence from (113) defects
Sharma et al. Determination of minority‐carrier diffusion length in ap‐silicon wafer by photocurrent generation method
Chambouleyron et al. Photovoltaic effect in lead selenide p‐n junctions
JPH0982768A (en) Semiconductor wafer evaluation method
Liu et al. Hydrogen redistribution induced by negative-bias-temperature stress in metal–oxide–silicon diodes
Kamigaki et al. Two signals in electrically detected magnetic resonance of platinum-doped silicon p–n junctions
Sobolev et al. Light-emitting Si: Er: O diodes operating in the avalanche regime
Murel et al. Capacitance spectroscopy of hole traps in high-resistance gallium-arsenide structures grown by liquid-phase epitaxy

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070707

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080707

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080707

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090707

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees