JP3086500B2 - Field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a field effect transistor (hereinafter, referred to as FET).

[0002]

2. Description of the Related Art Generally, there are two types of FETs: a .pi. Type having a single gate electrode and a comb type having a plurality of gate electrodes. FIG. 10 shows a top view of the FET, and shows an example of a comb-shaped gate electrode. This FET is configured by providing a source electrode 53, a drain electrode 52, and a gate electrode 51 on a substrate.

In this conventional FET, the shape of the gate electrode 51 is exactly the same regardless of the cross section of any part regardless of the π-shaped or comb-shaped electrode structure. It may be considered that an FET is configured.

[0004]

By the way, this FET
Considering the high frequency characteristics of, for example, GaAs MESFE
At T, at 12 GHz, | S ₁₁ |
And | S ₂₂ | is usually 0.5 or more, and the absolute value does not largely change even if the phase changes even if the gate length or gate width is changed. Therefore, in order to make an amplifier using this FET, a matching circuit must be provided inside or outside the FET chip, and the input and output impedance must be 50Ω.

Therefore, when an amplifier is made with only one FET, there are the following problems.

[0006] If no matching circuit, the input and output is 50 [Omega, is it is extremely difficult to make a FET, is constrained to a value which can be taken in the S ₁₁ and S ₂₂ is about changing the gate length and gate width is there.

When a matching circuit is provided, it is possible to make the input and output 50Ω.
There is a problem that a place for providing a matching circuit is required, and thus the chip size is increased.

[0008] The reason for this is that, since the gate shape of the FET is exactly the same in each part, only a circuit that operates equivalently in one type can be considered.

On the other hand, a low noise MMIC using the above FET
When fabricating, Ganmaopt and S ₁₁ Togazu 11 are so far apart as the point A, the input VSWR deteriorates the matching directly Ganmaopt.

In order to solve this problem, in a conventional MMIC, a thin strip line 56 having an inductance (L) component is formed from a source electrode 53 as shown in FIG. Source electrode 53
The L component (Ls) is provided between the ground and the ground. This L
When was 0.1~0.3nH the s, because Γopt and S ₁₁ is approaching as B~D point, very VSWR matching to Γopt is not too bad. In FIG. 12, a region 54 indicated by a broken line is a mesa portion.

However, as shown in FIG. 12, when Ls is formed by the strip line 56, only that portion is occupied and the MMIC chip area is increased. Since the area of the bonding pad 57 is also required, it is easily expected that the chip area will be further increased. For example, if the conventional chip size is 200 × 100 μm
Then, the size of the strip line 56 for inserting Ls of 0.1 to 0.3 nH and the increase of the chip area are as shown in Table 1.

[0012]

[Table 1]

SUMMARY OF THE INVENTION An object of the present invention is to provide an FET which has a small chip size and can easily cope with various uses.

[0014]

According to a first aspect of the present invention, there is provided a field effect transistor having a source electrode, a drain electrode and a gate electrode provided on a substrate, wherein the gate electrode is constituted by a plurality of gate portions having different shapes. And these gate portions are connected in parallel.

According to a second aspect of the present invention, in a field effect transistor having a source electrode, a drain electrode and a gate electrode provided on a substrate, the source electrode or the impurity region layer under the source electrode is formed in a comb shape. And a source inductance component.

[0016]

According to the first aspect of the invention, the gate electrode shape on one FET chip is divided into a plurality of types instead of one type, and these are arranged in parallel. Things are made. For example, in the case of a comb-shaped FET, there are usually about four gate electrodes, which are divided into two, and the electrodes having different gate lengths and gate widths are different from each other. However, if the entire gate is integrated, the characteristics will be different from those of the related art. By properly adjusting the shape of each gate, S ₁₁ and S
₂₂ can be set to 50Ω.

Therefore, by forming two types of gate shapes on one FET chip, it becomes possible to make an FET having an input and output of 50Ω without a matching circuit, and by changing the gate length and gate width, possible values of S ₁₁ and S ₂₂ spreads larger than conventional.

Further, since there is no matching circuit, even when an amplifier is manufactured, the chip size does not change and there is an effect that the size can be significantly reduced as compared with the conventional one. Incidentally, S ₁₁ and possible values of S ₂₂ is further spread by forming three or more kinds of gate-shaped on one FET chip, the FET becomes 50Ω without increasing the gate width can be realized.

According to the second aspect of the present invention, when Ls is inserted into the equivalent circuit, the area of the bonding pad is not necessary, so that the chip area does not increase and is almost the same as the conventional FET. It exerts a sufficiently large effect.

[0020]

FIG. 1 is a top view showing a surface pattern of an FET showing an embodiment according to the first invention of the present invention.

As shown in FIG. 1, the FET of the present invention has a gate electrode 51, a source electrode 53,
It is constituted by a drain electrode 52.

The gate electrode 51 has a comb shape. In this embodiment, four gate portions 51a, 51a, 51b, 5
1b. In the present invention, this is divided into two lines and the gate width is changed. For example, if the length of the upper two gate portions 51a, 51a is a, and the length of the lower two gate portions 51b, 51b is b, the gate width of this FET is 2a, 2b. The structure has existed on one chip.

The gate length can also be changed between the upper and lower gate portions. By changing the offset amount of the position of the gate electrode, the source resistance and the drain resistance can be changed. In addition, the same gate length,
By changing the gate shape also in the gate width, the capacitance between the source and the gate can be changed.

In order to form the above gate electrode,
It can be easily realized by performing exposure using an electron beam.

Next, two types of FEs will be described as an embodiment of the present invention.
Consider the characteristics of T. As shown in FIG. 2, the equivalent circuit of the FET has the same circuit regardless of the shape, regardless of the constant.

In FIG. 2, 1 is a gate resistance, 2 is a gate inductance, 3 is a gate-drain capacitance, and 4 is a source-gate capacitance. 5 is a channel resistance, 6 is a source-gate conductance, 7 is a drain inductance, 8 is a drain resistance, 9 is a constant current source represented by a mutual conductance and a time constant, 10 is a drain conductance, and 11 is a source-drain. Capacity, 1
Reference numeral 2 denotes a source resistance.

From the equivalent circuit shown in FIG. 2, the S parameter at a high frequency can be easily calculated. Gate section 51a
The S parameter for the gate width of Sa is Sa, and the gate section 51b
Assuming that the gate width of Sb is Sb, as shown in FIG. 3, this FET can be regarded as a circuit in which the S parameter Sa (13) and the S parameter Sb (14) are combined in parallel. Can be replaced with one combined S parameter Total. And
Total elements S ₁₁ total and S ₂₂ to
By setting Sa and Sb so that tal becomes 50Ω, in other words, by setting the gate length, gate width and gate shape, a self-aligned FET can be obtained.

Next, the result of a simulation for determining equivalent circuit constants for Sa and Sb so that S ₁₁ total and S ₂₂ total become 50Ω will be specifically described.

As a premise for performing the simulation, the gate width of the gate portion 51a of the FET with respect to Sa is short. On the other hand, the gate width of the gate portion 51b of the FET with respect to Sb is long. Therefore, it is assumed that a <b. Since the electrodes on the FET chip are the same for the gate inductance 2 and the drain inductance 7 in FIG. 2, these values are assumed to be the same.

The gate resistance 1, drain resistance 8, source resistance 12, gate-source capacitance 4, constant current source 9, drain conductance 10, channel resistance 5, and gate-drain capacitance 3 are gate width, gate length, and gate shape. Because there are a wide range of characteristics depending on the differences, no conditions were set here.

As a result, Sa becomes (S ₁₁ a = 0.7 <−1)
35 °, S ₂₁ a = 3.73 <54 °, S ₁₂ a = 0.22
<10 °, S ₂₂ a = 0.19 <172 °), and Sb
Is (S ₁₁ b = 0.6 <127 °, S ₂₁ b = 1.31 <1
4 °, S ₁₂ b = 0.14 <44 °, S ₂₂ b = 0.73 <
96 ゜), input (S ₁₁ Total) of Total
l) and output (S ₂₂ total) were as follows.

S ₁₁ total = 0.05 <69 ゜ S ₂₂ total = 0.04 <156 ゜

Thus, both are almost close to 0,
That is, the impedance was close to 50Ω.

FIG. 4 shows S-parameter characteristics on the Smith chart. In this figure, 20 is a position which is a 50Ω impedance, 21 denotes an S ₁₁ a, 22 is S ₁₁ b, 23 is S ₁₁ total, 24 is S ₂₂ a, 25 is S ₂₂ b, 26 is S ₂₂ total .

The equivalent circuit constants of the Sa and Sb FETs are as follows. The equivalent circuit constants for the FETs having the gate widths of the gate portions 51a, 51a are as follows. The gate resistance 1 is 3.2Ω, the gate inductance 2 is 0.25 nH, and the gate-drain capacitance 3 is 0.0
4PF, source-gate capacitance 4 is 0.24PF, channel resistance 5 is 10.2Ω, source-gate conductance 6 is 0, drain inductance 7 is 9.4mS,
The drain resistance 8 is 3.0Ω, and the transconductance and the time constant of the constant current source 9 are 121 mS and 13.8pese, respectively.
c, the drain conductance 10 is 0.30 nH, the source-drain capacitance 11 is 0, and the source resistance 12 is 9.9.
Ω.

FE of the gate width of the gate portions 51b, 51b
The equivalent circuit constants for T are as follows. The gate resistance 1 is 7.6Ω and the gate inductance 2 is 0.25
nH, the gate-drain capacitance 3 is 0.31 PF, the source-gate capacitance 4 is 0.94 PF, the channel resistance 5 is 10.5Ω, the source-gate conductance 6 is 0,
The drain inductance 7 is 14.7 mS, the drain resistance 8 is 3.0Ω, the mutual conductance and the time constant of the constant current source 9 are 237 mS and 20.9 pesec, respectively, the drain conductance 10 is 0.30 nH, and the source-drain capacitance 11 is 0 and the source resistance 12 is 0.5Ω.

From this equivalent circuit constant, the gate length, gate width and gate shape can be estimated as follows.
And it became possible to make it very small.

The FET of the gate section 51a has a gate length of 0.1.
A recess is dug deep with 2 μm and a gate width of 200 μm, and is placed at the center of the source / drain.

The FET of the gate section 51b has a gate length of 0.1.
The recess may be shallowly dug with a thickness of 7 μm and a gate width of 500 μm, the gate metal film thickness may be reduced, and a considerable offset may be applied to the drain side. .

As described above, by forming two types of gate shapes on one FET chip, it becomes possible to make an FET having an input and output of 50Ω without a matching circuit, and to change the gate length and gate width. by, S ₁₁ and S ₂₂
The value that can be taken is larger than before.

Further, since there is no matching circuit, even when an amplifier is made, the chip size does not change, and a significant reduction in size can be realized as compared with the conventional one. There is an effect. In addition, 1
One of the possible values of that at S ₁₁ and S ₂₂ that form three or more kinds of gate-shaped on the FET chip further spread the FET becomes 50Ω without increasing the gate width can be realized.

Next, a second embodiment of the present invention will be described with reference to FIGS.

First, the S parameter of the FET is set to 1-26G.
It was measured on-wafer in the frequency range of Hz. This FET has a gate length of 0.25 μm and a gate width of 20 μm.
0 μm, and the measurement conditions were as follows: Ids = 10 mA, Vds
= 2V. Next, a simulation was performed based on the measured S parameters. The results are shown below. Ls = 0 S11 = 0.807 <118 ° Γopt
= 0.639 <83 ° Ls = 0.1 S11 = 0.595 <120 ° Γopt
= 0.593 <88 ° Ls = 0.2 S11 = 0.430 <114 ° Γopt
= 0.542 <94 ° Ls = 0.3 S11 = 0.323 <101 ° Γopt
= 0.489 <101 ° That is, as Ls increases, the distance between S11 and Γopt decreases.

As described above, since the distance between S ₁₁ and Δopt is reduced in accordance with the source inductance, the present invention includes a source inductance component in the equivalent circuit of the FET so that the Δopt position is brought into a gain matching state. It was made.

FIGS. 5 and 6 show the first embodiment of the second invention.
It will be described according to the following. FIG. 5 is a top view, and FIG. 6 is BB ′ of FIG.
It is a line sectional view.

As shown in FIGS. 5 and 6, in this embodiment, the source electrode 53 is a comb type. The ohmic junction between the source region and the n ++ type region is formed at the comb-shaped portion. In this figure, 52 is a drain electrode, 51 is a gate electrode, 54 is a mesa portion, and 55 is a semiconductor substrate.

As described above, when the ohmic junction is formed in a comb-shaped portion, since the thin metal is collected, the portion has an L component. Since the value of L can be adjusted by the number of metals, a considerably wide range of Ls can be formed even if the length is reduced.

The value of the L component of a thin metal is given by the following equation. L = 0.2 * l (ln (2 * l / (w + t)) + 0.5
+ (W + t) / 3 / l) where L is inductance (nH), l is length (mm) of metal, w is width (mm),
t is the thickness (mm).

From this equation, the size of the metal forming Ls of 0.1 to 0.3 nH is as follows. In consideration of the thickness of the ohmic electrode, t = 0.2 μm, W = 0.5
μm was fixed. Ls = 0.1 nH 1 = 84 μm Ls = 0.2 nH 1 = 152 μm Ls = 0.3 nH 1 = 217 μm

Therefore, since the length of the source electrode 53 is increased by the above value, the size of the source electrode 53 is about half the size of the conventional pattern having the same Ls. When w and t are reduced, the length l of the metal can be further reduced.

By the way, the above-mentioned length is the case when the metal is straightened, and there is no problem in actually forming the metal by bending. Therefore, even when Ls = 0.3 nH, it is possible to considerably reduce the size by forming the pattern as shown in FIG. 7, and the chip size in this case is Ls = 0.3 nH.
It turns out that it is hardly different from the case of 0. In addition, since the bonding pad can be formed directly on the source electrode 53, it is not necessary to form another bonding pad as in the related art, and the MMIC can be downsized by this function.

FIGS. 8 and 9 show a second embodiment of the second invention.
It will be described according to the following. 8 is a top view, and FIG. 9 is AA ′ of FIG.
It is a line sectional view.

In the second embodiment, the shape of the mesa 54 is a comb shape as shown in FIG. That is, an L component is provided by thinning the operation layer. In this case, since it can be considered exactly in the same manner as in the above-described example, the size can be reduced.
The present invention is also applicable to a case where an ion implantation method or the like that does not form a mesa is used.

[0053]

According to the first invention, by forming a plurality of types of gate shapes on one FET chip,
Input and output without matching circuit becomes possible to make the FET to be 50 [Omega, by changing the gate length and gate width, the possible values of S ₁₁ and S ₂₂ spreads larger than conventional.

Further, since there is no matching circuit, even when an amplifier is manufactured, the chip size does not change, and a significant reduction in size can be realized as compared with the conventional one. There is an effect. In addition, 1
One of the possible values of that at S ₁₁ and S ₂₂ that form three or more kinds of gate-shaped on the FET chip further spread the FET becomes 50Ω without increasing the gate width can be realized.

[0055]

[Brief description of the drawings]

FIG. 1 is a top view showing a surface pattern of an FET of the first invention.

FIG. 2 is an equivalent circuit diagram of the FET.

FIG. 3 is a conceptual diagram in which parallel S parameters are replaced with one S parameter;

FIG. 4 is a diagram showing, on a Smith chart, input and output impedances of respective FETs obtained in the embodiment of the first invention.

FIG. 5 is a top view showing the first embodiment of the second invention.

6 is a sectional view taken along line B-B 'of FIG.

FIG. 7 is a top view showing another embodiment of the second invention.

FIG. 8 is a top view showing a second embodiment of the second invention.

9 is a sectional view taken along line A-A 'of FIG.

FIG. 10 is a top view showing a surface pattern of a conventional FET.

FIG. 11 is a diagram showing input and output impedances of a FET on a Smith chart.

FIG. 12 is a top view showing a surface pattern of a conventional MMIC.

[Explanation of symbols]

 51 gate electrode 51a gate part 51b gate part 52 drain electrode 53 source electrode

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/812 H01L 29/40-29/43 H01L 29/47

Claims (1)

(57) [Claims] In a field-effect transistor having a source electrode, a drain electrode and a gate electrode provided on a substrate, the gate electrode is constituted by a plurality of gate portions having different gate widths and gate lengths , and these gate portions are formed. A field-effect transistor characterized by being connected in parallel.