JP3087296B2 - Microwave semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave integrated circuit, and more particularly to a small semiconductor device having excellent high frequency characteristics.

[Conventional technology]

Conventionally, this type of microwave integrated circuit is configured by cascade-connecting a large number of IC chips and mounting them in one package. In order to obtain the best high-frequency characteristics, a method of adjusting the resistance outside the package has been adopted as a means for optimally selecting a bias voltage to a semiconductor element.

[Problems to be solved by the invention]

In order to connect each semiconductor element to an external resistor, in the case of a multi-stage element, a number of connection lead terminals must be provided in the package. Although the shape of an IC chip has become extremely small due to monolithicization, there is a drawback that the size of the entire device is not so advanced because the shape of the package is limited by the number of connection lead terminals.

FIG. 5 shows a conventional semiconductor device for a microwave integrated circuit. 2A to 2F are IC chips, and will be described using an FET as an element. The package 1 is provided with connection lead terminals 5A to 5F for applying a gate bias and connection lead terminals 6A to 6F for applying a drain bias from each chip. Since the shape of the package is limited by the physical spacing between these lead terminals, there is a limit to miniaturization in a structure that requires several lead terminals.

An object of the present invention is to provide a small-sized semiconductor device for a microwave integrated circuit, in which the number of connection lead terminals from a package to an external power supply is reduced.

[Means for solving the problem]

A microwave semiconductor device according to the present invention is a microwave semiconductor device in which a plurality of IC chips are mounted in one package, wherein a plurality of thin films having one electrode commonly connected on the same substrate are provided in the package. A bias resistor circuit board including a resistor and a chip capacitor is mounted such that one bias resistor circuit board is assigned to at least two or more IC chips, and is assigned to each bias voltage supply point of each IC chip. One of the plurality of thin film resistors on the bias resistor circuit board, and connected to the other electrode of the selected thin film resistor, and one of the plurality of thin film resistors on the bias resistor circuit board. A connection point where the electrodes are commonly connected is electrically connected to one bias lead terminal penetrating the side wall of the package. That.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a package mounting diagram showing one embodiment of the present invention.

1 is a package, 2A to 2F are IC chips, 3A to 3C are gate bias resistance circuit boards, 5 is a gate lead terminal, and 6 is a drain lead terminal. Since the wiring from each bias resistance circuit is collected in four lead terminals, the package can be reduced in size.

FIG. 2 shows an enlarged view of the two IC chips and the bias resistor circuit. Thick lines indicate ground wiring. The parameters of the semiconductor element have manufacturing variations, and it is necessary to optimally adjust the bias voltage applied to each FET in order to obtain the best high-frequency characteristics. FIG. 3 shows an example of the FET bias circuit. R _G1 , R _G2, R _D, etc. are selected from the four thin film resistors in the bias resistance circuit board shown in FIG. ₂ and wired by bonding. Providing bias capacitors 7, 8 (chip capacitors) and the like on the bias resistor circuit board is effective in preventing abnormal oscillation.

By manufacturing the bias resistance circuit on a substrate different from the IC chip, the bias resistance can be adjusted and the size of the package can be reduced.

A procedure for mounting the present invention on a package will be briefly described.
First, a bias capacitor (chip capacitor) is mounted on a bias resistor circuit board on which a plurality of thin film resistors are formed, and this board and an IC chip are simultaneously mounted in a package. After this, the wiring between the bias resistor circuit boards and
Perform bonding wiring work between IC chip and bias resistor circuit, and between bias resistor circuit and lead terminal. When selecting a bias resistor, the optimum bias resistor is determined in advance by evaluating the high-frequency characteristics of each IC chip using a high-frequency measurement jig or the like. If several types of bias resistance circuit boards are prepared and freely replaced so that the resistance value can be arbitrarily selected, the degree of freedom is further increased.

When the number of IC chips is further increased, a plurality of blocks each composed of an IC chip, a bias resistor circuit board and lead terminals may be provided as shown in FIG.

In this way, even in a multi-stage IC structure of eight or ten stages, the number of lead terminals required on the side wall of the package is about four to six, and the purpose of a small package is sufficiently achieved.

〔The invention's effect〕

As described above, the present invention has an effect that the package can be miniaturized by housing the bias resistance circuit board including the plurality of resistors and the bypass capacitors in the package. As a result, when this package is used for a receiver, a transmitter, or the like, an external bias resistor is not required, and the entire device can be reduced in size and electrical adjustment can be simplified. is there.

[Brief description of the drawings]

FIG. 1 is a package mounting diagram showing an embodiment of the present invention, FIG. 2 is an enlarged mounting diagram of a bias resistor circuit portion of FIG. 1,
FIG. 3 is a bias circuit diagram, FIG. 4 is a package mounting diagram showing a modification of one embodiment, and FIG. 5 is a structural diagram of a conventional semiconductor device. 1. Package, 2A to 2J IC chip, 3A to 3E Gate bias resistor circuit, 5, 5A to 5F Gate lead terminal, 6, 6A to 6F Drain lead terminal, 7, 8, 9A ~ 9F, 10A
~ 10F: bypass capacitor, RF IN: input terminal, R
F OUT …… Output terminal.

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 23/12 301 H01L 25/00

Claims (1)

(57) [Claims] 1. A microwave semiconductor device in which a plurality of IC chips are mounted in one package, wherein a plurality of thin film resistors and a chip capacitor in which one electrode is commonly connected on the same substrate in the package. A bias resistor circuit board comprising: a bias resistor circuit board mounted such that one bias resistor circuit board is assigned to at least two or more IC chips; and a bias resistor circuit assigned to each bias voltage supply point of each IC chip. Any one of the plurality of thin film resistors on the substrate is selected and connected to the other electrode of the selected thin film resistor, and one electrode of the plurality of thin film resistors on the bias resistor circuit board is commonly connected. Wherein the connection point is electrically connected to a bias lead terminal penetrating the side wall of the package.