JP3087336B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device such as a semiconductor pressure sensor or a semiconductor acceleration sensor having a strain-generating film and a strain gauge thereon.

[0002]

2. Description of the Related Art An example of a conventional semiconductor pressure sensor is shown in FIG.
Shown in This sensor comprises a first substrate 1a bonded to each other.
And a second substrate 2a, the first substrate 1a and the second substrate 2
a has a pressure chamber 11a and a pressure introduction hole 21 communicating with each other.
a is formed. The pressure chamber 1 is provided on the surface of the first substrate 1.
An oxide film 4a is formed including the surface of 1a. Then, a strain generating film 5a made of a silicon nitride film is formed on the first substrate 1 to cover the pressure chamber 11a, and a strain gauge 32 is formed on the strain generating film 5a.

A part of the process of this semiconductor pressure sensor is shown in FIG.
The method will be described with reference to FIG. 3. After joining the first and second substrates 1a and 2a, the concave portion 11a is dug in the first substrate 1a by etching, and after the polysilicon 9a is deposited, polishing is performed until the oxide film 4a is exposed. Next, the polysilicon 9a is removed through the opening of the intermediate insulating film 3a by anisotropic etching from the second substrate side 2a to form the pressure chamber 11a and the pressure introducing hole 21a. Therefore, for the above polishing, the oxide film 4a
Is formed somewhat thicker.

[0004]

In recent years, it has been proposed to integrate a circuit such as a CMOS on the same chip as a semiconductor pressure sensor in order to improve the characteristics of the semiconductor pressure sensor. In this case, it is necessary to expose the surface of the first substrate 1 to form a circuit. For example, as shown in FIG. 24, after patterning an oxide film 4a in advance, a silicon nitride film 5a for strain generation is formed. Then, the silicon nitride film 5a is patterned to expose the surface of the first substrate 1, and a CMOS can be formed thereon.

[0007] As shown in FIG. 25, after an oxide film 4 a and a silicon nitride film 5 a for strain generation are sequentially deposited, the silicon nitride film 5 a and the oxide film 4 a are sequentially patterned to expose the first substrate 1. You can also. However, whichever of the above-described methods is employed, a non-negligible level difference is generated immediately below the end of the silicon nitride film 5a, and the wiring layer formed thereon is easily cut.

In the method of FIG. 25, the silicon nitride film 5
Undercut is likely to occur immediately below the periphery of "a", and further, disconnection of the wiring and remaining of the resist are likely to occur. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device in which wiring steps are not easily cut off in the periphery of a cavity.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate having a cavity, a protective insulating film having a predetermined thickness formed on the semiconductor substrate surface and the cavity surface around the cavity, and formed on the protective insulating film around the cavity and extending over the cavity; A strain-generating film, and a strain gage formed on the strain-generating film, wherein the surface is formed adjacent to the periphery of the protective insulating film and has a surface flush with the surface of the protective insulating film. Wherein the strain-generating film extends over the semiconductor region.

Here, the strain generating film can be made of an insulating film such as a silicon nitride film, a semiconductor such as silicon, or a metal. A semiconductor region having a different etching characteristic from that of the strain-generating film is selected. The semiconductor device to which the present invention is directed includes all semiconductor devices having a strain-generating film formed by etching and a strain gauge disposed thereon, such as a semiconductor pressure sensor, a semiconductor acceleration sensor, and a semiconductor humidity sensor. .

[0009]

According to the present invention, a semiconductor region having a surface flush with the surface of the protective insulating film is formed adjacent to the periphery of the protective insulating film. Wiring breakage can be prevented. Further, since the strain-generating film covers the surface of the protective insulating film on the surface of the semiconductor substrate around the cavity, and furthermore, the semiconductor region covers the side surface of the protective insulating film. The undercut of the protective insulating film immediately below the periphery of the strain film prevents the above-mentioned disconnection of the wiring from becoming more serious.

Therefore, according to the present invention, since a semiconductor region having a surface flush with the surface of the protective insulating film is formed adjacent to the periphery of the protective insulating film, a high yield is achieved in this type of semiconductor device. Can be realized.

[0011]

【Example】

Embodiment 1 FIGS. 1 to 5 show an example of a semiconductor pressure sensor as an embodiment of the semiconductor device of the present invention. here,
FIG. 1 is a cross-sectional view of the semiconductor pressure sensor, FIG. 2 is a rear plan view, and FIGS. 3 to 5 are cross-sectional views showing the manufacturing steps. FIG. 1 is a sectional view taken along line AA of FIG.

This semiconductor pressure sensor comprises a first substrate 1 and a second substrate 2 joined to each other with a silicon oxide film 3 interposed therebetween.
And a pressure chamber (cavity) 11 and a pressure introduction hole (cavity) 21 communicating with each other are formed in the first substrate 1 and the second substrate 2. Then, a protective insulating film 4 made of a silicon oxide film is formed on the surface of the first substrate 1 including the surface of the cavity 11, and the cavity 1 is formed on the protective insulating film 4.
1, a diaphragm film (strain-induced film) 5 made of a silicon nitride film is formed. An n ⁻ type epitaxial layer (semiconductor region) 6 is formed on the surface of the first substrate 1, and the epitaxial layer 6 is flush with the protective insulating film 4 by polishing. Extend over the epitaxial region 6. A strain gauge 7 made of doped polysilicon is formed on the diaphragm film 5, and an nMOS integrated circuit (only one transistor is shown in the figure) is formed on the surface of the first substrate 1. 8 are formed. Further, other configurations will be described with reference to the description of the manufacturing method of FIGS.

First, as shown in FIG. 3, the first substrate 1 and the second substrate 1
A bonded substrate prepared by bonding the substrate 2 and having a silicon oxide film 3 in the middle is prepared. In the bonded substrate of FIG.
The substrate 1 is a 10Ωcm (100) n-type silicon substrate, and the second substrate 2 is a 10Ωcm, 400 μm thick (1) silicon substrate.
10) Use an n-type silicon substrate. Then, a cavity 11 for a pressure chamber is formed in the first substrate 1 by anisotropic etching using a KOH aqueous solution using the silicon oxide film 3 as an etching stopper. The reason why such a bonded substrate is employed is that the silicon oxide film 3 is used as an etching stopper for the anisotropic etching, and a normal bulk substrate can be used.

Next, as shown in FIG.
A 1 μm thick oxide film (protective insulating film) 4 by thermal oxidation
The oxide film 4 is formed and opened all around the cavity 11.
I do. At this time, the silicon oxide film 3 is also opened at the same time.
You. Next, as shown in FIG.
To form The growth condition of the epitaxial layer 6 at this time is as follows.
Normal ones may be used, for example, SiCl _FourWhen
H_TwoAnd a growth temperature of 1000 to 1
270 ° C. During this epi growth, the oxide film 4 and the oxidized
Polysilicon layer 9 is formed on silicon film 3. This
Of the polysilicon thickness at the center of the cavity 11
Until the thickness is sufficient, that is, the cavity 11
It is carried out until it fills up. In this embodiment, silicon oxide is used.
The thickness of the silicon film 4 is 1 μm, the thickness of the first substrate 1 is 9 μm,
Is 1 μm thick, so 3 mm including the margin for selective polishing
An epi growth of 0 μm was performed.

Next, as shown in FIG. 6, the wafer surface is selectively polished, and the polishing is stopped when the oxide film 4 is exposed. Next, as shown in FIG. 7, a 2 μm-thick diaphragm film serving as a diaphragm of the pressure sensor, that is, a silicon nitride film 5 is deposited and patterned. This patterning is performed so that the silicon nitride film 5 extends over the epitaxial layer 6 by a distance 1 so as to cover the polysilicon layer 9 in the cavity 11 and the oxide film 4 therearound. This is to prevent an undercut due to repetition of an etching process such as a later transistor formation, and the prevention of the undercut does not cause a residue of the resist or a disconnection of the wiring layer.
In this embodiment, the distance 1 is set to 5 μm.

Next, as shown in FIG.
Then, gate oxide film 7 is formed using oxide film 4 as a mask. Next, as shown in FIG.
A thick polysilicon film is deposited and patterned to form a gate electrode 31 and a strain gauge 32,
By ion implantation, an n ⁺ type source and drain region 33,
34, a BPSG film 35 is deposited by the CVD method, and the BPSG film on the diaphragm film 5 is removed by patterning. At this time, the end of the diaphragm film 5 is
5 so as to cover a step between the diaphragm film 5 and the epitaxial layer 6 thereunder. Next, a 0.5 μm thick
A thick silicon nitride film 36 is deposited by CVD and patterned. Thereafter, the BPSG film 35 and the silicon nitride film 36 are opened, and a predetermined wiring is formed by the aluminum wiring 37.

Next, as shown in FIG. 10, an opening is formed in the silicon nitride film 38 formed on the surface of the second substrate 2, and thereafter,
As shown in FIG. 11, the second substrate 2 is anisotropically etched by alkali etching, and the polysilicon layer 9 is further etched to form a pressure chamber 11 and a pressure introducing hole 21 (cavity). Although KOH was used as an etching solution, other alkaline aqueous solutions such as NaOH, LiOH,
EPW, TMAH (tetraethyl ammonia aqueous solution) or the like may be used.

As shown in FIG. 2, the shape of the formed pressure introducing hole 21 is <1 with respect to the Si (110) plane of the second substrate 2.
When a rhombic pattern inclined by 54.7 ° in the 10> direction is used, a hole perpendicular to the Si (110) plane can be formed due to a difference in etching rate between the (111) plane and the (110) plane. That is, in the case of KOH, the ratio between the etching rate of the (111) plane and the etching rate of the (110) plane is several hundred times, so that the (111) plane is hardly etched, and the (111) plane is perpendicular to the (110) plane on the back surface. The (111) plane is formed along the side of the deformation, and the (110) plane on the back surface and 35.3
A (111) plane with an angle of ° appears (FIG. 2). In this way, a large number of pressure introducing holes (cavities) can be accumulated.

According to the above-described embodiment, the silicon layer of the first substrate 1 and the oxide film 4 are formed by forming the epitaxial layer 9.
And the undercut around the diaphragm film 5 due to the subsequent nMOS process (or cMOS or bipolar process) can be prevented. Note that if the above-described nMOS process is performed first to form a circuit and then a diaphragm film made of silicon nitride is formed, the above-described adverse effect of the undercut does not occur. A problem arises in that the polysilicon film 9 buried in the cavity 11 cannot be protected by the diaphragm film.
In this embodiment, the strain gauge 32 and the gate electrode 31
Has the advantage that it can be manufactured in the same step. (Embodiment 2) FIGS. 12 to 18 show a semiconductor pressure sensor according to another embodiment.

This sensor forms the oxide film (protective insulating film) of Example 1 and a thick insulating film for channel separation of a circuit portion by a LOCOS process.
The manufacturing process will be described. First, as shown in FIG. 12, a pressure chamber (cavity) 11 is formed in a bonding substrate in the same step as in FIG. 3 of the first embodiment.

Next, as shown in FIG. 13, an oxide film 51 having a thickness of 400 ° is formed on the surface of the first substrate 1 by a thermal oxidation method.
A silicon nitride film 52 for a mask is formed on the oxide film 51 and patterned. Next, as shown in FIG. 14, a 9500-thick LOCOS oxide film 53 is formed by oxidation,
The silicon nitride film 52 is removed and the oxide film 51 is removed to form a new gate oxide film 54 having a thickness of 400 °. At this time, the gate oxide film 54 is formed surrounding the cavity 11. Although not shown here, LOC
A channel stop is performed by implanting p-type impurities into the surface of the first substrate 1 under the OS oxide film 53 by ion implantation.

Next, as shown in FIG. 15, a polysilicon layer 9 is deposited to a thickness of about 30 μm and polished similarly to the first embodiment.
Thus, a polysilicon layer 91 is also formed on gate oxide film 54. Next, as shown in FIG.
Similarly, a silicon nitride film 5 serving as a diaphragm film is deposited and patterned. At this time, the peripheral portion of the diaphragm film 5 is overlapped with the polysilicon layer 91 on the gate oxide film 54 by a distance 1 (here, 5 μm). This is to prevent the oxide film (protective insulating film) 53 under the silicon nitride film 5 from being undercut by a subsequent etching process.

Next, as shown in FIG.
The polysilicon film 91 is patterned by the mask 60,
Ion implantation is performed from above the exposed gate oxide film 54.
T ⁺Mold source and drain regions 33 and 34 are self-aligned
It is formed by in. Thereafter, as shown in FIG.
A BPSG film 62 is deposited and patterned by VD method.
The BPSG film 62 on the diaphragm film 5 is removed. next,
Polysilicon serving as a strain gauge on the diaphragm film 5
The layer 63 is selectively formed to protect the polysilicon layer 63.
A 0.5 μm thick silicon nitride film 64 by CVD.
Deposited and patterned. Then, these BPSG films 6
2 and silicon nitride film 64 are opened to form aluminum wiring 61
More predetermined wiring is performed.

Thereafter, the pressure introducing hole 21 is formed from the step of FIG. 10 to the same step as in the first embodiment. This embodiment has an advantage that the step of forming the polysilicon film 91 immediately below the end of the diaphragm film 5 can be performed in the same steps as the step of forming the gate electrode and the step of embedding the polysilicon layer in the cavity 11.

(Embodiment 3) FIGS. 23 to 25 show a semiconductor pressure sensor according to another embodiment. This semiconductor pressure sensor uses single crystal silicon for the strain gauge, and its manufacturing process will be described below. First, the bonding substrate A shown in FIG. 19 is manufactured through the steps up to FIG. 6 in the first embodiment, and a third substrate B having a surface on which a nitrided oxide film 3a is formed is prepared (see FIG. 19). Here, a (110) n-type silicon substrate of 1 Ωcm to 10 Ωcm is used for the third substrate 1, and a thermal oxide film of 100 to 5000 ° is formed on the nitrided oxide film 3 a by dry O ₂ oxidation at 1000 ° C. It is formed by nitriding at 1000 to 1200 ° C. in a _three- gas atmosphere.

Next, the third substrate B is bonded to the surface of the first substrate 1 with the nitrided oxide film 3a interposed therebetween, and is mirror-polished.
Then, a single crystal silicon layer 101 having a thickness of about 5 μm is formed, and then ap ⁺ strain gage region 7a is formed in a predetermined region of the single crystal silicon layer 101 by ion implantation (see FIG. 20). Next, the single-crystal silicon layer 101 is patterned so that the single-crystal silicon layer 10 is formed only above the cavity 11.
Leave one. Note that this patterning is performed by anisotropic etching using KOH, and the side surface 102 is used as a tapered surface. This is to reduce the step. Next, patterning is performed by dry etching using the nitrided oxide film 3a as a strain-induced film (diaphragm film) (see FIG. 21). Here, the nitrided oxide film 3a covers the protective oxide film 4 and extends on the epilayer 6, and protects the protective oxide film 4 as in the first embodiment. Thereafter, a MOS integrated circuit is formed in the periphery by the steps of FIGS. 8 and 9 of the first embodiment.

In this way, a more accurate semiconductor pressure sensor can be manufactured. Further, in this embodiment, since the surface of the bonding substrate A is planarized by epitaxial growth and subsequent polishing, as a result,
The effect of improving the bonding with the third substrate B can be achieved without adding a process.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of an integrated semiconductor pressure sensor using the present invention;

FIG. 2 is a back plan view thereof,

FIG. 3 is a sectional view showing a manufacturing process of the first embodiment;

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the first embodiment.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of the first embodiment.

FIG. 6 is a sectional view showing the manufacturing process of the first embodiment.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the first embodiment.

FIG. 8 is a sectional view showing the manufacturing process of the first embodiment;

FIG. 9 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment.

FIG. 10 is a sectional view showing a manufacturing process of the first embodiment;

FIG. 11 is a sectional view showing the manufacturing process of the first embodiment;

FIG. 12 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment;

FIG. 13 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment;

FIG. 14 is a cross-sectional view illustrating a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment.

FIG. 15 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment;

FIG. 16 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment;

FIG. 17 is a sectional view illustrating a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment.

FIG. 18 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the second embodiment;

FIG. 19 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the third embodiment;

FIG. 20 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the third embodiment;

FIG. 21 is a sectional view showing a manufacturing process of the integrated semiconductor pressure sensor according to the third embodiment;

FIG. 22 is a cross-sectional view of a conventional integrated semiconductor pressure sensor.

FIG. 23 is a sectional view showing a manufacturing process of a conventional integrated semiconductor pressure sensor.

FIG. 24 is a sectional view showing a manufacturing process of a conventional integrated semiconductor pressure sensor.

FIG. 25 is a sectional view showing a manufacturing process of a conventional integrated semiconductor pressure sensor.

[Description of References] 1 is a first substrate (semiconductor substrate), 2 is a second substrate (semiconductor substrate), 4 is an oxide film (protective insulating film), 5 is a silicon nitride film (strain-induced film), and 6 is an epitaxial layer (Semiconductor area), 1
1 is a pressure chamber (cavity), 21 is a pressure introduction hole (cavity), 32 is a strain gauge,

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/84 G01L 9/04 101

Claims (1)

(57) [Claims] A semiconductor substrate having a cavity; a protective insulating film having a predetermined thickness formed on the surface of the semiconductor substrate and the surface of the cavity around the cavity; and a protective insulating film formed on the protective insulating film around the cavity. In a semiconductor device having a strain-generating film extending over a cavity and a strain gage formed on the strain-generating film, a surface of the protective insulating film is formed adjacent to a periphery of the protective insulating film. A semiconductor device having a semiconductor region coplanar with a surface thereof, wherein the strain-generating film extends over the semiconductor region.