JP3087697B2 - DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as "DRAM") having a block PDL for precharging / balancing bit lines.

[0002]

2. Description of the Related Art FIG. 6 shows a layout of a typical example of a stacked memory cell array and a PDL of a DRAM.

The PDL is a circuit for amplifying data in a memory cell and then balancing and precharging a digit line pair at a power supply or a ground level when rewriting to the memory cell is completed.

FIG. 6 shows a pair of bit lines 6 for simplicity.
11 and the 4-bit memory cell array 6 connected thereto.
Although 02 is shown, this is repeated a plurality of times in a normal DRAM. Similarly, the cell counter electrode poly (capacitance polysilicon) is not shown. The dummy word line will be described later.

As shown in FIG. 6, a PDL has a completely different shape from a memory cell.

FIG. 7 is a circuit diagram corresponding to the layout of FIG. The PDL includes a transistor A for connecting bit line pairs and a bit line pair 611, 611 '.
And a precharge level signal 603. The transistors A, B, and C input the bit line precharge signal 604 to the gate.

When the transistors A, B, and C are formed of N-type transistors, the bit line pair is balanced and set to the precharge level at the same time when the bit line precharge signal 604 goes high. Here, even though the transistor A is not provided, the bit line pairs are balanced, but the digit lines (bit line pairs) are connected by a single-stage transistor A in order to improve the balance speed.

[0008]

However, in places where dense patterns are regularly arranged, such as in a memory cell array, pattern deformation occurs around a boundary where pattern regularity is lost. This is called a “microloading effect” (that is, a phenomenon in which the etching rate decreases as the hole diameter or the etching width decreases).

When the PDL is arranged in the memory cell array, there is a problem that the stack polysilicon is deformed due to the microloading effect and the cell capacitance around the PDL is varied.

Further, when dummy word lines 605 (see FIG. 6) are arranged in order to eliminate the variation in cell capacity, there is a problem that the layout size becomes large.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device which eliminates a dummy word line for avoiding a microloading effect.

[0012]

According to the present invention, a PDL layout pattern is formed in the same shape as a cell transistor of a memory cell.

[0013]

Embodiments of the present invention will be described. In a preferred embodiment of the semiconductor memory device of the present invention, the microloading effect is avoided by forming the PDL layout pattern in the same pattern as the cell transistors of the memory cells. P
Even if the capacitance of the DL is deformed by the microloading effect, it does not pose a problem because the PDL is not used as a capacitance.

In a preferred embodiment of the semiconductor memory device according to the present invention, a PDL is arranged in a dummy word line region provided adjacent to a memory cell array,
The layout shape of the L portion is the same as the shape of the cell transistor of the memory cell except for the stack polysilicon forming the capacitance, and the dummy word line is not required.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described. FIG. 1 shows a typical stacked memory cell array 102,
FIG. 2 is a diagram illustrating a layout of a PDL 101 according to a first embodiment of the present invention. 2 is a cross-sectional view taken along line A1-A1 in FIG. 1, FIG. 3 is a cross-sectional view taken along line A2-A2 in FIG. 1, and FIG. 4 is a diagram showing an equivalent circuit of FIG.

Referring to FIG. 1, in the present embodiment,
In the layout pattern of the PDL 101, the shape other than the stack polysilicon forming the capacitance is the same as that of the memory cell. This can prevent the microloading effect of the memory cells adjacent to the PDL.
Note that even if the shape of the stacked polysilicon 106 'of the PDL 101 is deformed due to the microloading effect, P
In the DL 101, no problem occurs because the stack polysilicon is not used as a capacitor.

In addition, a bit line precharge level signal 103, which is conventionally often connected by a metal wiring, is
Since the power is supplied by the high-resistance stacked polysilicon 106 ', there is a concern that the precharge speed may decrease. ,
(2) One of the bit line pairs immediately before the precharge is at the power supply level and the other is at the ground level.
As you can see from the above two points, the precharge speed is not dominant to the balance speed,
There is no problem even if the precharge level signal has some resistance.

Next, the reduction in the balance speed due to the use of the stacked polysilicon will be discussed.

Even if the sheet resistance of the stacked polysilicon is high, since the length of the wiring connecting the precharge transistors of the bit line pair is short, the connection can be made with a resistance of several tens of Ω. This resistance value is sufficiently smaller than the ON resistance value of the transistor. Thus, there is no significant delay in the balance speed associated with the use of stacked polysilicon.

As described above, P is added to the dummy word line region.
By arranging the DL, it is possible to reduce the layout size of the conventional PDL area.

For reference, when applied to our 16 Mbit product, a chip size reduction of about 2 to 3% is possible.
Since there is no transistor corresponding to the transistor dedicated to bit line balance (transistor A in FIG. 7), there is a concern that the balance speed may be reduced. Since they can be arranged, the delay due to the resistance and capacitance of the bit line is reduced, and the same performance as that of the related art can be exhibited.

FIG. 5 shows a layout of a PDL according to a second embodiment of the present invention.

Referring to FIG. 5, in this embodiment, unlike the first embodiment, the PDL 101 is arranged inside the memory cell array 102.

The circuit is the same as that of the first embodiment. As described above, since the shape other than the stacked polysilicon forming the capacitance is the same as that of the memory cell, the PDL can be arranged inside the memory cell array without generating the microloading effect.

Conventionally, since a PDL circuit is attached to one of the long bit lines, a delay of several ns occurs between the resistance and the capacitance of the bit line at the far end of the bit line. Here, for example, when the total transistor size of the PDL circuit of the present invention is adjusted to that of the conventional PDL and scattered at six locations on the bit line, the delay is expected to be about 1/6 of the conventional. The layout size at this time can be made substantially the same by using the dummy word line region existing in the conventional example.

[0026]

As described above, according to the present invention,
The following effects are obtained by making the pattern shape of the PDL similar to that of the memory cell.

A first effect of the present invention is that the layout size can be reduced because the PDL can be arranged in the dummy word line region, which is arranged to prevent deformation of the stacked polysilicon.

The second effect of the present invention is that the PDL can be arranged in the memory cell array without worrying about the microloading effect, so that points for precharging / balancing bit lines can be scattered, and This means that the reduction of the precharge / balance speed due to the resistance and capacitance of the line can be reduced.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line A1-A1 of FIG.

FIG. 3 is a sectional view taken along line A2-A2 in FIG.

FIG. 4 is a diagram showing an equivalent circuit of FIG. 1;

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a layout diagram showing a conventional PDL and a memory cell.

FIG. 7 is a diagram showing an equivalent circuit of FIG. 6;

[Explanation of symbols]

 Reference Signs List 101 PDL 102 Memory cell array 103 Bit line precharge / level signal 104 Bit line precharge / balance signal 105 Word line gate polycide 106 Stack polysilicon 107 Diffusion layer 108 Bit contact 109 Capacitance contact 110 Bit line wiring silicide 111 Capacitance polysilicon 601 PDL 602 Memory cell array 603 Bit line precharge / level signal 604 Bit line precharge / balance signal 605 Dummy word line 606 Word line gate polycide 607 Diffusion layer 608 Stack polysilicon 610 Bit contact 611 Capacitance contact 611 Bit line wiring silicide

Claims (3)

(57) [Claims] 1. A dynamic semiconductor memory device having a circuit block (hereinafter, referred to as "PDL") for precharging / balancing bit lines, wherein a layout pattern of the PDL is formed in the same pattern as a cell transistor of a memory cell. A semiconductor memory device characterized in that: 2. A dynamic semiconductor memory device having a circuit block (hereinafter referred to as "PDL") for precharging / balancing bit lines, wherein said PDL is arranged in a dummy word line region provided adjacent to a memory cell array. The layout shape of the PDL portion is the same as the shape of the cell transistor of the memory cell except for the stacked polysilicon forming the capacitance,
A semiconductor memory device wherein a dummy word line is eliminated. 3. The semiconductor memory device according to claim 2, wherein a bit line precharge signal is formed of said stacked polysilicon.