JP3088564B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

(Table of Contents) Industrial Application Field Conventional Technology (FIG. 5) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (a) Description of One Embodiment (FIG. 2) To FIG. 4) (b) Description of Another Embodiment Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which processes an image in accordance with image processing data, writes the processed image into a memory, and reads the image in a predetermined order.

An image forming apparatus such as a copying machine, a printer, a display device, or the like processes one page of character data or other processing data to generate an image of one page of a character image or the like and forms an image. ing.

In such an image forming apparatus, as in an electrophotographic printer, which forms an image by line-scanning a photosensitive drum, an image is formed by line-scanning with image data. A memory is provided so that an image is written to the memory in units of characters and the like, and then the memory is read in units of lines.

It is desired that this image processing apparatus has a simple configuration and can perform image processing at high speed.

[0006]

2. Description of the Related Art FIG. 5 is an explanatory diagram of the prior art. The figure shows the character processing unit of the printer, and the microprocessor (MP
U) decodes print data from a higher-level device (such as a computer), issues image processing data such as commands / parameters, and outputs data to the FIFO buffer 1.
At 0, the image processing data is temporarily stored, and the speed is absorbed.

A raster image operator (RI)
O) 2 decodes the command / parameter of the FIFO buffer 10, reads out the corresponding character pattern from the character pattern storage unit 5 for storing the character pattern via the bus (RIO-BUS) 7, and performs necessary rotation, enlargement, etc. Processing is performed, and the data is written to a designated position in the page area of the bitmap memory 4 via the bus 7.

When the writing of one page is completed, the printer controller 3 issues a request signal BREQ to the arbitration circuit 6 in response to a printer start instruction from the printer engine unit, obtains a selection signal BSEL, and obtains a bus signal. After obtaining the exclusive right, the image data is read out from the page area of the bitmap memory 4 in units of lines and written into the FIFO buffer 30 for one line, and the printer engine unit converts the image data in the FIFO buffer 30 into a video signal according to raster scanning. And printing is performed.

The bit map memory 4 has a page area for two pages, and after one page has been written,
During reading of the printer controller 3, raster
The image operator 2 writes the next page.

Conventionally, even if the printer controller 3 occupies the bus 7 for a certain period of time and the one-character processing time of the raster image operator unit 2 becomes longer, the raster image program is stored in the raster image program. In order to prevent the program from being stopped because the operator unit 2 does not seem to be interrupted, a FIFO buffer 10 is provided to absorb the speed of the processor 1 and the speed of the raster image operator unit 2.

[0011]

However, the prior art has the following problems. The FIFO buffer 10 is expensive, for example, 51
If two 2-byte FIFO buffers are used, the FIFO
The buffer alone costs 10,000 yen and makes the device expensive.

Conversely, when the FIFO buffer 10 is removed, while the printer controller 3 occupies the bus 7, the program is in a stop state, and the performance of the apparatus is reduced.

Accordingly, it is an object of the present invention to provide an image processing apparatus capable of maintaining the performance of an apparatus even if an expensive FIFO buffer is deleted.

[0014]

FIG. 1 is a diagram illustrating the principle of the present invention. A first aspect of the present invention is a processor 1 that issues image processing data, an image processing unit 2 that performs image processing according to the image processing data, a memory 5 in which a processed image is written, and a content of the memory 5 is read. A read unit 3; a bus 7 connecting the image processing unit 2, the memory 5 and the read unit 3; and, in response to a bus use request from the read unit 3, the bus 7 is connected to the image processing unit. In the image processing apparatus used in a time-sharing manner by the read unit 2 and the read unit 3, the image process unit 2 is provided with a pair of buffers 20 for alternately receiving the image processing data of the processor 1, and the read unit 3 And an interval control circuit 31 for issuing a bus use request at a predetermined interval in response to a read request.

[0015] Claim 2 of the present invention is based on claim 1,
An arbitration circuit 6 for interrupting bus use of the image processing unit 2 in response to a bus use request of the read unit 3 is provided.

According to a third aspect of the present invention, in the first or second aspect, the interval control circuit 31 counts clocks in response to the read request and counts the number of set clocks to determine the bus use request. Counter 32 generated
It is characterized by including.

According to a fourth aspect of the present invention, in the first or second or third aspect, the image processing section 2 performs character processing according to the character processing data of the processor 1 and stores a character image in the memory 5. It is characterized by writing.

[0018] Claim 5 of the present invention is based on claim 4,
The image processing unit 2 writes the character image in a page area of the memory 5, and the reading unit 3
The contents of the page area are sequentially read in the line direction.

[0019]

According to the first aspect of the present invention, basically, even if the speed of the image processing unit 2, which is hardware, is faster than the firmware speed of the processor 1, one character processing time of the image processing unit 2 is reduced. The double buffer 20 is provided to prevent the firmware processing from being temporarily delayed in some cases.

Next, if the processing of the image processing unit 2 is frequently interrupted due to the exclusive use of the bus by the reading unit 3, the hardware processing time increases with respect to the firmware processing time.
Since the buffer becomes full and a firmware WAIT occurs, the image processing unit 2 is not stopped frequently, so that the reading unit 3 accesses the memory at regular intervals within a range where data to the printer engine or the like can be reached in time. Thus, the interval control circuit 31 is provided.

If a certain interval is provided in this manner, since the delay is a temporary delay, it can be absorbed by the double buffer 20. According to the second aspect of the present invention, since the arbitration circuit 6 is provided, the reading unit 3 can use the bus 7 at a constant interval smoothly.

According to the third aspect of the present invention, since the interval control circuit 31 is constituted by the counter 32, it can be realized with a simple configuration. According to the fourth aspect of the present invention, since the image processing unit 2 performs character processing, even if the processing time of one character is temporarily delayed depending on the processing content, it can be absorbed with a simple configuration.

According to a fifth aspect of the present invention, the image processing unit 2
Is written to the memory 4 in image units,
Are read out in line units, so that image processing can be performed efficiently and an image in line units can be obtained.

[0024]

【Example】

(a) Description of one embodiment FIG. 2 is a configuration diagram of one embodiment of the present invention, and FIG. 3 is a main part configuration diagram of one embodiment of the present invention, showing a control unit of an electrophotographic printer.

2 and 3, the same components as those shown in FIG. 5 are denoted by the same symbols. The raster image operator unit 2 includes, as shown in FIG.
A double buffer 20 composed of a pair of buffer registers and alternately receiving character processing data of the processor 1;
A command analyzing unit 21 for analyzing a command of character processing data of the double buffer 20, an address calculating unit 22 for calculating an address based on data of the double buffer 20 and the command analyzing unit 21, and a data processing such as rotation and enlargement of a character pattern And a data processing unit 23 for transmitting the address of the address calculation unit 22 to the bus 7.
3 transmits and receives a character pattern.

As shown in FIG. 3B, the interval control circuit 31 provided in the printer controller 3
It comprises a counter 32, a flip-flop 33, a NAND gate 34, and an inverter 35.

Then, the printer start PRC / ST
The ART resets the counter 32, enables the count, and sets the interval setting value (here, “3”).
Is loaded, the bus cycle clock RCLK0 from the arbitration circuit 6 is counted, the flip-flop 33 is set by the carry output CRY, and the arbitration circuit 6
, A bus request signal BREQ.PRC is generated, and the flip-flop 33 is reset by the selection signal BSEL.PRC from the arbitration circuit 6.

FIG. 4 is a time chart of a main part of an embodiment of the present invention. The operation will be described below.
Decrypts print data from a higher-level device (such as a computer)
It issues character processing data such as commands / parameters, and sends it to the double buffer 2 of the raster image operator unit 2.
Store to 0.

The raster image operator (RI)
In O) 2, the command / parameter of the double buffer 20 is analyzed by the command analyzer 21 and the address
The corresponding character pattern is read from the character pattern storage unit 5 for storing the character pattern via the bus 7 and stored in the data processing unit 23, and then subjected to necessary processing such as rotation and enlargement. The data is written into the page area of the memory 4 at the position specified by the address calculation unit 22.

When the writing of one page is completed, the printer controller 3 causes the interval control circuit 31 to respond to the printer start command PRC / START from the printer engine as shown in FIG. When three RCLK0s are counted, a request signal BREQ • PRC is issued to the arbitration circuit 6 to obtain a selection signal BSEL • PRC, thereby obtaining a bus exclusive right.

The printer controller 3 reads out the image data (2 bytes) from the page area of the bitmap memory 4 in line units, and reads one line of F data.
The data is written into the I / O buffer 30, and the printer engine unit reads out the image data in the FIFO buffer 30 as a video signal in accordance with the raster scanning and performs printing.

This bitmap memory 4 has a page area for two pages, and after the writing of one page is completed,
During reading of the printer controller 3, raster
The image operator 2 writes the next page.

Therefore, as shown in FIG.
After the cycle is used by the raster image operator unit 2, the printer controller 3 uses it for one cycle.

Conventionally, when a printer start command is received, the printer controller 3 immediately generates a bus use request. Therefore, the bus 7 is alternately connected to the raster image operator unit 2 and the printer controller 3 one cycle at a time. Had to use it.

In this way, the data for one raster to the printer engine unit is quickly arranged, and the data is arranged before the raster scanning of the printer engine unit. However, since the FIFO buffer 30 is provided, the data is acquired before the raster scanning. There is no need to get together.

Therefore, even if the bus 7 is opened to the raster image operator unit 2 at a fixed interval (here, every four cycles) by the bus request of the printer controller 3, the raster scan of the printer engine unit is delayed. Never.

In this way, the hard raster
Even if the speed of the image operator unit 2 is faster than the firmware speed of the processor 1, even if the one-character processing time of the raster image operator unit 2 is temporarily slower than the firmware time due to rotation, etc. The data can be absorbed by the double buffer 20 so as not to affect the firmware processing.

Further, if the processing of the raster image operator unit 2 is frequently interrupted due to the exclusive use of the bus by the printer controller 3, the hardware processing time increases with respect to the firmware processing time, the buffer becomes full, and the WA of the firmware becomes full.
Since the occurrence of IT does not stop the raster image operator unit 2 frequently, the printer controller 3 makes the memory access at regular intervals as long as the data to the printer engine or the like can be reached in time. If a certain interval is provided in this way, since the delay is a temporary delay, it can be absorbed by the double buffer 20.

(B) Description of Other Embodiments In addition to the above-described embodiments, the present invention can be modified as follows. In the above-described embodiment, the image forming apparatus is described as an electrophotographic printing mechanism. However, the present invention can be applied to other printing mechanisms (for example, an electrostatic recording mechanism or the like) or a raster scanning device such as a display.

Although the interval set value is 3, other values may be used, and the program may be changed according to the resolution of the printer. Although the character pattern storage unit 5 and the bitmap memory 4 have been described separately, one memory may be used.

Although the character pattern is stored in the character pattern storage section, the character pattern may be generated by storing character outline data and the like. Although the image processing has been described using character processing, the present invention can be applied to other image processing.

The present invention has been described with reference to the embodiments.
Various modifications are possible within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0043]

As described above, according to the present invention,
The following effects are obtained. Since the temporary buffer of the processing of the image processing unit is absorbed by the double buffer, an expensive FIFO buffer can be omitted, and the apparatus price can be reduced.

Also in this case, since the use of the bus of the reading unit is restricted at regular intervals and the bus is opened to the image processing unit, a temporary delay of the image processing unit can be absorbed by the double buffer, and The wait state of the farm can be prevented.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a main part of an embodiment of the present invention.

FIG. 4 is a time chart of a main part of one embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processor 2 Raster image operator part (image processing part) 3 Printer controller (reading part) 4 Bitmap memory 5 Character pattern storage part 6 Arbitration circuit 7 Bus 20 Double buffer 30 FIFO buffer 31 Interval control circuit 32 Counter

Claims (5)

(57) [Claims] 1. A processor (1) for issuing image processing data, an image processing unit (2) for performing image processing according to the image processing data, a memory (5) in which a processed image is written, and the memory (5). ), And a bus (7) connecting the image processing unit (2), the memory (5), and the reading unit (3), and the reading unit (3). ), The image processing unit (2) and the read-out unit (3) use the bus (7) in a time-division manner in response to the bus use request of the image processing unit (2). A pair of buffers (2) for alternately receiving the image processing data of the processor (1)
0), and the reading unit (3) further includes an interval control circuit (31) for issuing a bus use request at a predetermined interval in response to the read request. 2. An image according to claim 1, further comprising an arbitration circuit for interrupting a bus use of said image processing unit in response to a bus use request of said read unit. Processing equipment. 3. The interval control circuit (31)
3. The image processing apparatus according to claim 1, further comprising a counter that counts a clock in response to the read request and generates the bus use request by counting a set clock number. 4. The image processing unit (2) performs character processing according to character processing data of the processor (1), and writes a character image into the memory (5). Or 2 or 3 image processing devices. 5. The image processing unit (2) writes the character image to a page area of the memory (5), and the reading unit (3) sequentially reads the contents of the page area in a line direction. Claim 4
Image processing equipment.