JP3089653B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an output driver of a semiconductor integrated circuit.

[Conventional technology]

A conventional technique will be described using an example of a MOS transistor.

FIG. 8 shows an inverter type output driver using a conventional MOS transistor, and FIG. 9 shows an equivalent circuit diagram of FIG.

First, the operation of the inverter type output driver will be described. In FIG. 8, when a low level (hereinafter simply referred to as L level) is applied to an input terminal 801, a P-channel MOS transistor (hereinafter simply referred to as PMOS) 802 is in an ON state, and an N-channel MOS transistor (hereinafter simply referred to as NMOS). 803) is turned off, and a high level (hereinafter simply referred to as H level) is output to the output terminal 804. Conversely, when an H level is applied to the input terminal 801, the PMOS 802 is turned off, the NMOS 803 is turned on, and an L level is output to the output terminal 804.

The above operation will be described with reference to FIG. Input terminal 901
When the L level is applied to the NMOS, the PMOS 902 is turned on, and the NMOS 9 is turned on.
03 is turned off, and PMOS 9 is turned on via the ON resistor 931 of PMOS 902.
A positive charge is charged in the capacitor 923, which is the sum of the diffusion capacitance of the drain of the NMOS 02 and the drain of the NMOS 903 and the wiring capacitance connecting the drains, and when this is completed, an H level is output to the output terminal 904. Conversely, when an H level is applied to the input terminal 901, the PMOS 902 is turned off, the NMOS 903 is turned on, and N
The capacitor 923 is charged with a negative charge via the ON resistance 932 of the MOS 903, and when the charge ends, an L level is output to the output terminal 904.

Next, the characteristics of the output driver will be described. The characteristics of the output driver are determined by what characteristics the side receiving the output signal of the output driver as an input signal (hereinafter simply referred to as a connection target) requires. For example, if the connection target requires high-speed operation, use a transistor with a large transistor size and a large load drive capability to configure an output driver with ON resistance 931, 932 low and agile switching characteristics, Conversely, when low-noise operation is required, a gradual switching operation is generally realized by using a transistor having a small transistor size and a small load driving capability.

[Problems to be solved by the invention]

According to the conventional technology, the characteristics of the output driver need to be determined at the design stage of the output driver whether the connection target of the output driver requires high-speed operation or low-noise operation. Since the transistor size etc. of the output driver is determined according to the requirements, the only way to change the characteristics of the output driver due to the change of the required characteristics of the connection target is to respond to the design change. That is, the characteristics of the output driver need to match the required characteristics of the connection target of the output driver, and the degree of freedom of design is limited.

Therefore, the present invention solves such a problem. The purpose of the present invention is not to pay attention to the correlation between the output driver and the connection target of the output driver, and the connection target is different on the output driver side. An object of the present invention is to provide an output driver that can cope with a case where a plurality of characteristics are required, without changing the design of the output driver.

[Means for solving the problem]

A semiconductor device according to the present invention includes an input terminal to which an input signal is input, a control terminal to which a control signal is input, an output terminal to which an output signal obtained by inverting or inverting the input signal is output, and the input signal Control means for controlling a switching time from input of the input signal to output of the output signal so as to be selectively switched in accordance with the control signal; and a series connection between a first power supply terminal and the output terminal. A plurality of first conductivity type MOS transistors connected in series, and a plurality of second conductivity type MOS transistors connected in series between a second power supply terminal and the output terminal. According to a control signal, at least one of the first conductivity type MOS transistor and the second conductivity type MOS transistor is turned on, and the remaining MOS transistors are switched. And

Also, the first conductivity type MOS transistor and the second
The n-type (where n ≧ 2) conductivity-type MOS transistors are connected in series, and the first conductivity-type MOS transistor and the first conductivity-type MOS transistor are present on the sides closer to the first power supply terminal and the second power supply terminal, respectively. The combination of the two-conductivity-type MOS transistors is the first combination, and the combination of the first-conductivity-type MOS transistor and the second-conductivity-type MOS transistor present on the side closer to the output terminal is n.
In the case of the third combination, the control means controls so as to select which one of the first to n-th combinations to perform the switching operation.

〔Example〕

The semiconductor device of the present invention will be described in detail based on an embodiment using a MOS transistor.

The semiconductor device of the present invention basically has the configuration shown in FIG. In FIG. 1, the inside of the broken line 100 is an inverter type output driver, and the inside of the broken line 101 is means for controlling the characteristics of the output driver within the broken line 101 (hereinafter simply referred to as control means).

The output driver 101 is composed of a PMOS and an NMOS. It has a CMOS structure in which the drain of NMOSL15 is connected.

The control means 100 includes an inverter 104, AND gates 105, 106, O
A signal input to an input terminal 102 is controlled by a signal input to a control terminal 103, and a PMOSL13 which is an output driver through the AND gates 105 and 106 and the OR gates 107 and 108. , 114, NMOSL15, and 116, respectively, to the PMOSL13 and NMOSL16 or PM
A signal is transmitted to output terminal 117 by one of the switching operations of the combination of OSL14 and NMOSL15.

The actual operation is shown in the equivalent circuit diagram of the output driver.
This will be described using the truth table of FIG. 3 and FIG. Control terminal 10
When L level is applied to 3, output signal 1 of AND gate 105
09 is fixed at the L level, the output signal 112 of the OR gate 108 is fixed at the H level, and the PMOSL13 and the NMOSL constituting the output driver are fixed.
16 is fixed to the ON state. Therefore, the signal input to the input terminal 102 operates the CMOS inverter using the PMOS L14 and the NMOS L15, and appears at the output terminal 117 as an inverted output.

Conversely, when an H level is applied to the control terminal 103, the output signal 110 of the AND gate 106 is fixed at the L level, the output signal 111 of the OR gate 107 is fixed at the H level, and the PMOS L14 and the NMOS L15 constituting the output driver are turned on. Fixed. Therefore, the signal input to the input terminal 102 is C
The MOS inverter operates and appears at the output terminal 117 as an inverted output.

This series of operations will be described with reference to the equivalent circuit diagram of FIG. The resistance 230 is the ON resistance of the PMOS 213, and the capacitance 221 is the diffusion capacitance in the region where the drain of the PMOS 213 and the source of the PMOS 214 are connected. The resistance 231 is the ON resistance of the PMOS 214, and the resistance 232 is N
MOS215 ON resistance, resistance 233 is NMOS216 ON resistance, capacitance 222
Is a diffusion capacitance in a region where the drain of the NMOS 216 and the source of the NMOS 215 are connected. The capacitance 223 is the sum of the diffusion capacitance of the drain region of the PMOS 214, the diffusion capacitance of the drain region of the NMOS 215, and the wiring capacitance connecting the drain of the PMOS 214 and the drain of the NMOS 215.

When an L level is applied to the control terminal 103, the PMOS 213 and the NMOS 216 are fixed in the ON state, so that the capacitor 221 has an ON resistance.
The positive charge is charged through 230, and the capacitance 222 turns ON resistance 233
Is charged with a negative charge. In this state, when the L level is applied to the terminals 210 and 221, the PMOS 214 becomes O
The N and NMOS 215 are turned off, the capacitor 223 is charged with a positive charge via the ON resistor 231, and when that is completed, an H level is output to the output terminal 217.

Conversely, when an H level is applied to terminals 210 and 211, PM
The OS 214 is turned off, the NMOS 215 is turned on, and the capacitor 223 is charged with a negative charge via the ON resistor 232. When the charge ends, the L level is output to the output terminal 217.

Next, the case where the H level is applied to the control terminal 103 will be described. In this case, the PMOS 214 and the NMOS 215 are fixed in the ON state. In this state, when an L level is applied to the terminals 209 and 212, the PMOS 213 turns on and the NMOS 216 turns off.
Then, a positive charge is charged to the capacitor 221 via the ON resistance 230 of the PMOS 213, and then the capacitor 223 is charged via the ON resistance 231 of the PMOS 214.
The capacitor 222 is charged with a positive charge through the ON resistor 232 of the NMOS 215, and when the charge ends, an H level is output to the output terminal 217.

Conversely, when an H level is applied to the input terminals 209 and 212, the PMOS 213 turns off and the NMOS 216 turns on. Then NMOS216
Negative charge is charged to the capacitor 222 through the ON resistor 233 of NM.
The capacitor 223 is charged with a negative charge via the ON resistor 232 of the OS 215, and the capacitor 221 is charged with a negative charge via the ON resistor 231 of the PMOS 214.
The level is output.

Thus, the switching operation is performed by the control means.
Depending on whether the combination of PMOS and NMOS is closer to the power supply or closer to the output terminal, the operation of charging the diffusion capacitance in the region where the drain and source of the transistor of the same channel connected in series are connected is required. Input terminal to become
The time until the inverted signal of the signal applied to 102 appears at the output terminal 117, that is, the switching time will be different.

The above embodiment is merely an example, and the configuration method of the control means is not particularly limited. By configuring the control means as shown in FIG. 4, it is also possible to configure a type of circuit that outputs a non-inverted signal of the signal input to the input terminal 402 to the output signal 417.

Further, as shown in FIG. 6, by providing a control means having two control terminals 603 and 604 and an output driver section in which the P-channel side and the N-channel side are connected in series of four,
Output drivers having different switching characteristics can be configured.

〔The invention's effect〕

As described above, according to the present invention, a CMOS type output driver composed of a serially connected PMOS side and NMOS side is provided by adopting a configuration having an output driver and control means for controlling the characteristics of the present output driver. It is possible to select the combination of PMOS and NMOS related to the final switching operation from among the above, and to set the diffusion time of the drains of the PMOS and NMOS of the output terminal section and the charging time of the wiring capacitance of the wiring connecting the respective drains. In addition, a plurality of switching characteristics can be realized by using the charging time of the region where the drain and the source of the transistor of the same channel connected in series are connected.

That is, a PMOS that performs the final switching operation and
When the combination of NMOSs is on the side closer to the output terminal, only the diffusion capacitance of the PMOS and NMOS drains of the output terminal and the wiring capacitance connecting the respective drains need to be charged, so that high-speed switching operation is possible. Yes, this is effective when the connection target of this output driver requires high-speed operation.

Conversely, PMOS and NMOS for final switching operation
If the combination exists on the side close to the power supply, in addition to the diffusion capacitance of the drain of the PMOS and NMOS of the output terminal and the wiring capacitance connecting each drain, the source and drain of the transistor of the same channel connected in series Since it is necessary to charge the diffusion capacitance in the connected area, the switching characteristics are gradual, and this is effective when the connection target of this output driver dislikes noise.

Therefore, this output driver can select and provide different switching characteristics by the control means for various specifications that the connection target requires on the output driver side,
It is possible to reduce the number of design steps of an output driver that has been individually designed for the characteristics of the connection targets, and it is possible to flexibly handle a large number of connection targets with a single output driver.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment, FIG. 2 is an equivalent circuit diagram of the driver section of FIG. 1, FIG. 3 is a diagram showing a truth table of FIG. 1, and FIG. 4 and FIG. FIG. 5 is a diagram showing the truth table of FIG. 4, FIG. 7 is a diagram showing the truth table of FIG. 6, and FIG. 8 is a diagram showing a conventional embodiment. , Ninth
The figure is an equivalent circuit diagram of FIG. 100, 400, 600 Control means 101, 401, 601 Output driver 102, 402, 602, 801, 901 Input terminals 103, 403, 603, 604 Control terminals 117, 217, 417, 623, 804904 output terminals 104, 404, 605, 606 inverters 105, 106, 607 to 610 AND gates 107, 108, 611 to 614 OR gates 109 to 112, 409 to 412, 615 to 622 Internal signals 209-212 ... Terminals 113, 114, 213, 214, 413, 414, 603-633, 802, 902 ...
... P-channel MOS transistors 115, 116, 215, 216, 415, 416, 634-637, 803, 903 ...
… N-channel MOS transistors 230 to 233, 931, 932… ON resistance 221, 222… Diffusion capacitance 223, 923… Diffusion capacitance and wiring capacitance 405, 406… NOR gate 407, 408… NAND gate

Claims (2)

(57) [Claims] An input terminal for receiving an input signal; a control terminal for receiving a control signal; an output terminal for outputting an output signal obtained by inverting or inverting the input signal; Control means for controlling a switching time from when the output signal is output to when the output signal is output, in accordance with the control signal, and connected in series between a first power supply terminal and the output terminal A plurality of first conductivity type MOS transistors, and a plurality of second conductivity type MOS transistors connected in series between a second power supply terminal and the output terminal.
A conductive type MOS transistor, wherein the control means turns on at least one of the first conductive type MOS transistor and the second conductive type MOS transistor in response to the control signal, and sets the remaining MOS transistors A semiconductor device characterized by performing a switching operation. 2. The semiconductor device according to claim 1, wherein the first conductivity type MOS transistor and the second conductivity type MOS transistor are n pieces (where n ≧ 2).
The first conductive type MOs connected in series one by one and present on the sides closer to the first power supply terminal and the second power supply terminal, respectively.
The combination of the S transistor and the second conductivity type MOS transistor is a first combination, and the combination of the first conductivity type MOS transistor and the second conductivity type MOS transistor present on the side closer to the output terminal is the nth combination. The combination according to claim 1, wherein the control means performs control so as to select which combination of the first to n-th combinations is to be subjected to the switching operation. 13. The semiconductor device according to claim 1.