JP3092299B2 - Decoding device for run-length 1 / n compressed floating code - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus used for high-quality recording and transmission of image data, and particularly to a run-length 1/2 signal having a good instantaneous S / N ratio characteristic over a wide input range.
The present invention relates to a decoding device for n-compressed floating codes.

[0002]

2. Description of the Related Art In conventional satellite PCM broadcasting and digital audio tape recorders (hereinafter abbreviated as DATs), relatively light compression is obtained as a result of taking into account a trade-off with the amount of hardware while suppressing quality deterioration due to compression. The rate is adopted. Examples of these are the line symbols,
In the DAT, a 12-bit 13-line code is used. The detailed technical standard is “EIAJ CP-2305 DAT Cassette” issued by the Japan Electronics Machinery Association.
e System Part1: Dimension
and Characteristics ".

[0003] FIG. 19 (b) shows the 1
It is a figure explaining the conversion method of a three-fold line code (12 bits), and shows a positive range. In the frame in the figure, the numbers in parentheses are decimal numbers, and the other numbers are binary numbers. The most significant bit (MSB) of the binary number is a polarity bit P
And is “0” in the positive range and “1” in the negative range. “ABCDEFGH” in the figure is “00000000”
"0" to "11111111", and "*"
Is any binary number. L0 is the run length of the continuous data Q0 in which “0” continues in the upper order excluding the polarity bit of the original data. For the above encoding method,
The procedure will be described below.

FIG. 19 (b) is a diagram specifically showing conversion between encoding and decoding. First, a description will be given of a method and apparatus for encoding a 13-line segment code (12 bits). 16
The bit area is divided into seven in the positive range, and the shift amount is operated according to each area. As can be seen from the figure, the area division can be performed at a position where "1" is initially located when viewed from the MSB side. In other words, it can be determined by the run length L0 of the continuous data of “0” excluding the polarity bit. The run length L0 is set to 8 types from “0” to “7 or more”, and L
The complement of 0 is expressed as exponent as range data. For example,
The original data is “1216 (decimal)”, that is, “0000”
00100110000 (binary) ", the run length L0 of the continuous data Q0 is" 4 ". The range data Q2 is “011” obtained by inverting “100”. “ABCDEFGH” is “00110000”. Therefore, the output data is “00110011000
0 ". FIG. 19A is a diagram schematically illustrating the above concept. The output data is composed of the polarity bit P, the range data Q2 representing the area, and the shifted mantissa data D2 to form 12 bits. Range data Q2 has a fixed word length and is 3 bits. In the case where the original data is 2'S (toe's) complementary, encoding can be performed in exactly the same manner as in the positive range by inverting all bits below the P in the negative range. In this manner, a code obtained by inverting bits in a negative range is called a folded binary code. In the following description, a folded binary code will be used unless otherwise specified, but conversion with 2'S complementary is mutually possible.

Next, a method and an apparatus for decoding a 13-fold line code (12 bits) will be described.

[0006] Decoding is performed by using line data range data Q2.
Is known, the exponent, that is, the range is reproduced by looking at the three bits after the polarity bit P. Since the position of the mantissa data D2 is also known, the run length L0 of the linear code (16 bits) is restored using the range data Q2, and the inversion bit T0 and the mantissa data D2 are added thereafter. If it is less than the code length W0 of the original data, a fixed value is used. The decoding process is performed according to such a procedure.

[0007] When the encoding and decoding described above are performed, the expression precision changes due to rounding of information. The rounding of information occurs by a shift operation. Run length L0 is "6"
And “7 or more” are the same, so there are seven types of shifts. Therefore, although there are 14 types of positive and negative, the same shift operation is performed for positive and negative in the center area, so that the input / output characteristics of the entire area can be represented by 13 types of polygonal lines.

[0008] In each area of FIG.
The expression accuracy, that is, the resolution, changes depending on the run length L0. When the run length L0 is “0” to “6”,
The resolution is 10 bits to 16 bits in terms of word length conversion bits.

The contents described above are summarized in (Table 1).

[0010]

[Table 1]

FIG. 20 is a characteristic diagram of a restored code obtained by decoding a compressed code of a conventional encoding device using a broken line code by a decoding device and expanding the decoded code. In the figure, the horizontal axis represents the input level, and the vertical axis represents the instantaneous S.
/ N ratio. However, the instantaneous S / N ratio is the S / N of the square wave.
About 2 dB of the ratio improvement is omitted for simplicity. In the figure, Z1 indicates the characteristics of the 13-line code (12 bits). Z1 will be described. The input level 0 dB is based on the maximum sine wave amplitude that can be represented by a code. The linear code “P11111111111111
"1" corresponds to this. Input level 0dB to -6d
In the range of B, it becomes “P1 ***...
According to Table 1, since the run length L0 is "0", the resolution is 10 bits. The quantization noise of 10-bit data is -60 dB, assuming -6 dB per bit. Accordingly, the instantaneous S / N ratio at the input level of 0 dB to -6 dB is 60 dB to 54 dB.

Next, an input level of -6 dB to -12 d
In the range of B, the linear code is “P01 ***...”, And since the run length L0 is “1” from (Table 1), the resolution is 11 bits. The quantization noise of 11-bit data is -66 dB. Therefore, the instantaneous S / N ratio is 6
It becomes 0 dB to 54 dB. Hereinafter, similarly, -96 dB
The instantaneous S / N ratio is obtained in the region up to and a characteristic curve is Z1. Here, when the input level is −36 dB or less, the characteristic curve is the same as the characteristic curve of the linear code (16 bits).

[0013]

However, in the above-mentioned conventional apparatus, the instantaneous S / N ratio is only 60 dB at best, and the instantaneous S / N ratio is smaller at a very small input level as with the linear code (16 bits). descend. In a digital recording / reproducing apparatus for business use which requires a margin (headroom) for an excessive input, recording is performed with the average input level set low, so that the usable dynamic range is substantially narrowed and the input level is reduced. Since the instantaneous signal-to-noise ratio becomes insufficient in a considerable range, there is a problem that deterioration is increased in editing in which amplification and attenuation are repeated. As described above, this problem is the same even with a linear code (16 bits).

[0014] Preferably, it is required that the instantaneous signal-to-noise ratio characteristic exceeding the auditory detection limit of about 48 dB or more be satisfied in a wide range of input levels from 0 to -96 dB.

As an improved method for this purpose, a method of extending the conventional 13-line code (12 bits) to 16 bits can be easily considered. (Table 2) is a linear code (20 bits)
This shows a method of converting from to a broken line code (16 bits). In Table 2, since the word length of the mantissa data D2 is 12, the resolution is increased by 4 bits as a whole.

[0016]

[Table 2]

A broken line code (16 bits) shown in Table 2
The characteristic diagram of the decompressed code that decodes and decompresses the compressed code by using is as shown by Z2 in FIG. In the device according to this improved method, the instantaneous S / N ratio is improved by 24 dB in all regions, but the instantaneous S / N ratio is insufficient at input levels in the range of -72 dB to -96 dB, which is less than 48 dB.
Therefore, if this signal is amplified by an amplifier, the quantization noise still has a problem that the auditory sense is detected.

The present invention has been made to solve the above-mentioned conventional problems, and has as its main object to secure an instantaneous S / N ratio of about 48 dB or more, which is a hearing detection limit, in a wide range from 0 to -96 dB. I do. The other purpose is to provide a device that supports positive and negative polarities, prevents offset bias that is parasitic in the exponent range, embodies the decoding of compressed residual data, and realizes high-speed continuous processing by pipeline processing. It is to be.

[0019]

In order to achieve this object, a run-length 1 / n compressed floating encoder according to the present invention comprises: a compressed continuous data Q1 in which bits of a predetermined logic are consecutively arranged in a high order; Inverted bit T1 for breaking continuity, compressed remainder data C1 representing remainder F1 generated when compressing run length, and mantissa data D
1, an input unit for inputting the compressed data constituted by 1, a C1 memory for storing the compressed remainder data C1, and a run length of Q1 expanded by n times, and continuous data having a length corresponding to the value of the C1 memory is added. , Q0 by adding an inverted bit T0 for breaking the continuity, and subsequently adding mantissa data D1, and an output unit for reading out the continuous data Q0, the inverted bit T0 and the mantissa data D0 from the expanding means and outputting the expanded data. And

However, when the run length of the continuous data Q0 is L0, the run length of the compressed continuous data Q1 is L1, the remainder obtained from the compressed remainder data C1 is F1, and n is an integer of 2 or more, L0 = L1 * n + F1 D0 = D1.

For another purpose, an MSB latch for storing a polarity bit, an input means for input distribution, an output means for multiplexing odd data, and an expansion means for adding fixed data to a lower part of compressed data. Or a decompression means for adding a run length according to the value of the compression remainder data C1.

[0022]

According to the present invention, a run-length 1 / n-compressed floating code obtained by compressing a run-length to about 1 / n is input to an input unit by the above-described apparatus. The input section supplies the captured compressed data to the C1 memory and the decompression means. The C1 memory stores and retains the extracted compressed remainder data C1 and supplies this data to the decompression means. Decompression means decompresses the fetched compressed data by n times, further extends the run length based on the compressed remainder data input from the C1 memory, adds an inversion bit, and further outputs the data to which the mantissa has been added to the output section. Supply. The output unit outputs the data from the expansion means, that is, the original data restored by the expansion, to the outside.

The run length 1 / n compressed floating code, which is compressed data, forms an exponent part, that is, a range, with the compressed continuous data, the inverted bit, and the compressed remainder data. The exponent, that is, the range, changes as follows according to the run length of the original data. That is, when the run length of the original data is small, the exponent part, that is, the range is represented by a small number of bits, and when the run length becomes large, the bit number is further allocated to represent the exponent part, that is, the range. Further, since the word length of the entire code is set to a predetermined length, the number of bits allocated to the mantissa part changes according to the run length. By these operations, the expression space of the compression code output from the output unit is expanded, and the expression accuracy can be maximized. Such compressed data can be restored.

Also, the absolute value of the input data is taken by the MSB latch and the binary code is folded back to correspond to the positive and negative polarities, and the fixed value "100..." Or " 011..., Is applied, thereby preventing the offset bias that is parasitic in the exponent part range, performing additional expansion of the run length according to the compression remainder data using the output data of the C1 memory, and performing input distribution and output means output. High-speed continuous processing can be performed by pipeline processing by the multiplexing selector.

[0025]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of a decoding apparatus for a run-length 1/2 compressed floating code according to a first embodiment of the present invention. The operation will be described with reference to the drawings.

MSB represented by 2'S complement
First serial data CMPDAT is input unit 10
01 is input. The input unit 1001 converts the 2'S complement into a folded binary code. The conversion to the folded binary code is because the subsequent processing is simplified.
In the input unit 1001, the MSB which is the polarity bit is set to M
MSB stored in SB memory 1002 and stored
Inverts and converts bits below the MSB. Thus, the decompressed binary encoding using the absolute value of the input data enables the same decompression decoding processing for both positive and negative polarities, thereby simplifying the hardware. The folded binary code is supplied to decompression means 1003, and C1
It is also supplied to the memory 1004. The decompression means 1003 is constituted by a shift register with a shift enable function and sequentially stores input data inside. However, only the compressed remainder data C1 is masked for shift input, and the subsequent mantissa data is stored left-justified. . The decompression unit 1003 outputs the data stored in the output unit 1005 at the next timing.
At this time, for the run length portion, the output shift is substantially doubled by setting the output shift enable to every other output and output. The output unit 1005 is M
The 2'S complement output data obtained by multiplexing the data of the SB memory 1002 and the data of the decompression means 1003 is output to the outside. The timing generation unit 1006 supplies a required timing signal to each unit.

FIG. 2 is a schematic operation timing chart in the first embodiment. The format of the input data is MSB-first serial data represented by the 2'S complement as described above. The 16-bit data is input with the MSB justified. SFCK is a clock having a frequency twice the bit clock and 64 times the sampling frequency.
That is, one bit is input in two cycles of SFCK. As another method, one bit may be input in one cycle of SFCK and the data may be left-justified, and the rear may be filled with zero data. Since the L channel and the R channel are multiplexed, a time equivalent to 32 clocks is allocated only with the L channel. LR
CK is a clock for identifying the L channel and the R channel.

The L channels of such input data are output at the next R channel input timing. The output data that has been expanded to 28 bits outputs one bit in one cycle of SFCK. The last four bits are filled with zero data.

In order to simultaneously expand the data of the R channel, two decoding devices 1008 shown in FIG. 1 are arranged and processed in parallel.

FIG. 3 is a block diagram of a decoding device for expanding the L channel and the R channel. In FIG. 3, the decoding device 1008A and the decoding device 1008B are the same device, and the input device
Inverter 1090 is inserted before 02B. The output data 1804A and the output data 1804B are
The multiplexed output data 1904 is output as output data DADT. In this way, high-speed continuous processing can be performed by pipeline processing by the multiplexing selector of the input distribution and output means.

FIG. 4 is a specific circuit diagram of the expansion means 1003. The expansion means is composed of 14 shift registers.
The shift registers 1301 to 1314 are synchronous enable type shift registers with asynchronous reset. These are serially connected in sequence, and a common clock SFCK and
It supplies a common enable signal DSFEN and a common asynchronous load signal NLO1T. In the figure, the input data DSIDT is the logic "H" when the enable signal DSFEN is logic "H".
At this time, the data is latched by the shift register 1301 at the rise of the clock SFCK, and at the same time, the internal data is sequentially shifted to the right. When the asynchronous load signal NLO1T is supplied, data "000... 0" is directly loaded and cleared.

FIG. 5 shows shift registers 1301 through 130.
14 is an internal circuit diagram of FIG. The description of the operation is omitted because it is a basic circuit.

FIG. 6 is a specific circuit diagram of the MSB memory 1002. Input data CMPDAT is input from a terminal 1201, and the MSB is latched by a DFF with synchronization enable composed of a selector 1021 and a D-type flip-flop (hereinafter, referred to as DFF) 1022. Since the data is MSB first data, it is enabled by NLO1T which becomes logic "L" in the first bit slot of the L channel. The latched data DLMSB is held until the next L channel data comes.

FIG. 7 is a specific circuit diagram of the C1 memory 1004. DSIDT is supplied as input data of a DFF with synchronization enable composed of a selector 1042 and a DFF 1043. The enable data provides LDAT0DD. However, when the enable data is logic "L", the data is latched, and when the enable data is logic "H", the data is held. Therefore, when LDAT0DD becomes logic “H”, the current DAT0DD becomes “H”.
SIDT, that is, the value of the C1 data is latched and thereafter held. The held data is output as DLC1.

FIG. 8 is a specific circuit diagram of the timing generator 1006. The internal operation will be briefly described, and the output signal will be particularly described. Reference numeral 1041 denotes a JK flip-flop (hereinafter, referred to as JKFF). The data excluding the MSB of the input data DSIDT converted into the folded binary code is supplied to the input terminal K, and the output terminal Q is held at the logic “H” by the logic “H” that appears first. Also, since the output is ORed with L26T, the output terminal Q is always held at the logic "H" at the timing of the 26th bit and subsequent bits of the L channel.
The data at the output terminal Q is referred to as LDAT1. LDAT
1D is LDAT1 delayed by one clock by SFCK, LDAT1DD is LDAT1 delayed by two clocks by SFCK, and LDAT1DDD is SFAT of LDAT1.
This is delayed by three clocks by CK. In addition, JKFF
1041 is initialized with NLO1T at the beginning of the L channel.

The inverted bit T1 or R24T immediately after the run length that is doubled from the DSR 13 is detected, and RSRT1 is held at logic "H". This RSRT1
Is delayed by SFCK to generate RSRT1D and RSRT1DD.

BITAD0 is initialized with NL01T and SF
This is the LSB of a 6-bit counter that counts up with CK. Therefore, it represents an odd number of bit slots. Also, the value of the 6-bit counter is decoded by a decoder, and L26 indicating the 26th slot of the L channel is displayed.
R indicating the 24th slot of the T and R channels
24T are output.

DSFEN is used to control the shift enable of the expansion means 1003. Since the operation is different between shift-in of DSIDT and shift-out of decompressed data, the timing signals are switched respectively.

At the time of shift-in of DSIDT, NLO1
T is logic "H", DLC1MSK is logic "L", B
If ITAD0 is logic "H", DSFEN outputs logic "H".

When the expanded data is shifted out, the data is further expanded by the logic of the stored data DLC1 in the C1 memory.
By performing an OR operation with 1, DSFEN outputs a logical "H". When the logic of DLC1 is logic “L”, RSRT
By ORing 1D, DSFEN outputs logic "H".

FIGS. 9A and 9B show the input unit 10 respectively.
01 is a specific circuit diagram of the output unit 1005. Although a detailed description is omitted, the reason why the output unit 1005 outputs the DFF through one stage is that a hazard is generated in the selector output, so that this is corrected and the output timing of the decompression means 1003 is adjusted to adjust the output timing. This is for output. Also, the JKFF in the figure generates fixed data “1000...” To be added to the LSB side of the compressed data.

The operation of the first embodiment described above will now be described with reference to a timing chart. 10 to 13 are diagrams for explaining input / output data of the decompression unit 1003 and timing processing of the timing generation unit 1006. FIG. 10 shows the case where the run length L1 is 0 and C1 = 1, FIG. 11 shows the case where the run length L1 is 10 and C1 = 1, and FIG. 12 shows the case where the run length L1 is 10 according to the run length and C1 of the input data. FIG. 13 is a timing chart when the run length L1 is 13 and C1 = 1. The input data DSIDT is a folded binary code, and data "0" continues in the run length L1 except for the polarity bit. Shifts input data from shift registers 1301 to 1314
Are sequentially shifted. DSR1 to DSR14 are internal output data of the shift registers 301 to 314. In the process of inputting to the expansion means 1003, after the initialization with the initialization pulse NLO1T, the LDAT generated by the timing generation unit 1006 according to the run length
The shift operation is controlled based on “1”. The inverted bit T1 and the remaining data D1 are shifted and input. It is DSFEN that directly controls the shift operation.

For example, in FIG. 12, the input data is MS
B and below, ten “0”, inverted bit T1 “1”, compression remainder data C1, remaining data D1 “AB...”
It is. When such data is input, the timing generation unit 1006 sets DSFEN to logic “H” for every three or more odd-numbered slots to remove the MSB. As a result, the decompression means 1003 is shifted and input for every three or more odd-numbered slots, and ten "0" s and inverted bits T1 are stored in the internal memory. Thereafter, the timing generation unit 1006 sets LDAT1 to logic "H" in synchronization with SFCK at the position of the inverted bit T1. The timing generation unit 1006 sets DSFEN to logic “L” at the timing of the compression remainder data C1.
The shift input of the expansion unit 1003 is prohibited. As a result, the decompression means 1003 skips the compression remainder data C1, and outputs the mantissa data D1 after the compression remainder data C1.
Is continuously shifted inward. Thus, a total of 14
Stores bits. Note that the C1 memory 1004 is an LDA
The data of the compressed remainder data C1 is stored internally using T1D to LDAT1DDD. Thus, the compressed data is stored.

Next, the process of expanding and extracting the stored compressed data at the data timing of the R channel will be described.

In FIG. 12, when the LRCK rises, the decompression means 1003 prepares the compressed data excluding the MSB data and the compression remainder data C1. The run length of the output is extended by intermittently extracting the compressed data and matching the output data timing. Therefore, in a data section corresponding to the run length L1, every other shift enable DSFEN is set to logic "H". Further, depending on the value of the compression remainder data C1, 1
Extends by the slot. These timing controls are performed by the DSFEN of the timing generation unit 1006. RSRT
1 is SF by either DSR13 or R24T
Set to logic "H" in synchronization with CK. That is, the timing generation unit 1006 sets the T1 of the DSR 13 to “1”.
Is detected, or at the fixed timing of R24T, which is the 24th slot of the R channel, RSRT1 is set to logic “H”. The output C1 of the C1 memory 1004 is "
If "0", DSFEN is masked using RSRT1D, which is a delay of RSRT1, and DSFEN is forced to logic "L" only during that time. In the case of FIG. 12, C1 = 0, which corresponds to this, so that the output run length is further extended by one slot.

Thereafter, the remaining data D1, ie, A
BC are sequentially output. The fixed data “1000...” Is applied to the blank part from the input part 1001.
The entire length is extended to 28 bits. Further, "0" for 4 bits is added to make 32 bits, and the output unit 1005 delays the output signal DAD by one clock at the output terminal 1804.
Output as AT. Since the fixed value “1000...” Is applied to the blank generated in the lower data after expansion, the data becomes the data closest to the center of the expression space of a certain exponent part range, and therefore, the bias of the parasitic offset is prevented. Thus, a smooth range transition can be performed, and the distortion factor can be substantially improved. The fixed value is "0111 ...
・ "Is exactly the same.

Next, FIG. 13 shows a case where the run length L1 is 13, but the operation is different from that of FIG. 12 in the following points. When the run length is large, LDAT1 is set to logic "H" at a fixed timing in order to terminate the run length. Therefore, L26T is generated by the timing generation unit 1006 and reflected on LDAT1. Therefore, the inverted bit T1
LDAT at L26T timing, regardless of presence or absence of
1 is set to logic "H". Further, RSRT1 is forcibly set to logic "H" at the timing of R24T, and a timing for masking DSFEN with the compressed remainder data C1 is created.
FIGS. 10 and 11 show the case where the run lengths are 0 and 10, however, the operation is the same as that described above, and a description thereof will be omitted. However, since C1 = 1, only the run length L1 is extended by a factor of two, and no additional extension by C1 is performed.

With respect to the compressed data obtained in this way, some examples of the code configuration and the characteristics of the code will be described.

FIG. 14A is a conceptual diagram showing the configuration of a run-length 1/2 compressed floating code used in the embodiment of the present invention, and FIG. 14B is a diagram showing a linear code (30 bits) converted to a run-length 1 code. / 2 compressed floating code (1
FIG. 9 is a diagram for explaining code conversion for compressing data to 6 bits. In the figure, the same symbols are given to the same parts as in the conventional example.

The procedure of compression (encoding) will be described first with reference to the drawings. The compressed continuous data Q1 is continuous data having a length of the run length L1 obtained by dividing the run length L0 of the continuous data Q0 by 2 and converting it into an integer. That is, L1 = int (L0 / 2). If the remainder term of the integer division is a compression remainder F1, then F1 = L0 mod 2.

The inversion bit T1 is an inversion bit for breaking the run of the compressed continuous data Q1. Compressed remainder data C
1 is a complement representation of the compression remainder F1. Further, the mantissa data D1 is upper partial data of the data D0.
The run-length 1/2 compressed floating code is arranged in the following order: polarity bit P, compressed continuous data Q1, inverted bit T1, compressed remainder data C1, and mantissa data D1.

Hereinafter, a case where the run length L0 is "0" to "28" will be described with reference to FIG.

When L0 = 0, L1 and F1 are as follows: L1 = int (0/2) = 0 F1 = 0 mod 2 = 0.

Since the run length L1 is "0", there is no compressed continuous data Q1. The compression remainder data C1 is “1”. The data D0 is 30 bits, and the upper 13 bits “ABCDEFGHIJKLM” are mantissa data D1.
It is. In the run-length 1/2 compressed floating code, the polarity bit P, the inverted bit T1, the compression remainder data C1, and the mantissa data D1 are arranged in this order, and "P11AB
CDEFGHHIJKLM ".

Similarly, the following is obtained. When L0 = 1, L1 = int (1/2) = 0 F1 = 1 mod 2 = 1, there is no compressed continuous data Q1, and there is no compressed residual data C1.
Is “0”. The upper 13 bits of data D0 “ABC
"DEFGHIJKLM" is the mantissa data D1. The run-length 1/2 compression floating code is "P10AB
CDEFGHHIJKLM ".

When L0 = 2, since L1 = int (2/2) = 1 F1 = 2 mod 2 = 0, the continuous data Q1 is "0" and the compression remainder data C1 is "1". The upper 12 bits “A” of data D0
"BCDEFGHIJKL" is the mantissa data D1. The run length 1/2 compression floating code is “P011
ABCDEFGHIJKL ".

When L0 = 3, since L1 = int (3/2) = 1 F1 = 3 mod 2 = 1, the continuous data Q1 is "0" and the compression remainder data C1 is "0". The upper 12 bits “A” of data D0
"BCDEFGHIJKL" is the mantissa data D1. The run-length 1/2 compression floating code is "P010
ABCDEFGHIJKL ".

When L0 = 20, continuous data Q1 is "000000000000" and compressed remainder data C1 is "1" from L1 = int (20/2) = 10 F1 = 20 mod 2 = 0. . The upper three bits “ABC” of the data D0 are the mantissa data D1. Therefore, the run length 1/2 compression floating code is "P
00000000000011ABC ”.

Further, when L0 = 28, L1 = int (28/2) = 14 F1 = 28 mod 2 = 0, and the continuous data Q1 is "0000000000000"
0 ", and the compressed remainder data C1 is" 1 ". There is no data D0 and no mantissa data D1. Therefore, the run length 1/2 compression floating code is "P00000
000000001 ”.

In this way, the linear code (30 bits)
To a run-length 1/2 compressed floating code (16 bits).

Next, the procedure of decompression (decoding) will be described. In the decoding procedure, the run length L1 is obtained from the compressed continuous data Q1 and the inverted bit T1 by removing the polarity bit P from the compressed data. Further, the compression remainder data C1 (1 bit) and the mantissa data D1 immediately after the inversion bit T1 are obtained. A compression remainder F1 obtained by inverting the compression remainder data C1 is obtained.

From these, the run length L0 of the continuous data Q0 of the original data is obtained from L0 = 2 * L1 + F1.

The continuous data Q0 is restored by connecting the length "0" of the run length L0. The inversion bit T0 is added after the continuous data Q0, and the mantissa data D1 is added after that. The polarity bit P is added to the head to be the original data. If the code length is less than W0, a fixed value is applied to the lower part of the mantissa data D1 to make the code length W0. The decoding process is performed according to this procedure.

Hereinafter, some cases of the run length L1 will be specifically described with reference to FIG.

When L1 = 0 and F1 = 0, since L0 = 2 * 0 + 0 = 0, there is no continuous data Q0. The mantissa data D1 is 13 bits and is “ABCDEFGHIJKLM”.
At this time, the original data includes a polarity bit P and an inverted bit T0.
And the mantissa data D1 to form “P1ABCDEF
GHIJKLM ************ ". Note that "*** ..." is a fixed value "011 ..."
Shall be allocated.

Similarly, when L1 = 10 and F1 = 0, since L0 = 2 * 10 + 0 = 20, the continuous data Q0 is "00000000000000".
00000000 ”and the mantissa data D1 is“ AB
C ". At this time, the original data is composed of the polarity bit P, the continuous data Q0, the inverted bit T0, and the mantissa data D1, and is referred to as “P000000000000000000”.
001ABC ****** ".

In this manner, the run length 1/2 compressed floating code (16 bits) is converted to the linear code (30 bits).
Bit) is decoded and decompressed.

The results summarized for all cases in the same manner as described above are shown in (Table 3).

[0070]

[Table 3]

In Table 3, the linear code (28 bits) is a folded binary code, and the floating code is a folded run-length 1/2 compressed floating code. The columns of run length L0, run length L1, and resolution are decimal numbers.

The expression accuracy, ie, the resolution, of the restored code obtained by decoding and expanding the compressed code is determined by the rounding accuracy of the linear code in the linear code, and varies depending on the run length L0. From Table 3, a precision of up to 28 to 15 bits can be obtained.

Here, the instantaneous S / N ratio in the case where a linear code is input and compression-encoded using a run-length 1/2 compression floating code, and this code is decoded and a decompressed code is output will be described. . However, for simplicity, the instantaneous S / N ratio is the improvement of the S / N ratio of the rectangular wave (about 2 dB).
Is omitted. The input level is based on the amplitude of the maximum sine wave that can be represented by a code (0 dB). The linear code "P11
11 ... "corresponds to this.

The range of the input level from 0 dB to -6 dB is "P1ABC..." By a linear code, as shown in Table 3.
More resolution is 15 bits. The quantization noise of the 15-bit data is -90 dB as -6 dB per bit. Therefore, the instantaneous S / N ratio becomes 90 dB to 84 dB in the range of the input level from 0 dB to -6 dB.

In the input level range of -6 dB to -18 dB, "P01ABC ..." or "P0
01ABC ... "and the resolution is 16 from (Table 3).
Is a bit. The quantization noise of 16-bit data is -9
6 dB, the instantaneous S / N ratio is 90 dB to 78
dB.

In the input level range of −18 dB to −30 dB, the code is “P0001ABC...” Or “P00001ABC...”, And the resolution is 17 bits according to (Table 3). Since the quantization noise of 17-bit data is -102 dB, the instantaneous S / N ratio is 84 dB.
B to 72 dB.

Similarly, an instantaneous S / N ratio is obtained in an input level region up to -180 dB. FIG. 16 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run-length 1/2 compressed floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve X1 shown in the figure is a run length 1/2 shown in (Table 3).
It shows the instantaneous S / N ratio of the compressed floating code. As shown in the figure, the characteristic curve X1 has an input level of 0 dB to-
Hearing detection limit of instantaneous S / N ratio in the range of 96 dB 48 dB
Is almost exceeded.

As compared with the conventional linear code (16 bits), the instantaneous S /
N-ratio improvement is achieved. The improvement of the instantaneous S / N ratio works over a wide range of input levels from -18 dB to -180 dB. Instantaneous S / N in the range of input level 0 dB to -6 dB
Although the ratio deteriorates, the deterioration is at most 6 dB and still 90 d
It has an instantaneous S / N ratio of B to 84 dB. Since this area is reserved as a margin and is usually in a range that is hardly used, there is no problem at all.

In comparison with the broken line code (16 bits) shown in the characteristic curve Z2 of FIG.
There is an improvement of 6 dB in the range from dB to -12 dB, and an improvement of 18 dB is obtained at -96 dB.

As described above, even if a signal of a very small level is amplified, the quantization noise can be made smaller than the hearing detection limit over a wide range up to the input level of -96 dB.
Therefore, the recording level can be set while securing sufficient headroom, and it can be arbitrarily amplified in later editing. Further, in order to improve the problem of the quantization noise of the eigen spectrum generated in a signal of a minute level, it is possible to eliminate processing such as adding white noise (dither) to disperse the noise spectrum.

In the current technology, the input level is 0 dB to -1.
Although it is difficult to amplify a wide range of signals of 80 dB or to digitize them with an AD converter, the effects of the present invention will be maximized due to the future development of functional elements and circuit technology that utilize high-temperature superconductivity. become able to. (Table 3)
Let us consider the increase characteristic of the run length 1/2 compression floating code. In the embodiment, since the compression remainder data C1 is a complement of the compression remainder F1, the numerical value of the upper range is always larger than the lower range at the boundary of the range. Therefore, this code has a monotonically increasing characteristic. Even if the compressed data is erroneously reproduced as a linear code (16 bits), a monotonically increasing characteristic is advantageous because level inversion and jump do not occur. This action is based on the fact that the compression remainder data C1 is the complement of the compression remainder F1, but it need not always be the complement and may be another expression.

As described above, it is difficult with the current technology to amplify a signal in a wide range from an input level of 0 dB to -180 dB or to digitize the signal with an AD converter. Therefore, when it is not possible to prepare a 30-bit linear code, the linear code may be shortened as in the first embodiment. Table 4 shows a code decoder for compressing and expanding a linear code (28 bits) into a run-length 1/2 compressed floating code (16 bits).

[0083]

[Table 4]

In this case, the run length L0 is cut off at a maximum of 26. When the run length L0 = 26, the inverted bit T
O is omitted, and the remaining data is set to D0. The encoding is the same, except that the compression remainder data C1 is omitted and the mantissa data D1, that is, D0 is arranged instead. Due to the termination of the run length L0, the instantaneous S / N ratio characteristics are changed as shown in FIG.
6 is the characteristic curve X2. Input level -162d
The range from B to 0 dB is the same as X1 in FIG.

Further, in a similar manner, the linear code may be shortened to 24 bits. Table 5 shows a linear code (24 bits) converted to a run-length 1/2 compressed floating code (1 bit).
(6 bits).

[0086]

[Table 5]

In this case, the run length L0 is set to a maximum of “1”.
8 ”. When the run length L0 = 18, the inverted bit T0 is omitted, and the remaining data is set to D0. The encoding is the same, but the run length L1 is known to have a maximum value of "9", so the inverted bit T1 may be anything. Further, the compression remainder data C1 is omitted, and instead, mantissa data D1, that is, D0 is arranged. The instantaneous S / N is obtained by terminating the run length L0.
The specific characteristic is a characteristic curve X3 in FIG. The input level is the same as X1 in the figure in the range of −114 dB to 0 dB. With any of the characteristic curves X1, X2, and X3 described above, the hearing detection limit of the instantaneous S / N ratio can be almost cleared in the range of the input level from 0 dB to -96 dB.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 15A is a conceptual diagram showing a configuration of a run-length 1/4 compressed floating code according to the second embodiment of the present invention, and FIG. 15B is a diagram showing a specific example for explaining a conversion process. It is. In the figure,
The same symbols are given to the same parts as in the conventional example.

The procedure of compression (encoding) will be described first with reference to the drawings. The second embodiment uses a linear code (32
Bit) into a run-length 1/4 compressed floating code (16 bits).

The compressed continuous data Q1 is continuous data having a length of the run length L1 obtained by dividing the run length L0 of the continuous data Q0 by "4" and converting it into an integer.

L1 = int (L0 / 4) If the remainder term of the integer division is a compression remainder F1, then F1 = L0 mod 4

The inversion bit T1 is an inversion bit for breaking the run length of the compressed continuous data Q1. The compression remainder data C1 is a complement representation of the compression remainder F1.
The mantissa data D1 is the partial data on the upper side of the data D0. The run-length 1/4 compressed floating code includes a polarity bit P, compressed continuous data Q1, and an inverted bit T.
1, compressed remainder data C1, and mantissa data D1.

Hereinafter, a case where the run length L0 is "0" to "28" will be described with reference to FIG.

When L0 = 0, since L1 = int (0/4) = 0 F1 = 0 mod 4 = 0, the run length L1 is "0", and there is no compressed continuous data Q1. The compression remainder data C1 is “11”. The data D0 is 30 bits, of which the upper 12 bits “ABCDEFGHIJKL” are the mantissa data D1. The run-length 1/4 compressed floating code is obtained by arranging the polarity bit P, the inverted bit T1, the compression remainder data C1, and the mantissa data D1 in this order, and setting "P111 ABC
DEFGHIJKL ".

Similarly, when L0 = 1, since L1 = int (1/4) = 0 F1 = 1 mod 4 = 1, there is no compressed continuous data Q1, and there is no compressed residual data C1.
Is “10”. The upper 12 bits “AB” of data D0
"CDEFGHIJKL" is the mantissa data D1. Run-length 1/4 compression floating code is "P110A
BCDEFGHIJKL ".

When L0 = 3, since L1 = int (3/4) = 0 F1 = 3 mod 4 = 3, the continuous data Q1 is "0" and the compression remainder data C1 is "00". The upper 12 bits “ABCDEFGHIJKL” of the data D0 are the mantissa data D1. The run-length 1/4 compression floating code is "P
100ABCDEFGHIJKL ".

When L0 = 20, L1 = int (20/4) = 5 F1 = 20 mod 4 = 0, the continuous data Q1 is "00000", and the compressed remainder data C1 is "11". . The upper 7 bits “ABCDEFG” of the data D0 are the mantissa data D1. Therefore, the run-length 1/4 compression floating code is "P
00000111ABCDEFG ".

When L0 = 23, L1 = int (23/4) = 5 F1 = 23 mod 4 = 3, so that the continuous data Q1 is "00000" and the compressed remainder data C1 is "00". . The upper 7 bits “ABCDEFG” of the data D0 are the mantissa data D1. Therefore, the run-length 1/4 compression floating code is "P
00000100ABCDEFG ”.

Thus, the linear code (32 bits)
To a run-length 1/4 compressed floating code (16 bits).

Next, the procedure of decompression (decoding) will be described. In the decoding procedure, the run length L1 is obtained from the compressed continuous data Q1 and the inverted bit T1 by removing the polarity bit P from the compressed data. Further, the compression remainder data C1 (2 bits) and the mantissa data D1 immediately after the inverted bit T1 are obtained. A compression remainder F1 obtained by inverting the compression remainder data C1 is obtained.

From these, the run length L0 of the continuous data Q0 of the original data is obtained from L0 = 4 * L1 + F1. The continuous data Q0 is restored by connecting the length "0" of the run length L0. The inversion bit T0 is added after the continuous data Q0, and the mantissa data D1 is added after that. The polarity bit P is added to the head to be the original data. If the code length is less than W0, a fixed value is applied to the lower part of the mantissa data D1 to make the code length W0. The decoding process is performed according to this procedure.

The decoding apparatus is the same as the first embodiment except for the following points. The difference is that the compressed remainder data C1 is 2 bits at the time of shift input, and during that time, DSFEN is set to logic "L" to inhibit shift input.
004 for 2 bits, and a DS for controlling the shift register of the expanded output 1003 at the time of expanded output.
The run length L1 is expanded by a factor of four by setting FEN to logic "H" once every four clocks, and the output run length is extended to 0, 1, or 4 in accordance with the values of the four types of compressed remainder data C1. This is the point of control in four ways of 2 and 3. The circuit of the timing generator 1006 is changed so as to satisfy these. Since the specific circuit can be easily derived from the first embodiment, the description is omitted.

Hereinafter, some cases of the run length L1 will be specifically described with reference to FIG.

When L1 = 0 and F1 = 0, since L0 = 4 * 0 + 0 = 0, there is no continuous data Q0. The mantissa data D1 is 12 bits and is "ABCDEFGHIJKL". At this time, as the original data, the polarity bit P, the inverted bit T0, and the mantissa data D1 are arranged, and “P1ABCDEFG
HIJKL ******** ".
Note that “***...” Satisfies the fixed value “1000.

Similarly, when L1 = 5 and F1 = 0, since L0 = 4 * 5 + 0 = 20, the continuous data Q0 is "00000000000000".
00000000 ”and the mantissa data D1 is“ AB
CDEFG ”. At this time, the original data is composed of the polarity bit P, the continuous data Q0, the inverted bit T0, and the mantissa data D1, and is referred to as “P00000000000000”.
0000001ABCDEFG *** ".

In this way, the run length 1/4 compressed floating code (16 bits) is converted to the linear code (32 bits).
Bit) is decoded and decompressed.

The results summarized for all cases in the same manner as described above are shown in (Table 6).

[0108]

[Table 6]

From Table 6, it can be seen that according to the present embodiment, a maximum of 32
Bit to 14 bit precision is obtained.

Here, the instantaneous S / N ratio in the case where a linear code is input, compression-encoded using a run-length 1/4 compressed floating code, and this code is decoded and a decompressed code is output is described. .

The range of input levels from 0 dB to -6 dB is "P1ABC..." By a linear code, as shown in Table 6.
More resolution is 14 bits. The quantization noise of 14-bit data is -84 dB, assuming -6 dB per bit. Therefore, the instantaneous S / N ratio becomes 84 dB to 78 dB in the range of the input level from 0 dB to -6 dB.

In the input level range of -6 dB to -12 dB, the linear code is "P01ABC ...", and the resolution is 15 bits according to (Table 6). Since the quantization noise of the 15-bit data is -90 dB, the instantaneous S / N ratio is 84 dB to 78 dB.

In the input level range of -12 dB to -18 dB, a linear code is "P001ABC ..."
According to Table 6, the resolution is 16 bits. Since the quantization noise of 16-bit data is -96 dB, the instantaneous S /
The N ratio is 84 dB to 78 dB.

In the input level range from -18 dB to -30 dB, the code is "P0001ABC..." Or "P00001ABC...", And the resolution is 17 bits according to (Table 6). Since the quantization noise of 17-bit data is -102 dB, the instantaneous S / N ratio is 84 dB.
B to 72 dB.

Similarly, an instantaneous S / N ratio is obtained in an input level region up to -180 dB. FIG. 17 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run-length 1/4 compressed floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve Y1 in the figure is a run length 1/4 shown in (Table 6).
It shows the instantaneous S / N ratio of the compressed floating code. The characteristic curve Y1 clearly shows that the input level is 0 dB.
In the range of from -96 dB, the instantaneous S / N ratio exceeds the auditory detection limit of 48 dB.

Compared with the conventional linear code (16 bits), the instantaneous S / N of about 60 dB at the input level of -96 dB
A ratio improvement is achieved. The improvement of the instantaneous signal-to-noise ratio works over a wide range of input levels from -18 dB to -196 dB. Instantaneous S / in the range of input level 0 dB to -12 dB
Although the N ratio deteriorates, the deterioration is at most 12 dB.
It has an instantaneous S / N ratio of 84 dB to 78 dB. Since this area is a range that is not usually used much as a margin, there is no problem at all.

In comparison with the broken line code (16 bits) shown in the characteristic curve Z2 of FIG.
There is an improvement in the range from 54 dB to -196 dB, and -96
In dB, an improvement of 36 dB is obtained.

As described above, according to the second embodiment, even if a signal having an input level of -144 dB smaller than that of the first embodiment is amplified, the auditory detection of quantization noise is completely eliminated. Therefore, the recording level can be set while securing sufficient headroom, and it can be arbitrarily amplified in later editing.

Table 7 shows a linear code (29 bits) converted to a run-length 1/4 compressed floating code (16 bits).
This shows a code decoding method for compressing and expanding the data.

[0120]

[Table 7]

In this case, the run length L0 is set to a maximum of “20”.
Terminate with When the run length L0 = 20, the inversion bit T0 is omitted, and the remaining data is set to D0. The encoding is the same, but the run-length L1 is known to have a maximum value of "5", so the inversion bit T1 is omitted. Further, the compression remainder data C1 may be anything. Due to the termination of the run length L0, the instantaneous S / N ratio characteristic becomes the characteristic curve Y2 in FIG. Input level -1
The range from 26 dB to 0 dB is the same as Y1 in FIG.

Further, the linear code may be shortened to 26 bits. Table 8 shows a linear code (26 bits) converted to a run length 1/4 compressed floating code (1 bit).
(6 bits).

[0123]

[Table 8]

In this case, the run length L0 is set to a maximum of “1”.
6 ”. When the run length L0 = 16, the inverted bit T0 is omitted, and the remaining data is set to D0. The encoding is the same, but since the maximum value of the run length L1 is known to be "4", the inversion bit T1 is omitted. Further, the compression remainder data C1 may be anything. The run-off of the run length L0 results in an instantaneous S /
The N ratio characteristic is a characteristic curve Y3 in FIG. The input level is the same as Y1 in the range from -102 dB to 0 dB. With any of the characteristic curves Y1, Y2, and Y3 described above, the auditory detection limit of the instantaneous S / N ratio can be completely cleared within the input level range of 0 dB to -96 dB.

Next, a third embodiment of the present invention will be described. The third embodiment is a coding method for compressing and expanding a linear code (24 bits) into a run length 1/4 compressed floating code (8 bits). That is, the number of bits of the code of the second embodiment is changed. Therefore, the procedure of compression (encoding) and decompression (decoding) and the configuration of the decoding device are the same as those in the second embodiment, and a description thereof will be omitted.

Table 9 summarizes the results for all exponents, that is, ranges.

[0127]

[Table 9]

From Table 9, it can be seen that according to the present embodiment, a maximum of 24
Bit to 6 bit precision is obtained.

FIG. 18 shows the run length 1/3 of the third embodiment.
FIG. 4 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a 4-compressed floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve V1 in the figure represents the instantaneous S / N ratio of the run length 1/4 compressed floating code shown in (Table 9).
As is clear from the figure, the characteristic curve Y1 shows a substantially flat characteristic of the instantaneous S / N ratio in a much wider input level range than the linear code (8 bits). In this state, the instant S
Although it is less than the auditory detection limit of 48 dB of the / N ratio, a wide input level range and high resolution can be utilized by combining with a difference code or the like. It can be used for redundancy compression using the correlation between samples of image data.

In the first to third embodiments described above, the linear code is a folded binary code.
Other linear codes, such as complementary codes and offset binary codes, can be applied in exactly the same way simply by converting each other or changing a predetermined logical value. Also, the case where n is only “2” and “4” has been described, but n may be any integer as long as it is “2 or more”. In this case, since the number in the case of the compression remainder changes according to the value of n,
It goes without saying that the word length of the compression remainder data may be changed and the shift enable control may be changed. In the embodiment, the circuit configuration uses the shift register. However, the circuit configuration may be configured by hardware and software of a DSP (Digital Signal Processor) that performs similar data conversion.

[0131]

As described above, the present invention is an apparatus for receiving and decoding a transmitted run-length 1 / n compressed floating code. Since the run-length 1 / n compressed floating code forms an exponent part, that is, a range, with the compressed continuous data, the inverted bit, and the compressed remainder data, the exponent part, that is, the range, changes according to the run length of the original data. When the run length of the original data is small, the exponent part, that is, the range, is represented by a small number of bits. When the run length is large, the bit number is further allocated, and the exponent part, that is, the range, is represented by a large number of bits. Since the word length of the entire code is fixed, the number of bits of the mantissa changes according to the run length. By these actions, the range expression space of the compression code output from the output unit is expanded, and at the same time, the expression accuracy can be improved. The present invention provides an input section for inputting compressed data, a C1 memory for storing compressed remainder data C1, a run length of Q1 expanded by n times, and continuous data having a length corresponding to the value of the C1 memory; Bit T0 for breaking the continuity of data, decompression means for adding mantissa data D1, and an output unit for reading out continuous data Q0, inversion bit T0 and mantissa data D0 from the decompression means and outputting decompressed data, MSB to store bit
Latch, input means for input distribution, output means for multiplexing odd data, decompression means for adding fixed data to the lower part of compressed data, or decompression means for adding run length according to the value of compression residual data C1. Prepare.

Thus, the input section supplies the received compressed data to the C1 memory and the decompression means. The C1 memory stores and retains the extracted compressed remainder data C1, supplies this data to the decompression means, and the decompression means receives the data. The compressed data is expanded by n times, the run length is further extended based on the compressed remainder data input from the C1 memory, the inverted bit is added, and the data to which the mantissa is added is supplied to the output unit. The original data restored by decompression is taken out. Since the decoded original data keeps both the accuracy and the input level range at or above the predetermined characteristics, especially when the present invention is applied to a digital recording / reproducing apparatus for business editing, mixing and dubbing with amplification and attenuation are repeated. , No quantization noise is detected by the auditory sense, and the input level 0
In addition, it is possible to provide a decoding device that secures the auditory detection limit of the instantaneous S / N ratio of about 48 dB or more in a wide range from -96 dB.

Further, by taking the absolute value of the input data using the MSB latch and performing return binary coding, it is possible to cope with positive and negative polarities and simplify the hardware.

By applying a fixed value “100...” Or “011...” To the blanks generated in the lower data after expansion, offset bias that is parasitic in the exponent range is prevented, and the distortion rate is improved. it can.

In addition, high-speed continuous processing can be performed by pipeline processing by the multiplexing selector of the input distribution and output means.

[Brief description of the drawings]

FIG. 1 shows a run length 1 according to a first embodiment of the present invention.
Schematic block diagram showing the configuration of a decoding device for a 1/2 compressed floating code

FIG. 2 is a schematic operation timing chart in the first embodiment.

FIG. 3 is a block diagram of a decoding device that expands an L channel and an R channel.

FIG. 4 is a specific circuit diagram of the expansion means 1003 in FIG.

FIG. 5 shows shift registers 1301 to 1303 in FIG.
14 internal circuit diagram

FIG. 6 is a specific circuit diagram of the MSB memory 1002 in FIG.

FIG. 7 is a specific circuit diagram of a C1 memory 1004 in FIG. 1;

8 is a specific circuit diagram of a timing generation unit 1006 in FIG.

9A is a specific circuit diagram of an input unit 1001 in FIG. 1. FIG. 9B is a specific circuit diagram of an output unit 1005 in FIG.

10 is a waveform chart for explaining input / output data of a decompression unit 1003 and timing processing of a timing generation unit 1006 in FIG.

11 is a waveform chart for explaining input / output data of the decompression means 1003 and timing processing of the timing generation unit 1006 in FIG.

FIG. 12 is a waveform chart for explaining input / output data of a decompression unit 1003 and timing processing of a timing generation unit 1006 in FIG.

FIG. 13 is a waveform chart for explaining input / output data of a decompression unit 1003 and timing processing of a timing generation unit 1006 in FIG.

14A is a conceptual diagram showing a configuration of a run-length 1/2 compressed floating code according to the first embodiment of the present invention; FIG. 14B is an explanatory diagram for explaining the conversion processing in the same manner;

FIG. 15A is a conceptual diagram showing the configuration of a run-length 1/4 compressed floating code according to the second embodiment of the present invention. FIG. 15B is an explanatory diagram showing a specific example for explaining the conversion process.

FIG. 16 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run-length 1/2 compressed floating code according to the first embodiment of the present invention.

FIG. 17 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run-length 1/4 compressed floating code according to the second embodiment of the present invention.

FIG. 18 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run-length 1/4 compressed floating code in the third embodiment of the present invention.

19A is a conceptual diagram showing a configuration of a conventional 13-line code (12 bits), and FIG. 19B is an explanatory diagram showing a specific example for explaining a conversion method in the same manner.

FIG. 20 is a characteristic diagram of a restored code obtained by decoding and expanding a conventional compressed code using a broken line code.

[Explanation of symbols]

 1001 input unit 1002 MSB memory 1003 decompression means 1004 C1 memory 1005 output unit 1006 timing generation unit P polarity bit Q0 continuous data Q1 compressed continuous data Q2 range data L0 run length of continuous data Q0 L1 run length of compressed continuous data Q1 L2 range data Run length of Q2 T0, T1 Inversion bit D0 Data of remaining part D1, D2 Mantissa data W0 Code length of original data W1, W2 Code length of compressed data

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/24 H03M 7/50

Claims (6)

(57) [Claims] 1. A compressed continuous data Q1 in which bits of a predetermined logic continue at a high order, an inverted bit T1 for breaking the continuity of the compressed continuous data Q1, a compressed residual data C1 representing a residual F1 generated when compressing a run length, and An input unit for inputting compressed data constituted by mantissa data D1, a C1 memory for storing the compressed remainder data C1, a run length of Q1 expanded by n times, and a length corresponding to the value of the C1 memory Decompression means for adding continuous data, adding an inverted bit T0 for breaking the continuity of Q0, and subsequently adding the mantissa data D1, and reading the continuous data Q0, inverted bit T0 and mantissa data D0 from the decompression means Decoding a run-length 1 / n compressed floating code, comprising: an output unit for outputting decompressed data. apparatus. However, the run length of the continuous data Q0 is L0,
When the run length of 1 is L1 and the remainder obtained from the compressed remainder data C1 is F1, and n is an integer of 2 or more, L0 = L1 * n + F1 D0 = D1. 2. Compressed continuous data Q having a polarity bit P, and bits of a predetermined logic continuing at a higher order except for the polarity bit P.
1. an inverting bit T1 for breaking the continuity of the compressed continuous data Q1, an input section for inputting compressed data constituted by compressed remainder data C1 and mantissa data D1 representing a remainder F1 generated when compressing a run length; An MSB memory for storing the bit P, a C1 memory for storing the compressed remainder data C1, a run length of the Q1 is expanded by n times, and continuous data having a length corresponding to the value of the C1 memory is added; Expansion means for adding an inverted bit T0 for breaking the continuity of Q0 and subsequently adding the mantissa data D1; read polarity bit P from the MSB memory; and output continuous data Q0, inverted bit T0 and mantissa data from the expansion means. An output unit for reading out D0 and outputting decompressed data. A decoding device for compressed floating codes. However, the continuous data Q
When the run length of 0 is L0, the run length of the compressed continuous data Q1 is L1, the remainder obtained from the compressed remainder data C1 is F1, and n is an integer of 2 or more, L0 = L1 * n + F1 D0 = D1. 3. The decompression means adds a fixed value “1” to the lower part of the data D0 so that the decoded linear code has a predetermined code length W0.
00 ... "or" 011 ... "or" 000.
3. The decoding device for run-length 1 / n compressed floating codes according to claim 1 or 2, wherein ".." or "111..." Is added or lower bits are deleted. 4. The decompression means is constituted by a shift register with a shift enable function, masks the shift input only for the compressed remainder data C1, shifts the mantissa data to the left, and sequentially stores them inside. By enabling the output shift once every n times for the part,
3. The decoding apparatus for a run-length 1 / n compressed floating code according to claim 1, wherein the output run-length is expanded and output substantially n times. 5. The decompression means is constituted by a shift register with a shift enable function, and only the portion of the compression remainder data C1 is masked by the shift input, the mantissa data is left-justified, and stored sequentially inside. By enabling the output shift once every n times for the part,
While extending the output run length substantially n times,
3. The run-length 1 / n compressed floating code according to claim 1, wherein run lengths having different lengths are further expanded and expanded according to the value of the compressed remainder data C1 stored in the C1 memory. Decoding device. 6. A decoding device A for alternately performing input processing and decompression processing for odd-numbered input data, a decoding apparatus B for performing input processing and decompression processing for even-numbered input data alternately, and an output of the decoding apparatus A. 3. The decoding of the run-length 1 / n compressed floating code according to claim 1, wherein a selector for multiplexing data and output data of said decoding device B is provided, and continuous odd output data is output from said selector. apparatus.