JP3093083B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for performing an analog-to-digital conversion of a signal continuously generated at a controllable timing, and for example, to an analog-to-digital conversion in an active distance measuring apparatus used for auto-focusing of a camera. Related to the device.

[0002]

2. Description of the Related Art In active autofocus of a camera, infrared light from a light emitting diode is emitted from a camera to a subject, and is emitted by a lens placed at a certain distance (a so-called base length) from a light emitting unit. Light is captured on an element called a PSD (Position Sensitive Diode), converted into an electric signal, and the signal is amplified and calculated to calculate the distance. However, the light that can be reflected and captured by a lens is Since it is very small, the electric signal is also very small and easily buried in noise.
For this reason, attempts have been made to improve the effective S / N ratio by averaging the signals by emitting light a plurality of times. In an analog-to-digital converter that handles such signals, an analog-to-digital converter of an integral type, particularly a so-called double integral type, is used to increase resolution and reduce noise. In this case, in the digital averaging method in which a double integration type analog-to-digital converter is used for each light emission and digital averaging is performed, the clock must be made very fast or the repetition time must be increased in order to increase the resolution. Is required. However, the clock cannot be made too fast due to the operation speed of the circuit, and increasing the repetition time is not preferable because the distance measurement time becomes excessively long. Therefore, after performing the integration corresponding to the first integration in the double integration method with the first signal, instead of immediately performing the inverse integration, the integration voltage is held as it is and the integration corresponds to the first integration for each signal. After performing the integration, the second integration (inverse integration), which is called a double integration method, is performed after the last signal, and the time required to return to the original voltage by the inverse integration is measured. In other words, analog averaging has been proposed.

[0003]

However, in the method based on analog averaging, the amplitude per LSB (least significant bit) is small, and errors are likely to occur due to noise. Also, while the digital averaging method requires each time, this method requires only one time, but it takes time to perform analog-to-digital conversion at the end. Furthermore, when each signal is generated, if just a large noise is generated, the accuracy of the whole may be greatly deteriorated due to one time.

[0004]

A / D conversion is performed with a small resolution each time a signal is generated, and a voltage corresponding to a quantization error is carried over as an analog quantity. Also,
The digital value of the A / D conversion performed every time a signal is generated is stored, and finally, data significantly different from the average value is removed and averaged.

[0005]

For example, if the light emission is performed 16 times, one resolution a
Even if it is a bit, a resolution equivalent to 4 + a bits can be obtained by adding. Further, since the amount corresponding to the quantization error for each time is carried over to the next A / D conversion every time as an analog amount, the quantization error as a whole is 1 LSB or less in 4 + a bits. Further, an accurate measurement result can be obtained by eliminating the influence of data largely deviated due to noise. At this time, of course, the next value carried over in analog form is an error. For example, if the removed data is for one time, this error is only an error of 1 LSB or less, so even if the original quantization error is added, This is 2 LSB, and the maximum number of occurrences when the analog amount is not carried over while leaving only the digital data each time is 1 ×
It is much more advantageous than the LSB quantization error and yields much better results than simply averaging and not performing operations to remove such singular data.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an electric circuit diagram of an analog-to-digital converter according to an embodiment of the present invention.
0, SFF0 are JK flip-flops, CFF1 to CF
Fm, SFF1 to SFFn are T flip-flops, G1
G1 to G7 are gates (logic symbols are MIL expressions), OP1 and OP
2 is an operational amplifier (op amp) (OP2 is used as a comparator during comparison), R1 to R10 are resistors, Q1
Q8 indicates a transistor, and I1 indicates a sink current source.

The analog-to-digital converter shown in FIG.
This is an example of a circuit that operates as an A / D converter corresponding to a high resolution according to an average value of a repeatedly input signal by repeating with seven stages of resolution (less than 3 bits) each time. In the figure, S0 is an original vibration generated by an oscillator (not shown). Flip-flops SFF0 to SF
Fn is a circuit for sequence control,
This circuit reads the input and determines the timing for performing the first integration. The output of the gate G6 becomes (the polarity is inverted) as shown at S2 in the timing chart of FIG. First, since the transistor Q5 is turned off at the timing of S2, the collector current of the transistor Q4 becomes a current proportional to the input. At this timing, the transistor Q8 outputs the initialization signal I.D. Since the transistor Q7 is turned off at S, the transistor Q7 is also turned off, and the feedback loop of the initial setting which sets the value of the capacitor C1 to the divided voltage value of the resistors R6 and R7 is broken. Therefore, the current of the transistor Q4 flows out of the capacitor C1. Assuming that the output of the operational amplifier OP2 is H when S2 becomes L, S1 becomes H and the transistor Q3 is turned off, so that the transistor Q3 inverts the current source I1.
The current mirror circuit composed of Q1 and Q2 operates, charging of the capacitor C1 starts again, and the voltage of the capacitor C1 rises again. After this voltage reaches the initially set value, S1 goes low again at the first falling edge of the clock, and reverse charging stops. At this time, the inverse integration is performed by a multiple of the clock, so if the first integrated voltage does not exactly match the multiple of the voltage per clock, the voltage corresponds to one clock and a fraction. The voltage which is obtained by subtracting the voltage is further increased from the original initially set voltage. This voltage will be carried over to the next integration in this state. Next, the second integration is performed from B in S2 of the timing chart of FIG. Then, as in the first time, the second integration is performed again, and the fraction is again carried over as the voltage of the capacitor C1. In this manner, the integration is repeated (2 (n−3) −1) times, and at this time, the digital amount corresponding to the sum total of the integration amount of the second integration is integrated into CFF0 to CFFm and counted. This value may be taken out in parallel as the output of these flip-flops, or these flip-flops may be converted into a shift register and taken out serially. As a matter of course, a method of adding a value each time by a microcomputer without performing a hardware operation in this way may be used. With such a method, the singular data described in claim 2 can be easily removed. Since the software processing by the microcomputer is widely used, it is omitted from the embodiment. As described above, according to the present apparatus, a digital signal corresponding to an average value of an analog signal generated a plurality of times can be obtained with a high resolution as a whole even though the resolution per one time is small.

[0009]

The resolution (number of bits) per operation is small, but a high resolution is obtained as a whole and the pause time between signal intervals is effectively used, so that the time required for conversion as a whole can be reduced. Even if the resolution is the same, 1
Since the amplitude with respect to the LSB is large, it is also strong against noise jumping into the input of the comparator.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of an analog-to-digital converter according to one embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment.

[Explanation of symbols]

JKFF1, CFF0, SFF0... JK flip-flops CFF1 to CFFm, SFF1 to SFFn... T flip-flops G1 to G7... R1 to R10 resistors Q1 to Q8 transistors I1 sink current sources OUT0, OUT1, OUT2, OUT3,.
Output of F0, CFF1, ...

Claims (2)

(57) [Claims] 1. An analog-to-digital converter for converting an average value of an analog signal generated continuously a plurality of times at a fixed timing by a clock pulse into a digital signal.
Means for initially setting the integrated voltage of the capacitor to a fixed reference value before the signal is input, and integrating the capacitor for a fixed time each time with a current proportional to the signal value each time a signal is generated. Means to perform and the time between the signal and the next signal except for the last signal, and for the last signal from the time when the integrated voltage exceeds the reference voltage after the signal is generated until the first clock is generated Means for holding the voltage at the end of the inverse integration until the integration is performed after the completion of the inverse integration and also at the timing of the next signal, and
An analog-to-digital converter having means for measuring the time during which the inverse integration is performed, and means for calculating the sum of the respective inverse integration times. 2. A device for monitoring and storing a digital value corresponding to an inverse integration time for each inverse integration is provided, and one or a plurality of values which are extremely different from an average value after calculation from among the digital values are provided. 2. The analog-to-digital converter according to claim 1, wherein the removed average value is calculated and used as an output value for control.