JP3094516B2 - Retry method of information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a retry method for an information processing apparatus, and more particularly to a retry method for an information processing apparatus when a mechanical error or a logical illegal event occurs.

[0002]

2. Description of the Related Art Conventionally, in a data processing apparatus, when a mechanical error or a logical illegal event occurs, the processing is retried.

FIG. 2 is a block diagram showing an example of this type of conventional information processing apparatus, which comprises a processing circuit 201 and an external resource 205 such as a main storage device. It is assumed that the information processing apparatus shown in FIG. 2 extracts a stored program according to the value of the instruction counter, controls an arithmetic function according to the content thereof, and executes processing.

A processing circuit 201 includes an arithmetic circuit 202 for performing arithmetic processing and internal resources 2 such as arithmetic registers and memories.
03, an input / output terminal 204 connecting the processing circuit 201 and the external resource 205, an arithmetic circuit 202 and the external resource 205
A mechanical error detecting circuit 206 for detecting a mechanical error such as a parity error of a signal exchanged with the logical device; a logical fraud detecting circuit 207 for detecting that a logically illegal process has been performed; Control of circuit 202, internal resources 203
And a control circuit 208 for updating and the like.

Next, the operation of FIG. 2 will be described.

When the mechanical error detection circuit 206 or the logical error detection circuit 207 detects a mechanical error or a logical error event while the processing is being performed by the processing circuit 201,
This is notified to the control circuit 208.

The control circuit 208 includes a mechanical error detection circuit 20
6 is often intermittent,
First, the arithmetic circuit 202 is stopped, and then the internal resources 2
03 to the state at the appropriate time (eg, checkpoint), and then
The arithmetic circuit 202 is retried the processing (performs the same processing using the same data).

When a notification is received from the logical misconduct detection circuit 207, the arithmetic circuit 202 is first stopped, and then the state of some registers included in the internal resource 203 is returned to the state at an appropriate time. . Then, the internal resources 203
A part of the data in the data is exchanged, and the arithmetic circuit 202 restarts the processing (the same processing is performed using different data)
Or return all or part of the internal resources 203 to a state at an appropriate point in time, and cause the arithmetic circuit 202 to execute another process.

As described above, in order to retry and restart the processing, the state of some registers in the internal resource 203 must be set to an appropriate state.
If it is updated, it becomes difficult or impossible to retry and restart. Save the register contents to another location,
At the time of occurrence of a mechanical error or a logical illegal event, measures are taken to return the state of the register to an earlier state by using the saved information, and to delay updating of the register as much as possible.

FIG. 3 shows a conventional circuit in which a processing error is dealt with by duplicating processing circuits 301 and 302 having the same configuration as the processing circuit 201 shown in FIG. FIG. 2 is a block diagram illustrating an information processing apparatus, in which processing circuits 301 and 302 include external resources 303;
Is shared.

That is, the information processing apparatus shown in FIG. 3 has one of the two processing circuits 301 and 302 (for example, the processing circuit 3).
01), the processing circuit 301 in which the mechanical error is detected is disconnected, or the state of the internal resources of the processing circuit 302 is transferred to the processing circuit 301 to restart the processing. To deal with mechanical errors. Note that, when a logical fraud event is detected, the same processing as in the information processing apparatus of FIG. 2 is performed.

[0012]

As described above, FIG.
According to the conventional example, the state of internal resources that would be difficult or impossible to retry after being updated is saved in another place in advance, and the internal resources are Since the state of the resource is returned to an earlier state at an appropriate time or the update is made as slow as possible, there is a problem that control for retry becomes complicated. In particular, in an information processing device that is pipelined with the aim of speeding up processing, internal resources that are saved for retry and internal resources that make updating as slow as possible are extremely large. There is a problem that control becomes very complicated.

In the configuration shown in FIG. 3, it is generally considered that the possibility of occurrence of a mechanical error is extremely low at the same time. On the other hand, a special means for restarting when a mechanical error is detected is considered. Is not required for the individual processing circuits 301 and 302. However, since the detection of a logical fraud event occurs at the same time, it is necessary to save the internal resources in order to resume the appropriate processing, which has the same problem as the prior art in FIG.

An object of the present invention is to provide a retry method for an information processing apparatus which is easy to control.

[0015]

According to the present invention, in order to achieve the above object, (A) a first processing circuit and a configuration of the first processing circuit
The same processing as the first processing circuit
A second processing circuit that executes with a delay of a cycle , wherein the first processing circuit detects a mechanical error or a logically incorrect event in its own processing circuit, so that the second processing circuit After the failure detection is notified to the second processing circuit and the information indicating the state of the internal resource is sent from the second processing circuit, the state of the internal resource of the own processing circuit is updated according to the sent information. The processing is retried and restarted, and the second processing circuit, upon being notified of the failure detection from the first processing circuit, transmits information indicating the state of the internal resources of its own processing circuit to the first processing circuit. To send to.

Further, the present invention facilitates the control for retrying the second processing circuit operating with a predetermined cycle delay with respect to the first processing circuit. The first processing circuit and the configuration
The same processing as the first processing circuit
A second processing circuit that executes with a delay of a cycle , wherein the first processing circuit receives a notification of failure detection from the second processing circuit, and thereby receives information indicating a state of internal resources of its own processing circuit. Is transmitted to the second processing circuit, and the second processing circuit detects a mechanical error or a logical illegal event in its own processing circuit, thereby detecting a failure in the first processing circuit. And the information indicating the state of the internal resource is sent from the first processing circuit, thereby updating the state of the internal resource in the own processing circuit according to the sent information. After being sent
It is to retry the process after the predetermined cycle elapses.

Further, the present invention further provides: (C) a first processing circuit, and a configuration comprising the first processing circuit , in order to facilitate control for retrying the first and second processing circuits. But
The same processing as the first processing circuit
A second processing circuit that executes with a delay of a cycle , wherein the first processing circuit detects a mechanical error or a logically incorrect event in its own processing circuit, so that the second processing circuit After the failure detection is notified to the second processing circuit and the information indicating the state of the internal resource is sent from the second processing circuit, the state of the internal resource of the own processing circuit is updated according to the sent information. The processing is retried and restarted, and the second processing circuit notifies the first processing circuit of failure detection by detecting a mechanical error or a logical illegal event in its own processing circuit. When the information indicating the state of the internal resource is sent from the first processing circuit, the state of the internal resource in the own processing circuit is updated in accordance with the sent information.
Can process after said predetermined cycle elapses after a retry to shall.

[0018]

In the configuration (A), when a mechanical error or a logical illegal event occurs in the first processing circuit, a failure detection is notified from the first processing circuit to the second processing circuit. You. When the second processing circuit is notified of the failure detection from the first processing circuit, the second processing circuit transmits information indicating the state of the internal resources in its own processing circuit to the first processing circuit. In the first processing circuit, the second
The state of the internal resources in the own processing circuit is updated according to the information sent from the processing circuit, and then the processing is retried and restarted.

In the configuration (B), when a mechanical error or a logical illegal event occurs in the second processing circuit,
Is notified of the failure detection to the first processing circuit. When the first processing circuit is notified of the failure detection from the second processing circuit, the first processing circuit transmits information indicating the state of the internal resources in its own processing circuit to the second processing circuit. The second processing circuit updates the state of the internal resources in its own processing circuit according to the information sent from the first processing circuit, and furthermore, after a predetermined cycle
After, we retry the process.

In the configuration (C), when a mechanical error or a logical illegal event occurs in the first processing circuit,
The processing shown in the configuration of (A) is performed, and the processing shown in the configuration of (B) is performed when a mechanical error or a logical illegal event occurs in the second processing circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which a first processing circuit 101 and a second processing circuit 120 are shown.
And an external resource 106 such as a main storage device accessible from the first and second processing circuits 101 and 120, and a cycle delay circuit 107.

The first and second processing circuits 101 and 120 are clock-synchronous processing circuits which operate in synchronization with the synchronous clock signal 109. The operation is delayed by a predetermined clock cycle.

The first and second processing circuits 101 and 120 are composed of arithmetic circuits 102 and 112 and internal resources 103 and 1 respectively.
13, the detection circuits 104 and 114, the control circuit 105,
115.

The internal resources 103 and 113 are an instruction counter,
It includes registers, built-in memory, etc.

The arithmetic circuits 102 and 112 synchronize the internal resources 103 and 113 and the external resources 10
6 is accessed to proceed with the information processing.

The detection circuits 104 and 114 are
2 and 112, a mechanical error such as a parity error generated in the process of accessing the external resource 106, the arithmetic circuit 102,
A logical illegal event such as a logically illegal process that occurs in a process in which the 112 accesses the internal resources 103 and 113 is detected.

The control circuits 105 and 115 are
2 and 112, update the internal resources 103 and 113, and communicate with the partner processing circuits 120 and 101.

The cycle delay circuit 107 is constituted by a first-in first-out buffer, and when the first processing circuit 101 extracts the contents of the external resource 106 via the external input / output signal line 108, the input to the second processing circuit 120 Is delayed by the delay of the second processing circuit 120 side.

Next, the operation of this embodiment will be described.

The second processing circuit 120 is the first processing circuit 1
01 is delayed by a predetermined clock cycle. The programs executed by the first and second processing circuits 101 and 120 are exactly the same except for the following points. That is, the read instruction for the external resource 106 included in the program executed by the first processing circuit 101 is replaced with the read instruction for the cycle delay circuit 107 in the program executed by the second processing circuit 120, and the first processing circuit External resource 1 included in the program executed in 101
The write instruction for 06 is replaced by a no-operation instruction in the program executed by the second processing circuit 120.

Now, for example, it is assumed that a mechanical error or a logical illegal event has been detected by the detection circuit 104 of the first processing circuit 101 which is performing processing in advance.

When the detection circuit 104 detects a mechanical error or a logical illegal event, it notifies the control circuit 105 of the detection.

Upon receiving this notification, the control circuit 105 first instructs the arithmetic circuit 102 in the processing circuit 101 to interrupt the processing, and also controls the control circuit in the second processing circuit 120 via the mutual control signal line 110. Notify 115 that a failure has occurred.

When the control circuit 115 receives the notification of the occurrence of the fault, it instructs the arithmetic circuit 112 in its own processing circuit 120 to interrupt the processing, and thereafter changes the state of the internal resource 113 via the internal resource information transfer line 111 to the first state. To the internal resources 103 in the processing circuit 101. Here, since the second processing circuit 120 operates with a delay of a predetermined clock cycle with respect to the first processing circuit 101, the state of the internal resources 113 in the second processing circuit 120 is changed to the first processing circuit. By transferring to the internal resource 103 in 101, the state of the internal resource 103 can be returned to the state before the occurrence of a mechanical error or a logical illegal event.

The control circuit 105 in the first processing circuit 101
When the state of the internal resource 103 is returned to the state before the occurrence of the mechanical error or the logical illegal event, the following processing is performed.

That is, when the occurrence of a mechanical error is notified from the detection circuit 104, the same processing as the interrupted processing is retried by the arithmetic circuit 102 as in the conventional example.

Also, when the occurrence of a logical illegal event is notified from the detection circuit 104, a part of the data in the internal resource 103 is replaced and the operation
2 to restart the processing, or return all or a part of the internal
To perform another process.

Next, the operation in the case where a mechanical error or a logical illegal event has occurred in the second processing circuit 120 which is performing the subsequent processing will be described.

Detection circuit 114 in second processing circuit 120
Detects a mechanical error or a logically incorrect event and notifies the control circuit 115 of the detection. Here, the detection circuit 114
If the error detected is a logically incorrect event, the error should be detected by the preceding detection circuit 104 in the first processing circuit 101, and may be regarded as a mechanical error.
Therefore, the detection circuit 114 may have only a function of detecting a mechanical error.

Upon receiving this notification, the control circuit 115 first instructs the arithmetic circuit 112 to interrupt the processing and notifies the control circuit 105 in the partner processing circuit 101 of the occurrence of a fault via the mutual control signal line 110.

The control circuit 105 in the first processing circuit 101
Immediately instructs the arithmetic circuit 102 to interrupt the processing when the occurrence of the failure is notified or immediately after the processing reaches the break point. Thereafter, the control circuit 105 controls the internal resources 10
After the state of No. 3 is transferred to the internal resource 113 in the second processing circuit 120 via the internal resource information transfer line 111, the processing is restarted.

The control circuit 115 in the second processing circuit 120 transmits the internal resource 1 via the internal resource information transfer line 111.
After a predetermined clock cycle after receiving the state of 03, the arithmetic circuit 112 is instructed to resume processing.

[0043]

As described above, the present invention relates to the case where a mechanical error or a logical illegal event occurs in a first processing circuit operating a predetermined cycle ahead of a second processing circuit. Since the state of the internal resources in the second processing circuit is transferred to the internal resources in the first processing circuit, the state of the internal resources is saved and the update of the internal resources is delayed as much as possible. As compared with the conventional example, there is an effect that control for retrying the first processing circuit can be facilitated.

Further, according to the present invention, when a mechanical error or a logical illegal event occurs in the second processing circuit, the state of the internal resources in the first processing circuit is transferred to the internal resources in the second processing circuit. Therefore, there is an effect that control for retrying the second processing circuit can be facilitated.

Further, according to the present invention, when a mechanical error or a logical illegal event occurs in the first and second processing circuits, the state of the internal resources in the second and first processing circuits is changed to the first and second processing circuits. ,
Since the data is transferred to the internal resources in the second processing circuit, there is an effect that control for retrying the first and second processing circuits can be facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a block diagram of another conventional example.

[Explanation of symbols]

 101, 120, 201, 301, 302 processing circuit 102, 112, 202 arithmetic circuit 103, 113, 203 internal resource 104, 114 detection circuit 105, 115, 208 control circuit 106, 205, 303 external resource 107: cycle delay circuit 108: external input / output signal line 109: synchronous clock signal 110: mutual control signal line 111: internal resource information transfer line 206: mechanical error detection circuit 207: logical fraud detection circuit

Claims (3)

(57) [Claims] The first processing circuit has the same configuration as the first processing circuit, and the first processing circuit has the same configuration as the first processing circuit.
Performs the same processing as the processing circuit with a predetermined cycle delay.
And a second processing circuit for row, the first processing circuit, by detecting the mechanical error or logical fraud events at the self-processing circuit, failure to said second processing circuit The detection is notified, and the information indicating the state of the internal resource is sent from the second processing circuit, so that the state of the internal resource of the own processing circuit is updated according to the sent information, and then the processing is restarted. The second processing circuit, when notified of the failure detection from the first processing circuit, transmits the information indicating the state of the internal resources of the own processing circuit to the first processing circuit.
A retry method for the information processing apparatus, wherein the retry method is transmitted to the processing circuit of (1). 2. The first processing circuit has the same configuration as the first processing circuit, and the first processing circuit has the same configuration as the first processing circuit.
Performs the same processing as the processing circuit with a predetermined cycle delay.
A second processing circuit for performing the processing, wherein the first processing circuit receives information indicating a failure detection from the second processing circuit, and transmits information indicating a state of an internal resource of the own processing circuit to the second processing circuit. 2
The second processing circuit notifies the first processing circuit of failure detection by detecting a mechanical error or a logical illegal event in its own processing circuit, When the information indicating the state of the internal resource is transmitted from the first processing circuit, the state of the internal resource in the own processing circuit is updated according to the transmitted information.
Retry mechanism of the information processing apparatus according to claim re <br/> attempt to Rukoto processing after said predetermined cycle elapses from becoming is sent. 3. The first processing circuit has the same configuration as the first processing circuit, and the first processing circuit has the same configuration as the first processing circuit.
Performs the same processing as the processing circuit with a predetermined cycle delay.
And a second processing circuit for row, the first processing circuit, by detecting the mechanical error or logical fraud events at the self-processing circuit, failure to said second processing circuit The detection is notified, and the information indicating the state of the internal resource is sent from the second processing circuit, so that the state of the internal resource of the own processing circuit is updated according to the sent information, and then the processing is restarted. The second processing circuit notifies the first processing circuit of the failure detection to the first processing circuit by detecting a mechanical error or a logical illegal event in its own processing circuit. When the information indicating the state of the internal resource is sent from one processing circuit, the state of the internal resource in the own processing circuit is updated according to the sent information.
Retry mechanism of the information processing apparatus according to claim re <br/> attempt to Rukoto processing after said predetermined cycle elapses from becoming is sent.