JP3096801B2 - Time series data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time series data processing device.

[0002]

2. Description of the Related Art With the recent increase in screen size of home color television receivers, recording and reproducing media for video signals and audio signals have been improved in image quality and sound quality. In addition, as a storage medium for recording and reproducing high-quality video and high-quality sound while maintaining high-quality and high-quality sound, homes that digitize video signals and audio signals and perform band compression (high-efficiency coding) for recording and reproduction. Digital magnetic recording / reproducing device (hereinafter referred to as
Digital VTR) is known.

[0003] For recording / reproducing the sound in this digital VTR, for example, stereo sound of two channels is converted into two.
In general, a system capable of recording and reproducing data of more than one system, that is, four or more channels is used. By the way, ordinary stereophonic devices have two types, L (left) and R (right), except for special applications.
Since most of the channel audio is reproduced by a speaker or headphones, only the two channels of the four-channel audio that are actually output as audio are limited. That is, only audio data for two channels is output to a stereo audio device (not shown) connected to the audio output terminal of such a digital VTR. Therefore, it is necessary to select and process two channels of the four channels for output.

As a practical method for selecting two channels, for example, a combination as shown in Table 1 can be considered. For example, Japanese data of bilingual broadcasting is A data, English is B
When recorded as data, it would be very difficult to hear if A data and B data were reproduced at the same time. Therefore, in order to reproduce only Japanese voice, it is necessary to output a pair of A data and A data. For the same reason, a pair of B data and B data, C data for French and D data for German
In the case of data, it is necessary to output C data / C data pair and D data / D data pair.

[0005]

[Table 1]

It is also assumed that BGM (background music) is added in stereo to a stereo recording by, for example, editing. In this case, the so-called after-recording is performed. In this case, the stereo sound at the time of video shooting is recorded as A data / C data of the first system L / R channels and added during editing.
About BGM B data of the second system L / R channel
Consider the case where the data is recorded as D data.

When it is desired to reproduce both the sound at the time of video shooting and the BGM simultaneously, for example, a mixed sound of A data + B data and a mixed sound of C data + D data are reproduced as L sound and R sound, respectively. The L sounds are reproduced as L sounds and the R sounds are reproduced as R sounds, so that the sound can be reproduced with a natural feeling together with the BGM.

If the audio device (not shown) to which the digital VTR is connected is not a stereo device, that is, if it is a device that can only reproduce monaural sound, which is generally called, the left and right sounds of the first system stereo sound are output. Mixed A data + C data audio, or similarly B data + D
Since it is necessary to output data audio, A data + C data / A data + C data pair, B data + D data
Data output of a B data + D data pair is required.

It is necessary to select various reproduction sounds depending on the usage of the four channels of the audio data recorded as described above, the type of the connected audio device, and the like. Conventional audio processing in such a digital VTR will be described with reference to FIG.

FIG. 12 is a block diagram of a digital VTR audio data processor capable of recording and reproducing two channels of stereo audio in two channels. Reference numeral 10 denotes input audio data, 11 denotes a timing control input signal for identifying the input audio data, and selects appropriate two channels from the input audio data 10 and the timing control input signal 11 to output the audio data 600 and the timing control. An output signal 700 is obtained.

251 to 254 receive the input audio data 10 and four types of latch timing signals 711 to 714, respectively.
Four 16-bit data latches for obtaining latch outputs 2510 to 2540. The latch contents of these four types of data latches are output to the data bus 151, and the data bus 151
16-bit 4-input / 1-output selectors (hereinafter referred to as 4-1 selectors) 351 to 354 are connected to the input side.

Of the four 4-1 selectors 351-354,
Output signals 3510 and 3 of two 4-1 selectors 351 and 352
520 is input to an adder for average value calculation 451, and the output signals 3530 and 3540 of the remaining 4-1 selectors 353 and 354 are input to an adder for average value calculation 452. The 4-1 selectors 351 to 354 are supplied with control signals 81 to 84 for controlling the selection operation from the audio selection control unit 8, respectively.

The outputs of the adders 451 and 452 are input to one input terminals of multipliers 551 and 552 for attenuation calculation, respectively, and the other input terminals of the multipliers 551 and 552 have fade / mute level values 91 and 92 respectively. A mute signal is provided from the fade / mute control unit. Multiplier 551
And 552 output 5510 and 5520 are 16-bit 2-input 1
It is input to an output selector (hereinafter referred to as a 2-1 selector) 65.

The 2-1 selector 65 includes a timing controller 7
Is output, a selection output 650 is output and input to the parallel-serial converter 1. The output signal 730 of the timing controller 7 is supplied to the parallel-serial converter 1.
Is input, and output audio data 600 is output. The timing control section 7 also outputs a timing control output signal 700.

Next, the operation of the audio data processing apparatus will be described. Normally, audio data is generally digitally quantized to 16 bits per channel. Here, a case where digital data is digitally quantized to 16 bits per channel will be described. When transmitting 16-bit audio data for 4 channels, it is usual to transmit the data for 4 channels in a time-division manner on a data bus having a width of 16 bits. This will be described with reference to a data input format shown in FIG.

FIG. 13 shows the format of an input signal, which is composed of 16 bits of input audio data and 2 bits of a timing control input signal indicating the content of the signal. In FIG. 13, the first system L channel audio data is A, the second system L channel audio data is B, the first system R channel audio data is C, the second system R channel audio data is D,
Also, the 0th audio data is A0, B0, C0,
D0, the first audio data is A1, B1, C1, D1
And Similarly, the N-th data AN, BN, C
N and DN.

The timing control input signal 11 is a signal for identifying the content of the input audio data, and is input so as to be uniquely determined according to the content. For example, 0 is input when A data is input, 1 when B data is input, 2 when C data is input, and 3 when D data is input.

Referring to FIG. 13, 16-bit data latches 251-
Numerals 254 are used to fetch A data, B data, C data and D data from the input audio data stream, respectively. The timing signal for the fetching is taken by the timing control section 7 as fetched signals 711 to 714 and the respective data latches 251 to 254. To supply.

The output of each data latch is connected to a data bus 151.
2510 to 2540 are input, and are composed of 64 data buses. The data of this data bus 151 is 4 bits of 16 bits.
Each of the 4-1 selectors selects one of the A data to D data and outputs a 16-bit data signal 3510 to 3540.

The adder for average value calculation 451 is a 4-1 selector.
Calculate the average value of the 351,352 output signals 3510 and 3520,
The adder for average value calculation 452 calculates the average value of the output signals 3530 and 3540 of the 4-1 selectors 353 and 354, and outputs average value signals 4510 and 4520, respectively. This average signal 4510 is the source signal of the L channel of the output audio data,
4520 is the source signal of the R channel of the output audio data.

The attenuation calculation multiplier 551 performs audio fade or mute processing on the L-channel source signal 4510 of the output audio data, and multiplies the average signal 4510 by a fade / mute level value 91. Then, the processing result is output as a signal 5510. The fade / mute level value 91 is set to 0, for example, when the output sound is completely erased, and 0.5 for a half level.
And When fading out, set the value from 1 to 0
If the sound is gradually changed over a certain period of time (for example, one second), the output sound becomes gradually smaller, and finally (for example, one second later), the sound is completely muted.

In order to perform this processing, the fade
The block that temporally processes the mute level value 91 is the fade / mute control unit 9, which performs the above-described operation upon receiving a command from an external block (not shown) as a mute request signal or a fade request signal.

The multiplier for attenuation calculation 552 operates in the same manner as 551, and the signal to be calculated is the average value signal 4520 and the multiplier 552 for attenuation calculation is based on the fade / mute level value 92.
Is controlled. The 16-bit 2-1 selector 65 alternately selects the L channel output signal 5510 and the R channel output signal 5520 to generate an output signal 650 as audio data. The switching operation of the 2-1 selector 65 is performed by a control signal 720. If the control signal 720 is, for example, a high level, an output signal
Select and output 5510, and if low level, output signal 5520
Select and output.

The data of the R channel and the data of the L channel are temporally multiplexed by the selector
The bit is input as an output signal 650 to a bus (not shown). The parallel-serial converter 1 converts 16-bit parallel data 650 input thereto into 1-bit serial data. Next, this conversion operation will be described with reference to FIG. It is assumed that the 16-bit input data shown in FIG. 14B temporally follows D0, D1,. The parallel-serial converter 1 performs an operation of outputting 16-bit input data one bit at a time using a signal 16 times the data rate of the input data as an operation clock shown in FIG. Is time-divisionally output one bit at a time in order from the LSB side of, for example, parallel 16 bits as shown in FIG. 14 (c).

As described above, the output signal 650 of the 16-bit selector 65 is converted into 1-bit serial data and output as output audio data 600. Note that the timing control output signal 700 is simultaneously output for identifying the 1-bit data thus output. The timing control output signal 700 goes high, for example, when the output audio data 600 is L-channel data, goes low when the output audio data 600 is R-channel data. In synchronization with the first bit data output of the R channel data, and switches from the high level to the low level.

Therefore, the audio device (not shown) connected to the digital VTR receives the output audio data 600 and the timing control output signal 700 again to output 16 bits 2 bits.
The 16-bit audio data of the channel can be reproduced and audio output is possible. As described above, a method of transmitting a timing control output signal for identifying data bits simultaneously with 1-bit audio data is very commonly used when connecting audio devices.

Such an operation will be described below with a specific example. FIG. 15 shows audio data A of four channels.
When B, C, and D are input, L is output as output audio data.
FIG. 9 is a timing chart of signals of respective units when outputting an average value of data A and C data to a channel and outputting an average value of B data and D data to an R channel;

As shown in FIG. 15A, the input audio data 10 is composed of four channels of A data to D data of 16 bits simultaneously.
In terms of time, A data, B data, C data, and D data are sequentially and sequentially input in this order. Dedicated data latches 251 to 254 for A data to D data select and latch the respective data according to the output of the timing control unit 7. Thereafter, FIG. 15 showing the contents of each data latch 251 to 254
Output signals 2510 to 2540 shown in (b) to (d) are
Is output to

The 4-1 selector 351 selects only the A data from the data bus 151 as shown in FIG.
Enter 1 The 4-1 selector 352 selects only the C data as shown in FIG. 15 (g) and inputs the same to the adder 451. The adder 451 calculates the average value of both inputs and calculates the average of the A data and the C data. The average value signal 4510 of the average value is output as shown in FIG. Similarly, the 4-1 selector 353 is arranged as shown in FIG.
The 4-1 selector 354 converts the B data shown in FIG.
And the output signals 3530 and 3540 shown in FIGS. 15 (i) and (j) are input to the average value adder 452, and the average value adder 452 calculates the average of both inputs. By calculating the value, the average signal 4520 of the average value of the B data and the D data is obtained as shown in FIG.
Output as shown.

The 16-bit selector 65 outputs the average signal 5510 and
5520 is switched and output at the timing shown in FIG.
The parallel-serial converter 1 outputs the audio data 600 shown in FIG.
The timing control output signal 700 shown in (m) is output.

[0031]

In the above-described conventional audio data processing apparatus, the input audio data is temporarily stored as 16-bit data.
In addition to the necessity, 64 data buses are required, and the number of wirings is greatly increased. Also, four large selectors for 64-bit input and 16-bit output are required for the 4-1 selector for audio data selection.
Furthermore, the average value operation adder is also a 16-bit parallel adder.
Since two parallel multipliers for fade and mute operation are required, the circuit scale of the audio data processing apparatus becomes extremely large, and the cost is high.

An object of the present invention is to provide an inexpensive time-series data processing apparatus in which the wiring scale of the apparatus and the circuit scale are significantly reduced in order to solve the above drawbacks. .

[0033]

A time series data processing apparatus according to a first aspect of the present invention includes a parallel-serial converter that converts time series data of one channel of m bits and n channels into m bits of serial data, A shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter is to be inputted;
A plurality of 1s for selectively selecting output data of the parallel-serial converter and output data of the shift register.
A bit selector, an output switching 1-bit selector for selectively selecting output data related to output data of the plurality of 1-bit selectors, the parallel-serial converter, the shift register, and the output switching 1-bit selector And a timing control unit for controlling the operation timing of.

The time-series data processing device according to the second invention comprises:
One channel is m-bit, and the parallel channel converts n-channel time-series data into m-bit serial data.
A serial converter, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter should be input, and output data of the parallel-serial converter and the shift register. A plurality of 1-bit selectors for selectively selecting output data, and an adder to which k (k is a natural number) output data of the 1-bit selectors is inputted and one-bit full addition is performed m + k-1 times and an addition operation is performed. An output switching 1-bit selector for selectively selecting the output data of the plurality of 1-bit selectors or the output data of the adder; the parallel-serial converter, the shift register, and the output switching 1-bit selector And a timing control unit for controlling the operation timing of.

The time series data processing device according to the third invention comprises:
One channel is m-bit, and the parallel channel converts n-channel time-series data into m-bit serial data.
A serial converter, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter should be input, and output data of the parallel-serial converter and the shift register. A plurality of 1-bit selectors for selectively selecting output data, and output data of the 1-bit selector are input, and each bit data is provided for at least two data in a data sequence for each 1-bit delay of the output data. A logical product of the output data and a constant bit, performing a full addition for each bit, and calculating a multiplication of the output data and the constant bit; An output switching 1-bit selector for selectively selecting output data of a multiplier, the parallel-serial converter, and the shift And a timing controller for controlling the operation timing of the register and the output switching 1 bit selector.

The time series data processing device according to the fourth invention comprises:
One channel is m-bit, and the parallel channel converts n-channel time-series data into m-bit serial data.
A serial converter, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter should be input, and output data of the parallel-serial converter and the shift register. A plurality of 1-bit selectors for selectively selecting output data;
An adder that performs an addition operation by performing a total addition of bits m + k−1 times, and the output data of the 1-bit selector or the output data of the adder, and at least two of a data string for each 1-bit delay of the input data For one set of data,
Find the logical product of each bit data and a constant bit,
A multiplier for performing full addition on a bit-by-bit basis to calculate a multiplication result, and at least two or more of output data of the plurality of 1-bit selectors, output data of the adder, or output data of the multiplier are input An output switching 1-bit selector for selectively selecting input output data; and a timing control unit for controlling operation timings of the parallel-serial converter, the shift register, and the output switching 1-bit selector. Prepare.

An adder according to a fifth aspect of the present invention comprises: a first delay unit for delaying one bit of each of two input data; and a switch circuit for switching output data of the first delay unit and the input data. The switch circuit operates to output input data from the first bit to the m-th bit of the input data, and to select the output data of the first delay unit at the (m + 1) -th bit. A full adder that performs a full addition of a carry input bit and a carry output bit and an addition result bit, outputs 0 or 1 in a first bit, and outputs a second bit and subsequent bits Comprises a second 1-bit delay device that delays the carry output bit by one bit and outputs the carry input.

The time series data processing device according to the sixth invention comprises:
One channel is 16 bits, and the parallel channel converts time-series data of four channels into 16-bit serial data.
A serial converter, a shift register formed by cascading three stages of 16-bit shift registers to which output data of the parallel-serial converter is to be input, output data of the parallel-serial converter, and output data of the shift register Four sets of 1-bit selectors for selectively selecting two output data, two sets of adders for inputting two different output data from the different 1-bit selectors, performing one-bit full addition 17 times and performing an addition operation, For each output data of the set of adders, a logical product of each bit data of the data sequence for each 1-bit delay and a constant bit is obtained, and the obtained results are multiplied by performing a full addition for each bit. An output switching 1-bit selector for selectively selecting output data of each multiplier; the parallel-serial converter, the shift register, and the output switching 1-bit selector. A timing control unit for controlling the operation timing of the rectifier.

According to a seventh aspect of the present invention, there is provided a multiplier comprising: input bit data; a delay unit for delaying the input bit data by one bit; and the delay units are cascade-connected in a plurality of stages. A logic circuit for calculating a logical product of each of the plurality of variable constant bits independent of each other, an adder for adding each output data of the logic circuit, and an output data of the adder and an output data of the delay device. The maximum delay data is constituted by a switch circuit which selects the data based on the variable constant bit data.

An adder according to an eighth aspect of the present invention includes a first delay unit that delays each of two input data by one bit,
A switch circuit for switching between output data and input data of the first delay device, wherein the switch circuit outputs input data from the first bit to the 16th bit of the input data;
The 17th bit operates to select and output the output data of the first delay unit, performs a full addition of the two output data of the switch circuit and the carry input bit, and outputs the operation result to the carry output bit. And a full adder that outputs 0 or 1 as the first bit, and a second bit that outputs the carry input by delaying the carry output by one bit after the second bit. 1-bit delay device.

The time series data processing device according to the ninth invention is
One channel is m-bit, and the parallel channel converts n-channel time-series data into m-bit serial data.
A serial converter and a 1-bit shift register to which output data of the parallel-serial converter are input are m × (n
-1) a shift register connected in cascade, a plurality of 1-bit selectors for selectively selecting output data of the parallel-serial converter and output data of the shift register, and different one-bit selectors Two output data are input, and one for each of those data.
A switch circuit for switching between the bit-delayed data and the data input from the 1-bit selector, the switch circuit outputting the input data from the first bit to the m-th bit of the input data, and It operates to select the output data of the first delay device, performs full addition of the two output data from the switch circuit and the carry input bit, and outputs the operation result as a carry output bit and an addition result bit. An adder and a 1-bit delay unit that outputs 0 or 1 for the first bit and delays the carry output by 1 bit and outputs a carry input for the second and subsequent bits. An adder for performing addition, an output switching 1-bit selector for selectively selecting output data of a 1-bit selector or output data of the adder, and the parallel-serial converter Shift register, and a said adder and a timing control unit for controlling the operation timing of the output switching 1 bit selector.

The time series data processing device according to the tenth invention is
One channel is m-bit, and the parallel channel converts n-channel time-series data into m-bit serial data.
A serial converter and a 1-bit shift register to which output data of the parallel-serial converter are input are m × (n
-1) a shift register connected in cascade, a plurality of 1-bit selectors for selectively selecting output data of the parallel-serial converter and output data of the shift register, and different one-bit selectors A switch circuit for receiving two output data and switching between data delayed by one bit with respect to each of the data and data input from the one-bit selector is provided. Bit to m-th
Up to the bit, the input data is output, the operation is performed to select the output data of the first delay unit at the (m + 1) th bit, and the two output data of the switch circuit and the carry input bit are fully added, A full adder that outputs a calculation result as a carry output bit and an addition result bit; 0 or 1 is output as the first bit, and the carry output bit is delayed by one bit for the second and subsequent bits, and An adder that includes a 1-bit delay device that outputs an up input and performs 1-bit addition;
The output data of the one-bit selector or the output data of the adder is input, and at least two data of a data sequence for each one-bit delay of the output data are ANDed with each bit data and a constant bit And a multiplier that performs full addition on a bit-by-bit basis to calculate a multiplication, and at least two or more of the output data of the plurality of 1-bit selectors, the output data of the adder, or the output data of the multiplier. An output switching 1-bit selector for selectively selecting a plurality of input data and an input, and the parallel-serial converter, the shift register, the adder, the multiplier, or the output switching 1-bit selector And a timing control unit for controlling the operation timing of.

The time series data processing device according to the eleventh invention is
One channel is 16 bits, and the parallel channel converts time-series data of four channels into 16-bit serial data.
A serial converter, a 48-bit shift register to which output data of the parallel-serial converter is input, and four shift registers for selectively selecting output data of the parallel-serial converter and output data of the shift register. A 1-bit selector and a switch circuit which receives two different output data of the 1-bit selector and switches between data delayed by 1 bit with respect to each of the data and data input from the 1-bit selector. And the switch circuit comprises a first bit to a sixteenth bit of the input bit data.
It operates to output the input data up to the bit, select the data delayed at the 17th bit, perform the full addition of the two output data of the switch circuit and the carry input bit, and carry the operation result. A full adder that outputs as an output bit and an addition result bit, outputs 0 or 1 in the first bit, and outputs the carry input by delaying the carry output bit by one bit in the second and subsequent bits. Two sets of adders each including a 1-bit delay unit for adding one bit, and for each output data of the two sets of adders, each bit data of a data string for each one-bit delay, A multiplier for calculating a logical product of the bits and performing a full addition on a bit-by-bit basis to calculate a multiplication; an output switching 1-bit selector for selectively selecting output data of each of the multipliers; −
A timing controller for controlling the operation timing of the serial converter, the shift register, the adder, the multiplier, or the output switching 1-bit selector.

[0044]

According to the first aspect of the invention, the time-series data in which one channel is m bits and the n channels are time-divided is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each shift register in which an m-bit shift register is cascade-connected by n-1 stages.
Data of one channel is obtained. One-channel data without delay is obtained from the parallel-serial converter. The n 1-bit selectors selectively select the obtained n-channel data. Data related to the selected data is input to the output switching 1-bit selector,
When the output switching 1-bit selector performs a switching operation at the timing of the time series data, data related to the selected data is obtained alternately on different channels.

In the second invention, the time-series data in which one channel is m bits and the n channels are time-divided is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each 1-bit shift register cascaded in (n-1) stages, and data of n channels is obtained from each shift register. One-channel data without delay is obtained from the parallel-serial converter. N obtained
K 1-bit selectors select the channel data alternatively. The 1-bit full addition of the data of the selected different channels is performed m + k-1 times to obtain the average of both data. When either the output data of the 1-bit selector or the average of both data is input to the output switching 1-bit selector and the output switching 1-bit selector switches at the timing of the time series data, the output data or the average of both data is Obtained alternately on different channels.

In the third invention, time series data in which one channel is m bits and n channels are time-divided are
The data is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each 1-bit shift register cascaded in (n-1) stages, and data of the (n-1) -th channel is obtained from each shift register. One-channel data without delay is obtained from the parallel-serial converter. The n 1-bit selectors alternatively select the obtained n-channel data. For at least two data in the data sequence for each 1-bit delay of the selected data, a logical product of each data and a constant is obtained, and the obtained results are fully added one bit at a time to obtain input data. change. Either the output data of the 1-bit selector or the changed data is input to the output switching 1-bit selector, and when the output switching 1-bit selector performs the switching operation at the timing of the time series data, the output data or the data is changed. The changed data is obtained alternately on different channels.

In the fourth invention, time series data in which one channel is m bits and n channels are time-divided are
The data is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each shift register connected in cascade of n-1 stages, and data of the n-1 channel is obtained from each shift register. One-channel data without delay is obtained from the parallel-serial converter. The k different 1-bit selectors selectively select the obtained data of different channels. 1-bit full addition of selected data is m
Perform + k-1 runs to get the average of the data. 1 by multiplier
For at least two data in a data sequence for each 1-bit delay of the output data of the bit selector or the output data of the adder, a logical product of each data and a constant bit is obtained,
The results are subjected to full addition for each bit and multiplied, and the average of the data is changed according to the constant bits. Either the output data of the 1-bit selector, the output data of the adder, or the output data of the multiplier is input to the output switching 1-bit selector, and the output switching 1 is output at the timing of the time series data.
When the bit selector performs the switching operation, one of the output data of the 1-bit selector, the output data of the adder, and the output data of the multiplier is obtained alternately on different channels.

In the fifth invention, each of the switch circuits to which two input data are separately input selects the input data from the first bit to the m-th bit of the input data, and selects the (m + 1) -th input data.
The output data of the first delay unit is selected at the bit position, and the full addition of the input data and the output data and the carry input bit is performed. The second delay unit outputs 0 or 1 in the first bit, and after the second bit, the carry output bit is delayed by one bit, and the data obtained by performing the full addition carries two bits. The average of the input data is obtained.

In the sixth invention, time series data in which one channel is 16 bits and four channels are time-divided are
The data is converted to 16-bit serial data by a parallel-serial converter. The converted serial data is delayed by 16 bits by each shift register connected in cascade in three stages, and data of three channels is obtained from each shift register. 1 not delayed from parallel-serial converter
Channel data is obtained. The obtained four-channel data is selected alternatively by four 1-bit selectors. Then, for two sets of different 1-bit selectors, 1-bit full addition is performed 17 times on each of the two sets of output data, and the average of two sets of different data is obtained.
The logical product of each bit data of the data sequence for each 1-bit delay and a constant bit is calculated with respect to the average of the data, and the obtained results are multiplied by adding all the obtained results bit by bit to obtain the data. Is changed according to the constant bit. The data whose average has been changed is input to the output switching 1-bit selector, and the output switching 1 bit is selected at the timing of the time series data.
When the bit selector performs a switching operation, data in which the average of data is changed is obtained alternately on different channels.

In the seventh invention, the bit data obtained by calculating the logical product of the input bit data and the variable constant bit, and the bit data obtained by delaying the input bit data by one bit and the bit data obtained by calculating the logical product of the variable constant bit are obtained. to add.
The maximum delay data obtained by further delaying the bit data by one bit and the added bit data by
If an alternative is selected according to the variable constant bit, data obtained by changing the input bit data according to the variable constant bit is obtained.

In the eighth invention, each of the switch circuits to which two input data are separately input selects the input data from the first bit to the 16th bit of the input data, and sets the first delay at the 17th bit. The output data of the input device is selected, and full addition of the input data and output data and the carry input bit is performed. The second delay unit outputs 0 or 1 for the first bit, and after the second bit, the carry output bit is delayed by one bit to carry the data obtained by performing the full addition. 2
The average of two input data is obtained.

In the ninth aspect, time-series data in which one channel has m bits and n channels are time-divided is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each one-bit shift register connected in cascade with n-1 stages, and data of the (n-1) -th channel is obtained from each one-bit shift register. One-channel data without delay is obtained from the parallel-serial converter.
The obtained n-channel data is alternatively selected by k 1-bit selectors, and a switch circuit in the adder selects the selected data from the first bit to the m-th bit of the input data, and The output data of the first delay unit is selected by the (m + 1) th bit, and the input data and the output data are fully added to the carry input bit. Second
Outputs 0 or 1 in the first bit, and delays the carry output bit by one bit in the second and subsequent bits.
Carry the data after full addition to obtain the average of the two input data. When either the output data of the 1-bit selector or the output data of the adder is input to the output switching 1-bit selector, and the output switching 1-bit selector switches at the timing of the time series data, the output data of the 1-bit selector or Either of the averages of the input data is obtained alternately on different channels.

In the tenth invention, one channel is m bits, and time-series data obtained by time-division on n channels is converted into m-bit serial data by a parallel-serial converter. The converted serial data is delayed by m bits by each 1-bit shift register cascaded in (n-1) stages, and data of n-1 channels is obtained from each 1-bit shift register. One-channel data without delay is obtained from the parallel-serial converter. A plurality of 1-bit selectors alternatively select the obtained data of different channels, and a switch circuit in the adder selects the selected data from the first bit to the m-th bit of the input bit data, and The output data of the first delay unit is selected by the (m + 1) th bit, and the input data and the output data are fully added to the carry input bit. The second delay unit outputs 0 or 1 in the first bit, and carries out the full addition after delaying the carry output bit by one bit in the second and subsequent bits to carry out two inputs. Get the average of the data. For at least two data of the output data of the 1-bit selector or the data sequence for each 1-bit delay of the output data of the adder, the logical product of each bit data and a constant bit is obtained, and the result is 1
When the full addition is performed for each bit and multiplication is performed, the average of the data input to the multiplier is changed according to the constant bit. The data whose average has been changed is input to the output switching 1-bit selector, and when the output switching 1-bit selector performs the switching operation at the timing of the time series data, the average of the changed data is obtained alternately on different channels.

In the eleventh invention, the time-series data in which one channel is 16 bits and four channels are time-divided is converted into 16-bit serial data by a parallel-serial converter. The converted serial data is delayed by 16 bits by a 48-bit shift register, three-channel data is obtained from the 48-bit shift register, and one-channel data without delay is obtained from the parallel-serial converter. Four 1-bit selectors select the data of the obtained different channels. In each of the two sets of adders to which respective output data different from each other are input by the 1-bit selector, the switch circuit selects the input data from the first bit to the 16th bit of the input data, and the first bit at the 17th bit. , And the full addition of the input data and the output data and the carry input bit is performed. The second delay unit outputs 0 or 1 in the first bit, and after the second bit, the carry output bit is delayed by one bit, and the data obtained by performing the full addition carries two bits. Get the average of the input data. When the logical product of the bit data of the data string for each 1-bit delay and the constant bit is calculated for the output data of each of the two sets of adders, and the obtained results are fully added for each bit and multiplied, the multiplier The average of the data input to is changed according to the constant bit. The average of the changed data is input to the output switching 1-bit selector, and when the output switching 1-bit selector performs the switching operation at the timing of the time series data, the average of the changed data is obtained alternately on different channels.

[0055]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram of a first embodiment of a time-series data processing device according to the present invention. The input audio data 10 is input to a parallel-serial converter 110. The output side of the parallel-serial converter 110 is connected to a 4-bit data bus 111 and an input side of a 1-bit 16-stage shift register 21 via a 1-bit signal line 100. The output side of the 16-stage shift register 21 (22) is connected to the data bus 111 and the 1-bit 16-stage shift register 22 (2) via a 1-bit signal line 210 (220).
Connected to the input side of 3). The output side of the 16-stage shift register 23 is connected to the data bus 111 via a 1-bit signal line 230.

The data bus 111 is connected to each input side of the 1-bit 4-1 selectors 31 to 34. 4-1 selector 31 (3
The output side of 2) is connected to one input side (other input side) of the full adder 41 via a 1-bit signal line 310 (320). The output side of the 4-1 selector 33 (34) is connected to one input side (other input side) of the full adder 41 via a 1-bit signal line 330 (340). The output side of the full adder 41 (42) is connected to one input side of the multiplier 51 (52) via a 1-bit signal line 410 (420). Multiplier 51 (5
The output side of 2) is connected to one input side (other input side) of the 1-bit 2-1 selector 6 via a 1-bit signal line 510 (520). The output audio data 600 is output from the selector 2-1.

The output signal 71 of the timing controller 7 is input to the parallel-serial converter 110. The timing control section 7 also outputs a timing control output signal 700.
A control signal 72 for switching output from the timing control unit 7 is supplied to the 2-1 selector 6. A control signal 81 (82, 82) for switching output from the voice selection control unit 8
83, 84) are input to the 4-1 selector 31 (32, 33, 34). The fade mute signal 91 (92) output from the fade mute controller 9 is input to the other input side of the multiplier 51 (52).

Next, the operation of the time series data processing device will be described. Note that the timing control unit 7 and the voice selection control unit 8
The operation of the fade / mute control section 9 is the same as that of the above-described conventional one, and therefore, the description thereof will be omitted.
The input audio data 10 is converted into 1-bit serial data by the parallel-serial converter 1 and converted into 16-bit serial data via a signal line 100.
It is input to the stage shift register 21 and the data bus 111.
The 16-stage shift registers 21 to 23 delay input 1-bit data by 16-bit transmission time and output 1-bit data.

FIG. 2 is a timing chart of the input audio data 10, the operation clock of the shift register, and the audio data of the signal lines 100 and 210. Signal line shown in Fig. 2 (c)
When 100 voice data is input to the shift register 21,
As shown in FIG. 2D, the shift register 21 delays the input audio data by 16-bit data, and
It works to output to. Similarly, shift register 22 (2
3) operates to delay the audio data input thereto by 16-bit data and output the data.

These shift registers 21 to 23 can be simply constructed by cascading, for example, 16 D flip-flops. FIG. 3 is a block diagram of a shift register using a D flip-flop. When the audio data of the signal line 100 is input to the input terminal D of the first stage D flip-flop DF1 and the clock CLK is input to the clock terminal CK, the output of the D stage flip-flop DF1 becomes the input of the next stage D flip-flop DF2. The audio data input to the terminal D, sequentially input to the lower D flip-flop, and input to the first D flip-flop DF1 from the 16th D flip-flop DF16 is delayed by 16 clocks to the signal line 210. Is output.

Similarly to the operation of the shift register 21, the shift registers 22 and 23 also operate and output audio data to the signal lines 220 and 230 with a delay of 16 clocks, respectively. The four signals on the signal lines 100, 210, 220, and 230 are all input to a 4-bit data bus 111. The audio data on the data bus 111 is input to 4-1 selectors 31, 32, 33, and 34. Each selector selectively selects the input 4-bit audio data and outputs it to signal lines 310, 320, 330, and 340, respectively. This selection operation is controlled by the output signals 81, 82, 83, 84 of the voice selection control unit 8 as described in the conventional example.

The average value adder 41 accumulates one bit of each of the audio data on the signal lines 310 and 320 and outputs the result of the operation to the signal line 410. Similarly, the average value adder 42 accumulates and adds one bit to each of the audio data on the signal lines 330 and 340, and outputs the operation result to the signal line 420.

FIG. 4 is a block diagram of the adders 41 and 42 for calculating the average value.
FIG. 1-bit input terminal 40a (40b) is D flip-flop
Input terminal D of the data latch 40i (40k)
Connected to one terminal of input bit selector 40j (40m),
The output terminal Q of the latch 40i (40k) is the input bit selector 40
Connected to the other terminal of j (40m). Input bit selector 40j
(40m) common terminal is input terminal A of adder body 40h_in (B
_in) Is connected. Carry output terminal of adder body 40h
C_outIs connected to the input terminal D of the 1-bit data latch 40g.
The output terminal Q is the carry input of the adder body 40h.
Force terminal C_inConnected to Reset data latch 40g
The carry-in control signal 40c is input to the terminal RES.
The addition bit output terminal SUM of the adder body 40h outputs 1 bit.
Connected to force terminal 40d.

The adding operation of the average value calculating adders 41 and 42 will be described with reference to FIG. The two 1-bit input terminals 40a and 40b and the one 1-bit output terminal 40d correspond to, for example, the 1-bit adder 41 in FIG. 320, the 1-bit output terminal 40d corresponds to the signal 410. For the 1-bit adder 42, a 1-bit input terminal 40
a and signal line 330, 1-bit input terminal 40b and signal line 340,
The 1-bit output terminal 40d corresponds to the signal line 420. Table 2
FIG. 7 is an explanatory diagram of the input / output operation of the 1-bit adder body 40h. Two-bit input terminal _in, and B _in, in response to the speech data of the carry input terminal C _in (40f), the relationship between the speech data of the addition bit output terminal SUM (40d) and a carry output terminal C _out (40e) This is no different from the well-known full adder operation.

[0065]

[Table 2]

The 1-bit data latch 40g is a D flip-flop, and is a carry-out 40 of a 1-bit adder.
This is a circuit for delaying e by one data clock and returning it to the carry-in 40f. The carry-in control signal 40c clears the carry-in 40f at the start of bit addition. This carry-in control signal 40c
1 is not shown in FIG. 1 for the sake of convenience because it is complicated, but a signal corresponding to the carry-in control signal 40c is actually transmitted from the timing control unit 7.

Next, the operation of the average value calculating adder will be described with reference to an example. FIG. 5 is an adder operation timing chart when the average value calculation of the A data and the C data is performed.
While the C data C0 shown in FIG. 5B is being input to the input voice data 10, the input terminals A _in and B _{in of the} adder body 40h are input.
Fig. 5 each delayed by a 16-stage shift register
A data A0 and C data C0 shown in (c) and (d) are respectively input. This can be realized by selecting the A data of the signal line 220 by the bit selector 31 and the C data of the signal line 100 by the bit selector 32 in FIG. This selection operation is performed by the control signals 81 and 82 of the voice selection control unit 8.

At the time of LSB calculation, carry-in control signal 40c
Data latch 40g output (carry-in 40f) is 0
And the input terminals A _in and B _in are respectively initialized as shown in FIG.
The input bit selectors 40j and 40m are controlled by the control signal n so that the A data A000 and the B data B000 shown in (d) are input. Although the control of both input bit selectors is not shown in FIG. 1, it operates by receiving a control signal 40n from the timing controller 7.

In this way, the adder main body 40h is A000
+ C000 is added, and the result of the addition is the carry output terminal C
_out and output to the addition bit output terminal SUM. As a result, first, the operation of the LSB is completed.

In the next data clock cycle, input terminal A
_in A data A001, B _in B data B001
Is input to the carry input terminal C _in and the data latch 40
The carry output of the carry output terminal C _out delayed by one clock by g is input. That is, the carry input terminal C _in
Is the adder body 40h as the carry from the lower bit
Will be entered. And the adder body 40h is the second
The calculation of the bit is performed including the carry from the lower bit, and the addition result is expressed as SM01 and the carry output C to the next bit as the second bit operation result as shown in FIGS.
R01 is output. Thereafter, the same operation is repeated, and the adders A015, C015, C
The addition of R14 is performed.

Since the result of addition between the 16 bits is 17 bits, the adder needs to perform another one-cycle addition operation here. In this case the input audio data A data A015 again to the input terminal A _in the time calculation of the 17th bit for a 16-bit, C data C to the input terminal B _in
The input bit selectors 40j and 40m select the outputs of the data latches 40i and 40k, respectively, so that 015 is input.
Input to 40h.

The data latches 40i and 40k are provided to delay the input data 40a and 40b by one data clock, respectively. In this way, the operation of the 17th bit is performed, and as a result, the addition result SM shown in FIG.
00 to SM16 are obtained.

Here, a bit supplementary explanation of the bit addition will be given. The 16-bit input audio data has positive and negative values and is usually expressed in two's complement. When adding two's complements, which are signed data, add the most significant bit (MSB), which means the sign, as it is to the other higher bit, and create data that is expanded to 17 bits in advance.
Input to each 17-bit input full adder. By doing so, the addition of signed 16 bits is performed correctly, and a 17-bit output is obtained. Incidentally, the operation of adding the sign bit as it is to the upper one bit as it is is called a normal sign extension operation. If the addition is simply performed without performing the sign extension operation, correct operation cannot be performed when negative data is input.

It is necessary to divide by 2 to obtain an average value for the 17 bits of the addition result obtained in this way, but the operation itself is very simple. In order to reduce the number to one half in a binary number, it is sufficient to shift 1-bit data to the LSB side. In other words, if the upper 16 bits are taken out of the 17 bits of the addition result, it can be reduced to half. Therefore, among the calculation results SM00 to SM16 shown in FIG.
The 16 bits of M16 may be sent to the post-processing block as valid data, and the actual post-stage multiplier is controlled by the timing control unit 7 to perform an operation on the bit data. Will be done. Next, the multiplier will be described.

FIG. 6 is a block diagram of the multipliers 51 and 52.
One-bit data 50i is input to one input terminal of AND circuit 50a and D
The data is input to an input terminal D of a data latch 50d composed of a flip-flop. A signal 50M0 to be described later is input to the other input terminal of the AND circuit 50a. An output signal 50e of the data latch 50d is input to an input terminal D of a data latch 50f including an AND circuit 50b and a D flip-flop. AND
A signal 50M1, which will be described later, is input to the other input terminal of the circuit 50b. The output signal 50q (50h) of the AND circuit 50a (50b) is an adder
Input to one input (other input) terminal of 50c. Adder 50c
The output signal 50y of the data latch 50f is input to one input terminal of the switch circuit 50s, and the output signal 50g of the data latch 50f is input to the other input terminal.
Is entered. The switch circuit 50s has a signal 50 to be described later.
M2 is input. The signal 50o is output from the switch circuit 50s. A data clock is input to clock terminals CK of the data latches 50d and 50f.

Next, the operation of the multiplier will be described with reference to FIG. In the figure, 50i is an input signal of 1-bit data, and 16-bit data is sequentially input from the LSB side to the AND circuit 50a and the data latch 50d in synchronization with the data clock. The data latch 50d delays the input signal 50i by one clock and inputs the output signal 50e to the data latch 50f. AND circuit 50a
Performs an AND operation on the input signal 50i and a signal 50M0 to be described later, and outputs 1 only when the value is 1; otherwise, outputs an output signal 50q of 0. AND circuit 50b
Similarly, the output signal 50e and the signal 50
M1 is input and an output signal 50h is output, and the operation is exactly the same as that of the AND circuit 50a.

The adder 50c is a 1-bit adder, and the operation thereof is exactly the same as that of the adder 41 and the like. The switch circuit 50s is a 1-bit 2-1 selector, and outputs the output signal 50s.
Select and output either y or 50g.

Next, further explanation will be given with reference to FIG. 7 which shows a timing chart of the signals of each section. Here, it is assumed that 3-bit data is given as a fade mute value from the fade / mute control unit 9 to simplify the description.
Signals 50M2, 50M1, 50M as 3-bit data
0 is output, of which signals 50M1,
50M0 is input to the AND circuits 50b and 50a, respectively. Signal 5
0M2 is input to the switch circuit 50s and the signal 5M
When 0M2 is a value of 1, the switch circuit 50s outputs the output signal 50s.
g is selected and output, and when the value of the signal 50M is 0, the output signal 50y is selected and output.

This fade mute value corresponds to signals 91 and 92 in FIG. The fade mute value has five values of 0, 1, 2, 3, and 4, and each of the signals 50
It is represented by 3-bit data where M2 is MSB and 50M0 is LSB. These are 0, respectively, as the audio data attenuation value.
It corresponds to a quarter, a quarter, a quarter, and one. For example, if the fade mute value is 0, 50M0, 50M
1 and 50M2 are both 0. At this time, the audio output is 0 and the sound output is silent. 50M when fade mute value is 3
2 = 0, 50M1 = 1, 50M0 = 1, and at this time, the output sound is output at the level of three quarters of the input sound.

FIG. 8 shows a case where the fade mute value is 3. The signals 50M0 and 50M1 are both 1. Therefore, the input signals 50i and 50e of 1-bit data are input to the AND circuits 50a and 50b, respectively, and the output signals are 50q and 50h, respectively.
50h is a signal obtained by delaying the output signal 50q by one clock. Also, the input signal 50i (equal to 50q, see FIG. 6).
7 is the output of the preceding-stage average value adder described above.
This is 16-bit data of SM01 to SM16 shown in FIG.

The adder 50c operates in exactly the same manner as the above-mentioned average value calculating adder, and outputs an output signal 50y as a result of addition. At this time, the sign extension operation has to be performed as described above. To indicate the situation, a * mark is added to the bit position corresponding to FIG. The output signal of the adder 50c is output in a 17-bit length as SA00 to SA16 shown in FIG. 7C, of which SA16 is the MSB.
Input signal by using 16 bits as output data
It will be output as 3/4 value of 50i. And
Here, since the signal 50M2 is 0, the output signal 50y is selected as the final output 50o, and as a result, a value of 3/4 of the input signal 50i is output.

Next, when the fade / mute value is 4, since the signal 50M2 is 1, the switch circuit 50s outputs the output signal 50M2.
g, the output signal 50g is delayed by two data latch stages (two stages of 50d and 50f) with respect to the input signal 50i. As a result, the output signal 50g of the output signal 50g shown in FIG. It is output at the timing, which means that the input signal 50i is output as it is.

When the input signal 50i and the output signals 50e and 50g are viewed as output timings, the input signal 50i corresponds to exactly 1/4 of the input data value.
50e is equivalent to 1/2 and output signal 50g is equivalent to 1/1. Multiplication operation is executed in 1/4 steps from 0 to 1 by adjusting the addition operation with an AND circuit and an adder. It will be done. In the case of the fade-out processing, the mute / fade control section 9 outputs the mute / fade control value 91 or 92 in the order of 4 → 3 → 2 → 1 → 0, for example, sequentially every 0.1 second, so that the whole is output in 0.4 seconds. The sound gradually decreases, and finally silences. In the case of fade-in, on the contrary, the output sound can be gradually increased by sequentially increasing the value in the order of 0 → 1 → 2 → 3 → 4.

As described above, the multiplier for the fade / mute operation is constituted, and the output sound can be output at an appropriate attenuation rate. The above-described calculation is performed for both the L channel and the R channel by the multipliers 51 and 52, and a signal 510 is output as an L channel output and a signal 520 is output as an R channel output.

The 1-bit 2-1 selector 6 switches the signals 510 and 520 input thereto at appropriate timings and outputs them, and outputs the final output audio data 600 in the same timing format as in the prior art. Is output. This switching operation is controlled by a signal 72 from the timing control unit 7.

Next, the operation of the above series of operations will be described with reference to an example. FIG. 8 shows an example in which A data and B data pairs are stereo-output as output audio data 600. Each data shows only the type of A data to D data and their time position, and is not shown as bit data. However, each of them is actually transmitted as bit data sequentially from the LSB side as already described. Is what it is.

First, the 4-1 selectors 31 and 32 are connected to the signal line 220 in order to select and output the A data as the L channel output.
Is selected, and as a result, the audio data on the signal lines 310 and 320 is
It is output at the timing shown in (b). Since the addition result of the adder 41 is the average value of the same A data, the data is output as it is as A data, and after performing a fade / mute operation in the multiplier 51, the data is supplied as L channel audio data to the signal line 510. Is output.

Similarly, in order to selectively output B data as an R channel output, 4-1 selectors 33 and 34 are connected to signal line 230.
Is selected, and as a result, the audio data on the signal lines 330 and 340 is
It is output at the timing shown in (c). Since the addition result of the adder 42 is the average value of the same B data, the data is output as it is as the B data. After the fade / mute operation is performed by the multiplier 52, the data is output to the signal line 520 as the audio data of the R channel. Is output. Then, 2-1 selector 6
Is output as output audio data 600 shown in FIG. 8 (d) by appropriately switching and outputting the signal lines 510 and 520.
The timing control output signal for data identification shown in FIG.
7 is output from the timing control unit 7 so as to synchronize with the output audio data 600, whereby the target output audio data is output as shown in FIG.

FIG. 9 shows A + as L channel data.
Consider a case where a C (average value of A data and C data) signal and a B + D (average value of B data and D data) signal are output as R channel data. In this case, since the audio data of the L channel is an average value of the A data and the C data, the A data of the signal line 310 shown in FIG. 9B and the C data of the signal line 320 shown in FIG. The 4-1 selectors 31 and 32 are controlled by the control signal 81 from the audio selection control unit 8 so as to be selected.
And 82. That is, the 4-1 selector 31 selects the signal line 220, and the 32 selects the signal line 100. Then, after the average value of both data is calculated by the adder 41, the A + C signal is output to the signal line 510 as an L channel signal after the fade / mute processing is performed.

Similarly, since the R channel data is an average value of the B data and the D data, the signal line shown in FIG.
The 4-1 selectors 33 and 34 are controlled by the control signals 83 and 84 from the audio selection control unit 8 so that the B data 330 is selected from the D data on the signal line 340 shown in FIG. . That is, the 4-1 selector 33 selects the signal line 230, and the 4-1 selector 34 selects the signal line 210. Then, after the average value of both data is calculated by the adder 42, the fade-mute processing is performed, and then the B + D signal is
Is output as an R channel signal.

Thereafter, the 2-1 selector 6 sets the L level of the signal line 510 to L.
By appropriately switching and outputting the channel signal and the R channel signal on the signal line 520, it is output as output audio data 600 shown in FIG. 9 (h), and the timing control output signal 700 for data identification is synchronized with the output audio data 600. Is output from the timing control unit 7 so that target output audio data is output.

Next, the amount of reduction in circuit scale in this embodiment will be described. For this purpose, the circuit scale according to the conventional example is first roughly calculated for the case shown in FIG.

The 16-bit registers 251 to 254 are each 112 gates. This is because a 1-bit data latch normally corresponds to 7 gates. 16-bit 4-1 selector 35
1 to 354 are 64 gates each, which is 1-bit 4-1.
This is because the selector usually corresponds to four gates. The 16-bit adders 451 and 452 usually require about 200 gates, and the multipliers 551 and 552 usually require about 1000 gates. Therefore, the total size is 3104 gates. In this calculation, those in the same use state as the conventional example and the present embodiment are excluded.

On the other hand, according to the present invention, as shown in FIG. 1, 1-bit shift registers 21 to 23 are each 112 gates, and 1-bit 4-1 selectors 31 to 34 are each 4 gates.
The adders 41 to 42 each have 32 gates, and the multipliers 51 and 52 each have 112 gates, for a total of 640 gates. Therefore, when comparing by gate size, 2464 gates can be saved, and in fact, 1/5
Exactly the same operation can be performed with the following hardware scale.

Next, another embodiment of the average value adder will be described. In the above-described audio data processing apparatus, the operation of the adder for calculating the average value was performed by clearing the carry input terminal C _in to 0 during the LSB calculation as shown in FIG. It is also possible to do. With this configuration, it is possible to perform a rounding operation from the least significant bit at the time of rounding the 16 significant bits out of all 17 bits of the calculation result during the average value calculation.

In the first embodiment, since the carry input terminal C _in is always cleared to 0, the operation is always a truncation operation of the LSB operation value.
When the value is set to, the round-up operation is possible, and in an operation requiring precision, an operation equivalent to the rounding operation of the decimal number operation becomes possible. In terms of hardware, it is only necessary to clear the carry input terminal _Cin to 0 at the time of the LSB operation from the first embodiment by simply setting it to 1, and it can be easily realized without an increase in hardware.

It is particularly important for the multipliers 51 and 52 for the fade / mute operation to increase the accuracy of the operation. As described in the first embodiment, according to the present invention, the same adder is used as the multiplier, and high precision is required as the bit operation amount increases.

Next, another embodiment of the multiplier for fade / mute operation will be described. In the time-series data processing device described above, the multipliers 51 and 52 for the fade / mute operation use the 1/4
Although the amount of attenuation is controlled in steps, the present invention is not limited to this, and it is easy to increase the number of steps in units of 2N. This is because, as shown in FIG. 10, in the multipliers 51 and 52 shown in FIG.
The AND circuit 50j, the adder 50k, and the D flip-flop circuit 50l shown in FIG. 1 may be increased by one each, and the accuracy can be increased very simply. In this case, the increase of hardware is only about 13 gates every time the number of steps is doubled, which is extremely small.

When the number of steps of the multiplier is increased to increase the accuracy according to this example, the number of addition operations increases. Therefore, the rounding operation of lower bits according to another embodiment of the adder described above is used together. It is clear that a more accurate fade / mute operation becomes possible.

In the time-series data processing apparatus according to the present invention, two of the four types of input audio data (A data to D data) are used by using the two average value operation adders 41 and 42. All combinations of data can be operated. However, this adder and 1-bit 4-1 selector are
By increasing the number of pairs, the average value calculation can be easily extended to a combination of appropriate data types.

This extensibility will be described with reference to FIG. FIG. 11 shows a configuration in which an adder extension circuit 30u is further added to the configuration of the average value calculation unit for two data in the time-series data processing device according to the present invention. With such a configuration, calculations of three types of data can be easily performed.
For example, when it is desired to perform an operation on A data, B data, and C data, the 4-1 selector 30a shown in FIG.
If each data of C is selected from the data bus 111, A + B +
The calculation of C is performed, and as a result, the addition result is output to the signal line 300u. The operation itself of this addition operation is as described in the previous embodiment.

As described above, if the number of data processing units 30u is increased one after another, it is possible to easily increase the number of addition operation data such as addition of four types of data. When performing the average value calculation, it is naturally necessary to divide the addition result by the number of data to be added. However, the operation itself can be easily performed by a multiplier at the subsequent stage. It is possible to simplify the circuit for division by providing the mute operation circuit with the fade / mute operation function and the average value function.

For example, when calculating the average value of three values, if the calculation in the multiplier is 5/16, it is almost equal to the calculation of 1/3, and the multiplier calculation step is further reduced to, for example, 11/32 ,twenty one
Sufficient accuracy can be obtained by performing calculations using approximation coefficients obtained in the same manner, such as / 64. Of course, as shown in the embodiment of the time series data processing apparatus according to the present invention, it is possible to output the average value by the timing control of the addition circuit itself, but in this case, the division is performed by data shift. Therefore, it is necessary to select the number of data to be a multiple of two.

In the embodiment of the time-series data processing device according to the present invention, the description has been made of the configuration having the data select function, the average value calculation function, and the fade / mute calculation function.
Naturally, an appropriate combination such as only the data select function or only the data select function and the average value calculation function can be easily realized, and even in this case, the circuit size is smaller than that of the conventional configuration and the cost is lower. It is clear that this is possible.

In the embodiment of the time series data processing apparatus according to the present invention, the data latches 40i and 40k are used in the sign extension operation as described with reference to FIG. 4 for the configuration of the adder. Is shifted by one bit, the shift data corresponding to the timing in the 16-stage shift registers 21, 22, and 23 in FIG. 1 may be used. Further reduction can be achieved.

In other words, in addition to the 1-bit 4-1 selector for data, a data line is extracted from a position corresponding to one bit ahead of the equivalent data, and the data used for the sign extension operation by the similar 4-1 selector or the like. It is apparent that the function equivalent to the above can be achieved by separately selecting and inputting to the adder and using it instead of the data latch output for sign extension operation. At this time, as described with reference to FIG. 3, the 1-bit data shift register merely outputs the data latch output in the middle of the data latch column to newly output the data in the middle of the shift. It can be realized without.

In this case, the number of data latches is increased by four and the number of one-bit selectors is increased by four as compared with the embodiment of the time-series data processing device of the present invention. Since the bit 4-1 selector has approximately four gates, the circuit scale can be reduced. Naturally, this can be applied to the multiplier of the embodiment of the time-series data processing device of the present invention, and a further effect is obtained when the calculation accuracy is high, that is, when the number of internal adders is large. It is clear that

In the embodiment of the time-series data processing apparatus of the present invention, in addition to the audio data shown in Table 1, it is possible to output a suitable combination of two data including a single data. As the data and the R channel, a combination output such as C + D data other than those shown in Table 1 was possible. For this reason, 1-bit shift registers 21 to 23 and 1-bit 4-1 selectors 31 to 34 are required. However, when all combination outputs of two data are not required and only a specific combination output is required, further change is required. Circuit reduction becomes possible.

For example, during the necessary combination output, if no signal line 230 is used in FIG.
The stage shift register 23 becomes unnecessary, and therefore, the signal line 230 becomes unnecessary. Similarly, 1-bit 4-1 selectors 31 to 34
In the case where only the signal lines 100 and 210 are used for the 4-1 selector 31 during the necessary combination output, the selector 2-1 may be used and the circuit scale can be reduced accordingly. Is clear.

In each of the above-described embodiments, the bit clock required for each operation may be externally input together with the transmission data, or a clock generation circuit for generating an operation clock from the transmission data including the timing control input may be provided. These may be provided, which are generally performed in a digital data processing device, and the operation and effect of the time-series data processing device of the present invention are not changed by any method. In this embodiment, m = 16,
Although n = 4 and k = 2, the values are not limited to these values. Further, in the present embodiment, audio data is processed, but similar effects can be obtained with similar data other than audio data.

[0111]

As described above in detail, according to the present invention, not only can the conventional audio data processing apparatus be realized with a circuit size of 1/5 or less, but also the number of data to be handled and the average value calculation can be changed. Various changes in design, such as changes in accuracy, data type for average value calculation, change in number of steps for fade / mute processing (change in calculation accuracy), etc. Moreover, there is an effect that it is possible to cope without newly changing other parts of the target circuit.

Further, according to the present invention, the number of wirings can be greatly reduced. In the conventional example, the number of data buses is 64. However, according to the present invention, the number of data buses can be reduced to only four, and there is an effect that it can be realized with a wiring scale of 1/16. This is because the circuit board size can be significantly reduced with the circuit size reduction, and the LS
In the case of I, the chip area can be reduced, so that the cost can be reduced.Because the number of wirings is small, the operation failure rate due to disconnection, short circuit, etc. is reduced, the failure rate is reduced, and the yield is improved. Has an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a time-series data processing device according to the present invention.

FIG. 2 is an explanatory diagram of an operation of a 1-bit 16-stage shift register.

FIG. 3 is a block diagram of a 1-bit 16-stage shift register.

FIG. 4 is a block diagram of a 1-bit adder;

FIG. 5 is an explanatory diagram of the operation of a 1-bit full adder.

FIG. 6 is a block diagram of a 1-bit multiplier.

FIG. 7 is an explanatory diagram of the operation of the 1-bit multiplier.

FIG. 8 is an explanatory diagram of the operation of the time-series data processing device.

FIG. 9 is an explanatory diagram of the operation of the time-series data processing device.

FIG. 10 is a block diagram showing another configuration of the 1-bit multiplier.

FIG. 11 is a block diagram showing another configuration of the 1-bit adder.

FIG. 12 is a block diagram of a conventional audio data processing device.

FIG. 13 is an explanatory diagram of an input data format of a conventional audio data processing device.

FIG. 14 is an explanatory diagram of a parallel-serial data conversion operation of a conventional audio data processing device.

FIG. 15 is an explanatory diagram of an operation of a conventional audio data processing device.

[Explanation of symbols]

10 Input audio data, 1 serial converter, 21, 22, 23
1-bit 16-stage shift register, 31, 32, 33, 34 1-bit 4-input / 1-output selector, 41, 42 adder, 51, 52 multiplier, 61-bit 2-input / 1-output selector, 7 timing controller, 40i, 40k data latch (1-bit delay)
, 40j, 40m switch circuit, 40h adder body, 40g
Data latch (1-bit delay), 50d, 50f Data latch (1-bit delay), 50a, 50b AND circuit, 50c
Adder, 50s switch circuit.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Haruhisa Inoue 1 Baba Zujo, Nagaokakyo-shi, Kyoto Prefecture Mitsubishi Electric Engineering Co., Ltd.Kyoto Office (72) Inventor Tetsuo Ishiwatari 1006 Kazuma Oazadomo, Kadoma City, Osaka Matsushita Electric Within Sangyo Co., Ltd. (72) Inventor Toshihide Ishimoto 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Hidemi Oka 1006 Okadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (58 ) Surveyed field (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/14 H03M 9/00

Claims (11)

(57) [Claims] 1. One channel is m bits (m is a natural number)
A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission path for time-division transmission of n channels (n is a natural number) A parallel-serial converter for converting the data into bit serial data, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter is to be inputted, and the parallel-serial conversion A plurality of 1-bit selectors for selectively selecting output data of the shifter and output data of the shift register, and an output switching unit for selectively selecting output data related to output data of the plurality of 1-bit selectors
A time-series data processing device comprising: a bit selector; and a timing control unit that controls operation timing of the parallel-serial converter, the shift register, and the output switching 1-bit selector. 2. One channel is m bits (m is a natural number)
A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission path for time-division transmission of n channels (n is a natural number) A parallel-serial converter for converting the data into bit serial data, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter is to be inputted, and the parallel-serial conversion A plurality of 1-bit selectors for selectively selecting the output data of the shifter and the output data of the shift register; and k (k is a natural number) output data of the 1-bit selectors, and the full addition of 1 bit is performed by m + k.
An adder for performing a single addition operation, an output switching 1-bit selector for selectively selecting output data of the plurality of 1-bit selectors or output data of the adder, the parallel-serial converter, A time-series data processing device comprising: a shift register; and a timing control unit for controlling operation timing of an output switching 1-bit selector. 3. One channel is m bits (m is a natural number)
A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission line for time-divisionally transmitting time-series data of n channels (n is a natural number). A parallel-serial converter for converting the data into serial data of bits;
A shift register formed by cascade-connecting n-1 stages of m-bit shift registers to which output data of the serial converter is to be input, and output data of the parallel-serial converter and output data of the shift register are selectively selected. And a plurality of one-bit selectors, and output data of the one-bit selector, and at least two data in a data sequence for each one-bit delay of the output data, are logical product of each bit data and a constant bit And find the result as 1
A multiplier for performing a full addition for each bit to calculate a multiplication of the output data and a constant bit;
An output switching 1-bit selector for selectively selecting output data of a bit selector and output data of a multiplier, and timing for controlling operation timings of the parallel-serial converter, the shift register, and the output switching 1-bit selector. A time-series data processing device comprising: a control unit. 4. One channel is m bits (m is a natural number)
A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission path for time-division transmission of n channels (n is a natural number) A parallel-serial converter for converting the data into bit serial data, a shift register formed by cascading n-1 stages of m-bit shift registers to which output data of the parallel-serial converter is to be inputted, and the parallel-serial conversion A plurality of 1-bit selectors for selectively selecting the output data of the shifter and the output data of the shift register, and the output data of the k 1-bit selectors are input, and 1-bit full addition is performed m + k-1 times, and the addition operation is performed. And the output data of the 1-bit selector or the output data of the adder are input, and 1 bit of the input data is input. A multiplier for calculating a logical product of each bit data and a constant bit with respect to at least two data in the data sequence for each delay, and performing a full addition of the obtained results on a bit-by-bit basis; An output switching 1-bit selector to which at least two or more of the output data of the plurality of 1-bit selectors, the output data of the adder, or the output data of the multiplier are input, and the input output data is selectively selected. And a timing control unit for controlling operation timing of the parallel-serial converter, the shift register, and the output switching 1-bit selector. 5. A first delay unit for delaying an adder by one bit with respect to each of two input data, and a switch circuit for switching output data of the first delay unit and the input data, The switch circuit operates so as to output the input data from the first bit to the m-th bit of the input data, and to select the output data of the first delay unit at the (m + 1) -th bit. A full adder that performs full addition with input bits and outputs the operation result as a carry output bit and an addition result bit; 0 or 1 is output in the first bit; 5. The time-series data processing device according to claim 2, further comprising a second 1-bit delay unit that delays a carry output bit by one bit and outputs the carry input. 6. A time-series data processing apparatus for selecting, processing, and outputting time-series data of an appropriate channel from a transmission path in which time-series data in which one channel is 16 bits is time-divisionally transmitted on four channels. A parallel-serial converter for converting the time-series data of the channel into 16-bit serial data, a shift register formed by cascading three stages of 16-bit shift registers to which output data of the parallel-serial converter is to be input, Four 1-bit selectors for selectively selecting output data of the parallel-serial converter and output data of the shift register;
Two sets of adders, to which two different output data from the 1-bit selector are input, perform a full addition of 1 bit 17 times to perform an addition operation, and output data of each of the two sets of adders by 1
A logical product of each bit data of the data sequence for each bit delay and a constant bit is calculated, and the obtained results are subjected to full addition on a bit-by-bit basis and multiplied. The output data of each multiplier is alternatively selected. 1. A time-series data processing device comprising: a 1-bit output switching 1-bit selector, and a timing control unit that controls operation timings of the parallel-serial converter, the shift register, and the 1-bit selector for output switching. . 7. A multiplying device comprising: an input bit data; a delay device for delaying the input bit data by one bit; and the delay devices are connected in cascade at a plurality of stages, and the input bit data and the output data of each delay device are mutually connected. A logic circuit for obtaining a logical product of each of the plurality of independent variable constant bits, an adder for adding each output data of the logic circuit, and a maximum delay data of the output data of the adder and the output data of the delay unit 7. The time-series data processing device according to claim 3, wherein said switching circuit is configured by a switch circuit for selecting said data by variable constant bit data. 8. A first delay device for delaying an adder by one bit with respect to each of two input data, and a switch circuit for switching between output data and input data of the first delay device, The switch circuit operates so as to output the input data from the first bit to the 16th bit of the input data, and to select and output the output data of the first delay unit at the 17th bit. A full adder that performs full addition of two output data and a carry input bit and outputs an operation result as a carry output bit and an addition result bit; 0 or 1 is output as a first bit, and a second bit is output. 7. The time-series data processing apparatus according to claim 6, further comprising a second 1-bit delay unit that delays the carry output by one bit and outputs the carry input. 9. One channel is m bits (m is a natural number)
A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission path for time-division transmission of n channels (n is a natural number) A parallel-serial converter for converting the data into bit serial data, a shift register in which 1 × bit shift registers to which output data of the parallel-serial converter are inputted are connected in cascade of m × (n−1) stages; A plurality of 1-bit selectors for selectively selecting the output data of the parallel-serial converter and the output data of the shift register, and two different output data of the 1-bit selector are inputted, and each of the data is inputted. A switch circuit for switching between data delayed by one bit and data input from the one-bit selector. The switch circuit outputs the input data from the first bit to the m-th bit of the input data, operates to select the output data of the first delay unit at the (m + 1) th bit, and outputs two output data from the switch circuit. A full adder that performs full addition of a carry output bit and a carry output bit and outputs the operation result as a carry output bit and an addition result bit, outputs 0 or 1 in the first bit, and outputs An adder that includes a 1-bit delay unit that delays the carry output by 1 bit and outputs a carry input, and performs 1-bit addition;
An output switching 1-bit selector for selectively selecting output data of a 1-bit selector or output data of the adder, the parallel-serial converter, a shift register,
A time-series data processing device comprising: a timing control unit that controls operation timing of the adder and the output switching 1-bit selector. 10. Time-series data in which one channel is m bits (m is a natural number) is converted into n channels (n is a natural number).
A time-series data processing device that selects, processes, and outputs time-series data of an appropriate channel from a transmission line that is time-division-transmitted, and a parallel-serial converter that converts the time-series data into m-bit serial data. A 1-bit shift register to which output data of the parallel-serial converter is input is connected in a cascade of m × (n−1) stages, and the output data of the parallel-serial converter and the shift register A plurality of 1-bit selectors for selectively selecting output data, two different output data of the 1-bit selector being input, data delayed by 1 bit with respect to each of the data, and the 1-bit selector And a switch circuit for switching between the input bit data and the input data. Et until the m-bit outputs input data, the m +
Operates to select the output data of the first delay unit as the first bit, performs a full addition of the two output data of the switch circuit and the carry input bit, and outputs the operation result as the carry output bit and the addition result. A full adder that outputs 0 or 1 as the first bit, and a 1-bit delayer that outputs the carry input by delaying the carry output bit by 1 bit from the second bit onward. And an adder that performs 1-bit addition, and the output data of the 1-bit selector or the output data of the adder are input, and at least two data in a data sequence for each 1-bit delay of the output data A multiplier for calculating the logical product of each bit data and a constant bit, performing a full addition on a bit-by-bit basis and calculating a multiplication, and output data of the plurality of 1-bit selectors or the adder At least two or more of output data or output data of a multiplier are input, and an output switching 1-bit selector for alternatively selecting a plurality of input data, the parallel-serial converter, the shift register, A time-series data processing device, comprising: a timing control unit that controls an operation timing of an adder, the multiplier, or the output switching 1-bit selector. 11. A time-series data processing device for selecting, processing, and outputting time-series data of an appropriate channel from a transmission line for transmitting time-series data in which one channel is 16 bits through time-division transmission of four channels, A parallel-serial converter for converting the time-series data of the channel into 16-bit serial data, a 48-bit shift register to which output data of the parallel-serial converter is input, and output data of the parallel-serial converter. Four 1-bit selectors for selectively selecting the output data of the shift register; and two different output data of the 1-bit selector, which are input and delayed by one bit with respect to each of the data. , A switch circuit for switching between data inputted from the 1-bit selector and the switch circuit, Input data is output from the first bit to the 16th bit of the output bit data, and operation is performed to select data delayed at the 17th bit. A full adder that performs full addition and outputs an operation result as a carry output bit and an addition result bit; a 0 or 1 is output as a first bit, and the carry output bit is 1 after a second bit. A 1-bit delay unit that outputs a carry input with a bit delay and performs 1-bit addition 2
For each set of adders and the output data of the two sets of adders, the logical product of each bit data of the data sequence for each 1-bit delay and a constant bit is obtained, and the results are compared for each bit. A multiplier for performing a multiplication by performing a full addition, an output switching 1-bit selector for selectively selecting output data of each multiplier, the parallel-serial converter, the shift register, the adder, and the multiplication A time control unit for controlling the operation timing of a filter or an output switching 1-bit selector.