JP3097479B2 - Magnetic recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a helical scan type magnetic recording / reproducing apparatus such as a VTR (Video Tape Recorder), and more particularly, to economical use of a motor servo circuit of a general magnetic recording / reproducing apparatus which is widely used at home. Moreover, it is realized with good performance.

[0002]

SUMMARY OF THE INVENTION The present invention efficiently combines a microprocessor and a digital filter circuit, and further smoothly shifts the operation of the system so that rewriting of a memory means serving as an intermediary between them is not burdened on the microprocessor. Do so. The operation is further improved by adding a simple limiter circuit to each section of the digital filter. Further, when timing control such as splicing is important, the rewriting process of the memory means is skillfully performed, and the processing is realized with high accuracy and simple processing.

[0003]

2. Description of the Related Art A conventional technique relating to servo gain control is disclosed in Japanese Patent Application Laid-Open No. 61-276158. As disclosed in this document, there is a technique in which a disturbance component is detected and the terminal of an analog filter is switched to increase a gain of a servo loop or extend a frequency characteristic. Japanese Unexamined Patent Publication (Kokai) No. 58-186274 discloses a technique in which very complicated control of various types of motors and actuators is all processed by one microprocessor. is there. Further, as a prior art relating to splicing, there is one disclosed in Japanese Patent Publication No. 49-18805.

[0004]

However, in the case of the former technique, the former requires a disturbance detecting means, and has an economical problem that an analog filter and an analog switching circuit are not suitable for IC integration. In this case, since the microprocessor is involved in every process, the servo processing occupancy increases and the load on the processing time is heavy. Conversely, when the processing time is severe, the control is limited to coarse control. There was a problem that required a lot of labor. Further, as for the splicing, there is an example which is realized by a conventional analog circuit or the like, but it has no versatile structure as in the present invention, and the control frequency is fixed at the time of reproduction and recording.

[0005]

[Means for Solving the Problems] In order to solve the above-mentioned problems
In addition, the present invention relates to a motor control for performing phase control and speed control.
In a magnetic recording / reproducing device having a control device,
Means for detecting the rotational speed and rotational phase, respectively, and
Detect speed error from digitally converted rotation speed
Means and phase from rotational phase digitally converted after detection
Error detection means and the digital amount of phase error
The first digital filter means for calculating the speed
The digital amount of the difference and the output of the first digital filter means
Second digital filter that performs filter operation based on force
Filter means and filters of the first and second digital filter means.
Memory means for storing filter characteristics;
And the rotation speed and rotation phase of the motor described above, respectively.
Detection operation of the detection means and conversion operation to digital quantity
In parallel with the operation,
On the basis of the above-mentioned converted value to digital quantity.
Rewrite the contents of the memory means every time a fixed time elapses
And a processor.
Also, the present invention provides a motor control for performing phase control and speed control.
In a magnetic recording and reproducing apparatus having a control device,
Means for detecting the rotation speed of the motor, and the detected speed
Frequency dividing means for dividing the signal by N (N is an integer of 1 or more);
Synchronized to either the first reference signal or the second reference signal
Control that is preset and played from the tape.
Signal or the output of the frequency dividing means described above.
Therefore, the phase difference between the two is decoded by the latched counter.
Digital phase conversion means for converting to a digital amount;
Divided N times and cyclic count of the second reference signal described above.
Memory means for storing and controlling the number M (an integer of 1 or more)
And the output of the phase conversion means.
Means for controlling the phase of the motor, and the first reference
When switching from the signal to the second reference signal,
Digital phase conversion output is almost unchanged and continuous
As described above, the cyclic count number M of the second reference signal is reduced.
Microprocessor that changes from threshold value M0 to large value M1
Are provided .

[0006]

The microprocessor reduces the load on the microprocessor by monitoring only the operating speed and phase of the object to be controlled when necessary. In addition, the entirety is built in a digital circuit in an IC of the same chip to improve the above-mentioned another problem, namely, economy.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, description will be made below with reference to specific embodiments. Generally, in a magnetic recording / reproducing apparatus that records and reproduces a video signal, phase synchronization servo (phase control) for synchronizing with the video signal and speed control for quick control are performed in parallel. This takes a form almost common to the servo for the rotating head for the image and the servo for the tape drive. FIG. 1 shows an example in which the present invention is applied to a drive system of a drum motor (element 11) equipped with a rotary head in a magnetic recording / reproducing apparatus, and FIG. 2 shows an example in which the present invention is applied to a tape drive system.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a control unit, 2 is a microprocessor,
3 is a memory area, 4 is a speed error detection circuit, 5, 6, and 7 are digital filters, 8 is an adder, 9 is a phase error detector, 10 is a motor driver, 11 is a drum motor, 12
Is a phase signal generator, 13 is a speed signal generator, 20 is a limiter, 52 is a digital / analog converter (D / A converter), and 41 and 45 are voltage signals.

The operation will be described below. First, a high-frequency signal and a relatively low-frequency rotation phase signal are generated from the drum motor 11 in synchronization with the rotation. These are generated by the speed signal generator 13 and the phase signal generator 12, respectively. These are amplified and shaped as necessary (these are omitted here), and then applied to a speed error detection circuit 4 and a phase error detection circuit 9 which are digital time measuring means. The detailed operation by these elements will be described later, and the obtained error data is filtered by digital filters 5 and 7, respectively. Further, these data are added to each other by the adder 8 and finally filtered by the digital filter 6. Since the digital measurement result is basically a counter measurement result and a periodic repetition pattern, the output data is appropriately limited by the element 20. That is, when a partial value is taken out of the periodic repetitions (as shown at 44 in FIG. 4), this is output, and in other cases, the output is fixed to high or low. The range of values to be output monitors the higher order of the filter output. The speed error detection circuit 4 is configured so that the counter circuit 24 of FIG. 3 is stopped (not shown for simplicity) so as not to have an extremely large value. The digital filters 5, 6, and 7 are provided so as to cut off the high frequency band while increasing the low frequency gain and perform servo control with a small and stable steady state deviation. It can be omitted as appropriate, and in many cases the element 5 is omitted. The output of limiter 20 is converted by element 21 into an analog quantity. All of the processing up to this point can be digital processing, so that it can be integrated, producing a number of advantages as described above. After the above processing, the drum motor 11 generates torque according to the voltage applied to the motor driver 10. The outline of the control of the drum motor 11 has been described above. What is important here is that the characteristics of the digital filters 5, 6, 7 and the operating points of the error detectors 4, 9 are set by data from the memory area 3. In addition, this setting can be determined by the minimum necessary setting operation by the microprocessor 2 (extremely, only the initial setting). Therefore, there is no need to rewrite the contents of the memory area unless it is desired to intentionally change the characteristics (described in detail later). However, in this embodiment, a monitoring route of the speed and phase error data by the microprocessor is provided in order to avoid a prolonged transition time to the stable state due to the interaction between the speed control and the phase control at the time of startup.

On the other hand, the tape is driven by a capstan shaft that sandwiches and drives the tape together with a rubber pinch roller. FIG. 2 shows an example in which the present invention is applied to a capstan motor system. In the figure, 19 is a capstan motor,
16 is a control head, 17 is a magnetic tape, 14,
15 is a frequency divider, 18 is a pinch roller, and 51 is a changeover switch. In addition, the other 'numbers' indicate that the elements correspond to the element numbers in FIG. The outline of the control in this embodiment is almost the same as that in FIG. The difference is roughly the target signal of the phase control and the control at the time of quick reference at the time of reproduction.

The former compares the phase of the frequency-divided signal with the reference signal during recording, and the control head 1 during reproduction.
6 is to be subjected to phase comparison with the control signal and the reference signal reproduced from the control signal. The latter uses a frequency divider 1 for dividing the frequency signal and the phase signal because the tape traveling speed is a multiple of the recording speed at the time of quick playback.
4 and 15 are provided so that the number of divisions and the multiple of the tape speed are controlled to be equal. For this reason, the changeover switch 51 is connected to the a side during recording and to the b side during reproduction. In this embodiment, it is assumed that the frequency signal has a frequency that is an integral multiple of the reference signal, and a frequency division ratio corresponding to the multiple is set in the frequency divider 15.

Next, the speed and phase control will be described in detail with reference to FIG. FIG. 3 shows an internal configuration of the speed error detection circuit 4 and the phase error detection circuit 9 in the embodiment of FIG. In the figure, 21 and 31 are edge detection circuits, 22, 32,
37 is a pulse generation circuit, 23 and 33 are preset circuits,
24 and 34 are counter circuits, 25 and 35 are latch circuits,
26 and 36 are error calculation circuits, 27 is a clock generation circuit,
38 is a reference signal generation circuit, 41 to 43 and 45 to 48 are electric signals. Now the frequency of the clock generation circuit is C,
When the frequency of the frequency signal 41 at the time when the drum motor rotates at a predetermined number of rotations is f, the design is made so that C / f is at the middle point of the output range. This coincides with the case where the voltage obtained by directly converting the output of the error calculation circuit 26 into the analog amount by the D / A converter 52 becomes the center of the operating point. Further, regarding the phase control, the reference signal generator 38 is used.
And the phase signal 45 from the drum motor 11 have a predetermined phase (the head position comes to a predetermined position) so that the output of the phase error calculation circuit 36 becomes zero. To

A more detailed description will be given below with reference to waveform diagrams of main parts in FIGS. In the figure, reference numerals 41 to 43, 45 to 48 denote electric signals, and reference numerals 44 and 49 schematically denote count values of the counter circuits 24 and 34. First, the conversion of the frequency signal, that is, the speed control operation will be described. The rising edge of the frequency signal 41 is detected via the edge detector 21 and the pulse detector 2
2 is applied. Then, the pulse generator 22 generates a series of pulse signals 43 and 42 synchronized with the rising edge of the signal 41 in synchronization with the clock signal. These signals 43 and 42 are the latch pulse of the latch circuit 25 and the preset circuit 2 respectively.
3 preset pulses. The value 4 of the counter circuit 24
4 is preset by the pulse signal 42 and counting is started,
It is latched by the signal 43. The counter value 44 differs between (A), (A), (B), and (C) when the frequency signal is generated at a predetermined cycle as shown in (a), (b), and (c). The value to be set also becomes a middle point in a predetermined time, becomes large when it is late, and becomes small when it is early. This amount is converted into an analog amount, and is fed back to the motor to control the speed to be constant.

The operation at the time of phase control will be described with reference to FIG. Here, the latch pulse 48 and the preset pulse 47 are obtained from separate signals 46 and 45. Signal 4
Reference numerals 6 and 45 indicate the timings of the reference signal and the phase detection signal. If the predetermined phase difference, the phase difference is small, and the phase difference is large, the value 49 of the counter 34 becomes (d) (e) (f). An error calculation circuit 36 is provided so that latch data at a predetermined value becomes zero.
Can be converted to a minus value when the phase difference is small, zero when the phase difference is large, and a plus value when the phase difference is large. These speed control and phase control error signals (element 2
6, 36 outputs), a drum motor rotation at a predetermined speed and a predetermined phase can be obtained.

Next, the digital filter will be described in detail with reference to FIG. In the figure, 51, 51 ′, 52 ″, 5
3, 53 ', 53 "are arithmetic units, 52, 52', 52" are digital data holders, 54, 54 ', 54 ", 5".
5, 55 ', 55 ", 56, 56', 56" are integrators. Here, the arithmetic unit performs addition or subtraction of digital data. The retainer shifts in time every sampling. The integrator serves to multiply a certain coefficient. Figure 1
3 shows that the three digital filters 5, 6, and 7 are realized in the same format. Now, let the coefficient of the integrator 54 be A,
If the coefficient of the integrator 55 is B, the coefficient of the integrator 56 is C, and the time delay element by the holder 52 is represented by Z ~ ¹ , the transfer characteristic G of the digital filter 5 becomes

[0016]

G (Z) = C × (1 + A × Z ~ ¹ ) / (1 + B × Z ~ ¹ ), which indicates a first-order lag element of a discrete value system. Here, S = 2 × (1−Z ~ ¹ ) / Ts / (1 + Z ~ ¹ ), where Ts is a sampling period. Here, the coefficients A, B, and C are stored in the memory 3 and set by the microprocessor. For example, if A and B are zero and C is 1, the transfer function G =
It becomes 1 and the input of the filter is transmitted to the output as it is. If C = 0, the filter output will not be affected. Further, the cutoff frequency can be appropriately set according to the values of A, B, and C. As described above, various characteristics can be realized by variously setting the coefficients. According to the present example, the output of the digital filter can be effectively set according to the operation situation. For example, when starting the motor, it is not desired to be affected by the phase control until the motor approaches a desired frequency. Therefore, when the coefficients of the phase-based digital filter 7 are A ", B", and C ", the starting can be made smooth by setting the value of C" to zero. Then, when the frequency approaches the desired frequency, C ″ is reset. By changing the filter coefficient of the speed system at the time of start-up and at the time of steady state, the start-up is quick and the coefficient setting is stable at the time of steady-state. It is possible to monitor the frequency signal period indicating the motor speed at very coarse time intervals and rewrite the coefficient initialized at startup when the speed reaches the steady speed, and the load on the microprocessor is very small. Now, a specific example for realizing these characteristic changes will be described with reference to FIG.

In this embodiment, the digital filter of the speed control system is omitted for simplification. Integrators 54 ', 55',
The coefficients 56 ', 54 ", 55", and 56 "are A', B ', C', A", B ", and C", respectively. FIG. 8 schematically shows these set values from the time of startup on the vertical axis (the horizontal axis is time). At startup, A ", B", C "
Is set to zero, the phase control is cut, and A 'and B' are lowered to make the speed control filter lighter and the response is faster. Thereafter, when a predetermined period Tx is reached, both the speed and phase filters are activated, and the final coefficient in a steady state is set after a transition time ta. The coefficient at this time is written in the memory area 3 and is reset by rewriting the microprocessor. However, if there is a margin in the processing time, it can be changed to a division as shown by a broken line in FIG. .

As described above, one of the major features of the present invention is that the memory means and the microprocessor for controlling the memory means operate almost independently of the timing of the control circuit for controlling the motor (in extreme cases). Can be the same as the source clock). Therefore, since the motor control circuit operates in parallel with the microprocessor in time, it is possible to greatly increase other processes that can spend time in the microprocessor. This operation will be described with reference to the timing chart of the motor speed control shown in FIG.

In FIG. 9, 41 to 44 are electric signals also shown in FIG. 3, 70 is a counter preset value in FIG.
Reference numerals 71 and 72 denote time points, and reference numeral 73 denotes a speed control signal. Time point 7
Before 1 the preset value is P ₀ and thereafter the preset value is P ₁ .
Here, the speed control is performed by the preset signal 42 and the latch signal 43.
This is irrelevant to the timing 71 at which the preset value changes due to rewriting of the memory. In other words, changing the period T ₀ until it changes the preset value control system in a selfish timing after In other write memory contents at a proper timing. As described above, it is a great advantage that the contents of the memory can be updated without being conscious of the control timing, and the microprocessor can be operated without being conscious of the control of the motor. In the above case, the frequency signal period was monitored, and the coefficient initialized at startup was rewritten when the speed became steady.However, considering that the startup characteristics of the motor are almost constant every time, It is not always necessary to monitor the frequency signal period, and it is also possible to rewrite the above-mentioned memory contents after a certain time has elapsed from the start.
In this case, the microprocessor can concentrate on, for example, system control without being conscious of the rotation state of the motor.

However, in the case of performing fine timing control such as splicing, a more advanced circuit control is required. Hereinafter, a technique for skillfully implementing the present invention in splicing and shooting will be disclosed.

FIG. 10 is an explanatory diagram of capstan control at the time of splicing. In the figure, 13 'is a frequency signal generator synchronized with the capstan motor, 16 is a control head, 17 is a magnetic tape, 19 is a capstan motor, 8
0 is a portion where a video signal has already been recorded, 81 is a portion where a control signal (phase signal) has already been recorded, and 82 is an unrecorded portion. In general, the tape running phase is controlled so that the control signal on the tape during reproduction and the frequency-divided frequency signal of the capstan during recording are synchronized with a reference signal (video recording head and drum motor). Are synchronized with a reference signal during reproduction, and with a reference signal synchronized with a video signal to be recorded during recording.) Further, at the time of splicing, it is necessary to control the tape running phase while reproducing the already recorded portion 80, and to control the control signal so that the control signal continues even when the signal reaches the unrecorded portion. Otherwise, the control signal becomes discontinuous at the beginning of the newly recorded portion, causing phase disturbance. As a result, the reproduced image is violated by noise.)

In order to avoid the discontinuity of the control signal and the phase control signal, as a control means for performing a splicing operation, conventionally, a control signal to be recorded is used to instantaneously replace the capstan frequency signal with the control signal recorded. Means have been taken such as resetting the circumference or resetting the reference signal with the capstan frequency-divided signal. However, in a device modified such that the (pre) reset of the counter is performed at an arbitrary timing of the counter as in the present case, the conventional method cannot be used (synchronization cannot be performed). Therefore, this is made possible by the configuration and method disclosed below (and according to this, the phase control frequency can be appropriately selected at the time of recording).

FIG. 11 is an expanded view of the present invention applied to an apparatus for seamless shooting. In the figure, 31 'is an edge detection circuit, 32' and 37 'are pulse generators, 33' is a preset circuit, 34 'is a counter circuit, 35' is a latch circuit, 36 'is an error calculation circuit, and elements surrounded by broken lines. 100 is a phase error detection circuit, 101 is a reproduction reference signal generation circuit, 1
02 is a recording reference signal generation circuit, 103 and 105 are changeover switches, 104 is a frequency divider, 110 to 112 are data lines, and 113 to 120 are electric signals. Further, the same numbers as those in the above-described embodiment are added to the other elements.
Now, as a typical example, the field frequency of the video signal is 6
0Hz, control signal frequency during standard playback is 30H
z, the capstan frequency signal during recording / standard playback is 72
It is assumed that the frequency is 0 Hz. During playback, switch 103 is set to a
Side, the switch 105 is connected to the b side so that the signal 11
3, 114 are controlled. The elements 101 and 102 make a cycle according to the data of the data lines 111 and 112, respectively, and are preset to count repeatedly. That is, the generation frequency of the clock generation circuit 27 'is set to 5
MHz, Dp = 5 × 10 ⁶ /30=1.67×
What is necessary is to flow 10 ⁵ data to the data line 111. On the other hand, during recording, the signals 113 and 114 are controlled so that the switch 103 is connected to the b side and the switch 105 is connected to the a side. At this time, 720Hz generated in the element 13 '
Is appropriately divided by the frequency divider 104 (here, the division ratio N = 8), and a signal having a frequency of 90 Hz appears on the signal line 120. In this case, Dr = 5 × so that the recording reference signal generation circuit 102 also emits a 90 Hz signal.
The data of 10 ⁶ /90=5.55×10 ⁴ is the signal 112
Is set to As described above, the 30 Hz reference signal and the reproduction control signal are used during reproduction, and
The reference signal of Hz and the signal obtained by dividing the capstan frequency signal by 8 are controlled so as to be phase-synchronized. The problem is the moment when the state is switched from the reproduction state to the recording state. Element 101
Since the element 102 and the element 102 operate at different timings, a phase jump occurs at the moment when the state changes from reproduction to recording. Therefore, the contents of the memory area 3 'are controlled as described below.

The detailed operation will be described below with reference to the timing chart of FIG. In FIG. 12, as in FIG.
10 to 112, 131 are data lines, 113 to 120
Is an electric signal, 130 and 132 are values expressed with the numerical value (of the counter) on the vertical axis for convenience, and T3 and T4 are time points. As shown in the figure, the data Dp = 1.67 × 10
^{According to 5} , a signal 115 of 30 Hz is generated as a reproduction reference signal. First, before the time point T3, the minimum numerical value that can be set in the recording reference signal generating circuit 102 is given to the data line 112 (Dr = 1 in this example). Here, the recording reference signal generation circuit 102 generates a signal having an extremely short cycle. Next, after T3, Dr = 5.55 × 10 ⁴ . As a result, the value counted by the recording reference signal generation circuit 102 changes as indicated by 130. At this time, a pulse indicating that the count value has reached Dr (recording reference signal generation circuit 102
Can use a pulse that presets itself) on the signal 116. Now, after a period of 11, 1 milliseconds (hereinafter referred to as ms), which is the period after T3 of the signal 116, the switch 103 is switched from the side a to the side b at time T4 (by the signal 113). A signal 117 is obtained. The pulse generating circuit 37 'which receives this as an input outputs a signal 47'. Further, at time T4, the data 131 (Pp) changes from p1 to p2. As a result, while the counter circuit 34 'is preset by the preset circuit 33' by the signal 47 ', p1,
The counting operation of the counter circuit 34 'is performed using p2 as an initial value. Thus, the count value of the counter circuit 34 'is 1
32. On the other hand, the counter circuit 34 '
Is obtained as follows. That is, before the time point T4, the frequency division ratio n = 1, and after the time T4, the frequency division ratio n = 8.
Flow to 0. This is achieved by the microprocessor 2 writing this value to the memory area 3 'at time T4. As a result, before T4, the 720 Hz frequency signal itself,
After T4, the signal obtained by dividing this frequency by 8 (90 Hz) is the signal 1
18 is output. The changeover switch 105 is at time T4
The signal 114 connects to the b side before and to the a side after T4.
, The output 120 is obtained as shown in the figure (the control signal 119 which is a phase signal before T4).
Is applied). Finally, a signal 48 'which is an output through the edge detection circuit 31' and the pulse generation circuit 32 '
Can consequently latch a value approximately at the center of the operating point of value 132. In the above description, it is assumed that the phase control is performed at 90 Hz during recording. However, even when the phase control is performed at 30 Hz, Dr = 1.67 × 10 ⁵ , the dividing ratio n = 24, and the data 131 are always set to p1 during recording. Set the time difference of T4 to 33.
This can be dealt with by setting it to 3 ms.

As described above, the recording reference signal generating circuit 112
And the repetition cycle of the capstan frequency divider 104 is made sufficiently short in advance, and is rewritten to a predetermined value with an appropriate time difference at the moment of splicing to the frequency division ratio or the repetition count (contents of the memory 3 '). Can achieve the purpose. In other words, by making the cyclic period short enough at the beginning,
Next, the time until the repetition period is reset can be shortened, and the reproduction state can be shifted to the capstan phase control in the recording state at a desired timing, so that phase disturbance during the period does not occur.

Next, an example of a process for actually performing these processes will be described with reference to a process flowchart of FIG. As shown in the drawing, first, in the reproducing state, the magnetic tape is rewound by an amount sufficient to perform the phase control by both the drum and capstan motors. Next, after stopping, reproduction at the normal speed is started. Here, the phase of the drum motor is controlled so as to be synchronized with the vertical synchronization signal of the video signal to be recorded, and the phase of the capstan motor is controlled so that the reproduced control signal is synchronized with the reproduction reference signal. At this time, the recording reference signal and the frequency division ratio of the capstan frequency divider are set to values as small as possible (for example, Dr = 1, n
= 1). Also, the phase synchronization preset value P
Let p = p1. Next, Dr, which is the set value of the cyclic count number of the capstan recording reference signal, is set to 5.55 × 10 ⁴ , and at the same time, the timer is reset (TM = 0). When the timer reaches 11.1 ms, Pp = p2 and n = 8. Thereafter, the recording is actually started at an appropriate timing because the phase control of the recording state is performed for both the drum and the capstan.

In the above example, only two reference signal generation circuits (elements 101 and 102 in FIG. 11) are provided.
Of course, it is also possible to provide two sets of counters and latch groups and switch their outputs.

[0028]

As described above, according to the present invention, there is an economical effect that all the control units can be integrated into an IC and can be realized inexpensively and miniaturized. In addition, the performance can be improved by reducing the load on the microprocessor, and the microprocessor can have many functions. Furthermore, the microprocessor and the control parts such as the motor operate almost independently and in parallel, so that the processing efficiency is improved, and the program incorporated in the microprocessor is simplified and
This eliminates the need for a processing program that has difficult timing such as synchronization with the motor operation, thereby improving development efficiency.

In addition, the conventional splicing operation can be performed skillfully while the above-mentioned effects are produced, and there is an effect of ensuring performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is an internal block diagram of elements of one embodiment of the present invention.

FIG. 4 is a partial waveform diagram of FIG. 3;

FIG. 5 is a partial waveform diagram of FIG. 3;

FIG. 6 is an internal block diagram of another element of one embodiment of the present invention.

FIG. 7 is an internal block diagram of elements of another embodiment of the present invention.

FIG. 8 is a waveform diagram of a main part of FIG. 7;

FIG. 9 is a waveform diagram of a main part of FIG. 3;

FIG. 10 is a diagram of a connection shooting.

FIG. 11 is a block diagram of another embodiment of the present invention.

FIG. 12 is a waveform diagram of a main part of FIG. 11;

FIG. 13 is a flowchart for explaining the operation of the embodiment in FIG. 11;

[Explanation of symbols]

 2, microprocessor, 3, 3 ', memory area, 4, speed error detection circuit, 5, 6, 7, digital filter, 8 adder, 9 phase error detection circuit, 11 drum motor, 12 phase signal Generator 13 Frequency signal generator 19 Capstan motor 20 Limiter 38 Reference signal generation circuit 51 53 Operation unit 52 Holder 54 55 55 56 Integrator 102 Recording reference signal generation circuit.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yukinobu Tada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Video Media Research Laboratories (72) Inventor Hisashi Ota 1410 Inada, Hitachinaka-shi, Ibaraki, Japan In the Personal Media Equipment Division of Hitachi, Ltd. (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11B 15/52 G11B 15/46

Claims (10)

(57) [Claims] 1. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the motor and the rotational phase, respectively, after detecting di
Means for detecting speed error from digitally converted rotation speed
And phase error from the rotational phase digitally converted after detection
Means for detecting and a first digital filter means for the original to the operation of the digital quantity of the phase error, the speed
A second digital filter for performing a filter operation based on the digital amount of the degree error and the output of the first digital filter means
And Le filter means, said first, memory means for storing the filter characteristics of the second digital fill <br/> data unit, wherein the filter operation, each of the detecting means with the rotation phase and the rotational speed of the aforementioned motor A processor for rewriting the storage contents of the memory means every time a predetermined time elapses based on the converted value to the digital amount in parallel with the detection operation and the conversion operation to the digital amount. A magnetic recording / reproducing apparatus characterized by the above-mentioned. 2. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the motor and the rotational phase, respectively, after detecting di
Means for detecting speed error from digitally converted rotation speed
And phase error from the rotational phase digitally converted after detection
, A first digital filter means for performing a filter operation based on the digital amount of the phase error, a digital amount of the speed error and the first digital
Second for the original filter operation output Le filter means
A digital filter means, said first, second Digi
Memory means for storing the filter characteristics of the barrel filter means, said the filter operation, detecting operation of the respective detection means and the rotation phase and the rotational speed of the above-described motor, and in parallel with the conversion to a digital quantity, the A magnetic recording / reproducing apparatus, comprising: a microprocessor for rewriting the contents stored in a memory means in a stepwise manner from an initial value to a final value. 3. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the motor and the rotational phase, respectively, after detecting di
Means for detecting speed error from digitally converted rotation speed
And phase error from the rotational phase digitally converted after detection
Means for detecting and a first digital filter means for the original to the operation of the digital quantity of the phase error, the speed
A second digital filter for performing a filter operation based on the digital amount of the degree error and the output of the first digital filter means
And Le filter means, said first, memory means for storing the filter characteristics of the second digital fill <br/> data unit, wherein the filter operation, each of the detecting means with the rotation phase and the rotational speed of the aforementioned motor A motor control circuit unit for performing a detection operation, a conversion operation to a digital quantity, and the first and second filter operations described above, and a microprocessor for performing system control independently of the motor control circuit unit. A magnetic recording / reproducing apparatus for rewriting contents stored in the memory means from the microprocessor. 4. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the motor and the rotational phase, respectively, after detecting di
Means for detecting speed error from digitally converted rotation speed
And phase error from the rotational phase digitally converted after detection
, A first digital filter means for performing a filter operation based on the digital amount of the phase error, a digital amount of the speed error and the first digital
Second for the original filter operation output Le filter means
A digital filter means, said first, second Digi
The the original filter operation the output of the barrel filter means
3 digital filter means, and the first, second, and third digital filter means.
A motor control circuit having memory means for storing the filter characteristics of the digital filter means, and a microprocessor for controlling the system independently of the motor control circuit. A magnetic recording / reproducing apparatus, characterized by rewriting the stored contents of (1). 5. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the motor and the rotational phase, respectively, after detecting di
Means for detecting speed error from digitally converted rotation speed
And phase error from the rotational phase digitally converted after detection
Means for detecting the phase of the first digital filter means for the original filter operation the digital amount of error, the digital content and the first Digitally said speed error
Adding means of the output of the Le filter means, said second digital filter means for the original filter operation the output of the adding means, and the filter characteristics of said first, second digital filter means, first mentioned above The memory means for storing the addition ratio of the digital filter means and the value obtained by converting the rotation speed into a digital amount,
A magnetic recording / reproducing apparatus, comprising: a microprocessor for rewriting the storage content of the memory means so that the addition ratio of the digital filter means is substantially zero. 6. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the capstan motor, a frequency dividing means of the detected speed signal (N is the integer of 1 or more) N to divide the first reference signal or The phase difference between the two is converted into a digital value by a counter which is preset in synchronization with one of the second reference signals and is latched by a control signal reproduced from the tape or an output of the frequency dividing means. Digital phase conversion means; memory means for storing and controlling the above-mentioned N frequency division and the above-mentioned cyclic count number M (an integer of 1 or more) of the second reference signal; Means for controlling the phase of the stun motor, and the latched digital phase conversion when switching from the first reference signal to the second reference signal. Force so as to be continuous without substantially changing,
A magnetic recording / reproducing apparatus, comprising: a microprocessor for setting the cyclic count number M of the second reference signal from a small value M0 to a large value M1. 7. A motor control device for performing phase control and speed control.
In the magnetic recording and reproducing apparatus having a location, and means for detecting the rotational speed of the capstan motor, a frequency dividing means of the detected speed signal (N is the integer of 1 or more) N to divide the first reference signal or The phase difference between the two is converted into a digital value by a counter which is preset in synchronization with one of the second reference signals and is latched by a control signal reproduced from the tape or an output of the frequency dividing means. Digital phase conversion means; memory means for storing and controlling the above-mentioned N frequency division and the above-mentioned cyclic count number M (an integer of 1 or more) of the second reference signal; Means for controlling the phase of the stun motor, and a first means for switching the preset trigger from a first reference signal to a second reference signal.
A second timing for switching the latch signal from the control signal to the output of the frequency dividing means, a third timing for changing N of the memory means from a small value N0 to a large value N1. A magnetic recording / reproducing apparatus, comprising: a microprocessor for controlling a fourth timing at which the cyclic count number M of the second reference signal is changed from a small value M0 to a large value M1. 8. A motor control device for performing phase control and speed control.
In a magnetic recording / reproducing apparatus having a position, a means for detecting a rotational speed of a capstan motor, frequency dividing means for dividing the detected speed signal by N (N is an integer of 1 or more), and reproducing from a tape. First digital phase conversion means for converting the phase difference between the control signal and the first reference signal into a digital quantity; and converting the phase difference between the output of the frequency dividing means and the second reference signal into a digital quantity. Second digital phase conversion means, the above-mentioned N frequency division and the second
Memory means for storing and controlling the cyclic count number M (an integer equal to or greater than 1) of the reference signal, and a switching output between the first digital phase conversion means and the second digital phase conversion means. Switching means for providing a phase control signal;
A first timing for changing the value of N of the memory means from a small value N0 to a large value N1;
And a microprocessor for controlling a third timing indicating switching from the digital phase conversion means to the second digital phase conversion means. 9. The magnetic device according to claim 1, further comprising a circuit component in which the filter means, the memory means, and the microprocessor are integrated on the same chip. Recording and playback device. 10. A magnetic recording / reproducing apparatus according to claim 6, further comprising a circuit component in which said means and a microprocessor are integrated in the same chip.