JP3097613B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a read technique when a difference between a current value flowing through a cell transistor and a current value of a reference current source is small.

[0002]

2. Description of the Related Art A read circuit of a conventional semiconductor memory device,
In particular, a readout circuit of a nonvolatile semiconductor memory device applies a potential to the gate, drain, and source of a cell transistor in which data is held, and determines the amount of current flowing through the cell transistor and the value of current flowing through a reference current source serving as a reference. In comparison, data is determined depending on whether the current value is larger or smaller than the reference current value.

In recent years, various studies have been made on a multi-valued semiconductor memory device in which one cell transistor holds two or more values of data. However, basically, the above-described read circuit method is basically followed. Is what you do. The reading method of this multi-valued semiconductor memory device is described in, for example, Japanese Patent Application Laid-Open No. 7-37393, and has a plurality of reference current sources. It is configured to perform comparative amplification.

The present invention particularly relates to a method of generating a reference current source among read circuits of a semiconductor memory device. Therefore, the operation and setting of the reference current source will be described below.

[0005] As a read operation of a multi-valued semiconductor memory device, according to the above-mentioned Japanese Patent Application Laid-Open No. 7-37393, an example of a read-out operation of a multi-valued cell transistor in which one cell transistor holds a plurality of data. A method as shown in FIG. 7 is disclosed as the setting of the reference current source therein. Specifically, transistors having different conductances are prepared as reference current sources, and current values flowing through individual current sources are used as reference current sources. In FIG. 7, one transistor N7-1, two transistors N7-2 and N7-3 whose drains are commonly connected, and three transistors N7-4, N7-5 and N7- whose drains are commonly connected.
6 and a total of three reference current sources, and the gates of the transistors are commonly biased.

FIG. 7 schematically shows the number of transistors. For example, when a reference current source having a large current value is required, a transistor having a small resistance value is prepared. Are prepared, and the value of the current flowing through each reference current source is changed.

When an actual read operation is performed,
A multi-value read operation is performed by comparing and amplifying a current value flowing through each reference current source and a current value flowing through the cell transistor, and logically synthesizing the respective compared and amplified data.

[0008]

In this conventional semiconductor memory device, in particular, in the case of a multi-valued type, a malfunction occurs when a power supply potential of a word line fluctuates. Therefore, the width of the power supply potential variation is extremely small. As a matter of course, there was a problem that it was weak to power supply noise.

FIG. 9 shows a VG-ID characteristic (a gradient characteristic of a drain current with respect to a word line power supply potential) of a cell transistor and a V of a reference current source in a multilevel semiconductor memory device.
This shows an ideal type of G-ID characteristic. The slope of the VG-ID of each reference current source and the VG of the cell transistor
VG corresponding to the word line potential because the slope of ID is the same and each reference current source has a different threshold potential
No matter what potential is taken, the relationship between the reference current source and the value of the current flowing through the cell transistor is always fixed as long as the current flows, and even if the word line potential changes, correct read data is always obtained. It is obtained.

On the other hand, FIG. 8 shows the VG-ID characteristic of the reference current source shown in FIG.
It shows the ID characteristics. In the method of adjusting the current value of the reference current source only by the conductance of the transistor,
VG of one of three reference current sources prepared for multi-value
-Even if the conductance is set so that the slope of the ID characteristic approximates the slope of the VG-ID characteristic of the cell transistor, it is necessary to provide a plurality of reference current sources. If the slopes are the same, the threshold potentials are the same, so that the multi-valued read operation itself cannot be performed.

As a result, when performing a multi-valued read operation, the vertical relationship between the current value flowing through the cell transistor and the current value flowing through the reference current source changes when the potential of VG changes. VG, that is, the potential of the word line, must be very finely adjusted at all times, and even if it is adjusted, if a slight power supply noise is put on during operation, a malfunction easily occurs. Therefore, there is a problem that high-speed operation is difficult, the power supply potential is not easily changed, and a margin of noise immunity is extremely narrow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the current flowing through the reference current source and the current flowing through the cell transistor even if the power supply potential, particularly the word line potential, fluctuates. It is an object of the present invention to provide a semiconductor memory device capable of realizing a stable operation by realizing a reference current source with a fixed upper and lower relationship with a value, and expanding an operating power supply potential and a margin of noise resistance.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, information obtained by comparing and amplifying a current flowing in a selected cell transistor and a current flowing in a reference current source is stored in the selected cell. Means for approximating the slope of the drain current with respect to the word line power supply potential of the cell transistor in the semiconductor memory device as the storage information of the transistor and the slope of the drain current with respect to the word line power supply potential of the transistor of the reference current source; Means for arbitrarily setting the threshold potential of the source.

[0014]

Embodiments of the present invention will be described below. In the embodiment of the present invention, in order to correctly perform a read operation even if the power supply potential for a word line fluctuates, first, the VG-ID characteristics of the cell transistor and the apparent voltage of the transistor as a reference current source (reference current source) are determined. VG
A method of matching the inclination of one ID characteristic is adopted. One method for this is to adjust the gate length and gate width of a transistor as a reference current source. It is also possible to divide the gate potential of a transistor as a reference current source from a certain power supply.

The threshold potential can be arbitrarily changed by applying the gate potential of the transistor of the reference current source at a fixed potential lower than the word line potential. By using this and the method of matching the apparent VG-ID characteristics together, even if the power supply potential for the word line fluctuates, the read operation can be performed correctly.

First, there is a method of dividing a potential, which is a constant potential from the word line potential, and applying the divided voltage to the gate of the reference current source.

Second, there is a method of applying a potential which is lower than the word line potential to the gate of the transistor of the reference current source in which the slope of the VG-ID characteristic is matched with the cell transistor.

In the preferred embodiment of the present invention, the potential of the word line power supply (VW1) is reduced by a constant potential and input to the transistors (N1-3 to N1-5 in FIG. 1) to supply the word line power supply (VW1). VW1) clamp potential,
The individual clamp potentials are divided by resistors and input to reference current source transistors (N1-6 to N1-8 in FIG. 1). As a result, the threshold voltage Vt of the reference current source transistor can be individually set by the clamp potential (apparently Vt can be changed freely), and the slope of VG-ID can be adjusted by the resistance ratio. The word potential versus ID characteristic of a certain reference current source is equal to the inclination of the cell transistor, and the individual threshold voltage Vt can be set, so that the device operates correctly even if the power supply potential changes.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a circuit constituting a reference current source (also referred to as a reference current source, a reference current source) in a first embodiment of the present invention.

Referring to FIG. 1, the method of setting the reference current source is to divide a potential, which is a constant potential from the word line potential, and apply the resulting voltage to the gate of the transistor to use the reference current source.

First, the main circuit configuration will be described. This embodiment is a circuit for setting three reference current sources having different threshold potentials, N1-6, N1-7, and N1.
Reference numeral 1-8 denotes a transistor serving as a reference current source. The resistance R1-1, the resistance R1-2, and the resistance R1- surrounded by a broken line in the drawing.
3, P-type transistor P1-1, P-type transistor P1
−2, N-type transistor N1-1, N-type transistor N
The circuit consisting of 1-2 is a circuit group for lowering the word line potential VW1 by a constant potential. N-type transistor N1
-3, resistors R1-4, R1-5, N-type transistor N1
-4, resistors R1-6, R1-7, N-type transistor N1
−5 and the resistors R1-8 and R1-9 are each formed by combining a word line potential VW1 with one transistor and two resistors.
Is a group of three circuits for dividing the voltage by dropping a constant potential.

The circuit operation of this embodiment will be briefly described. First, FIG. 3 shows the VG-I of the cell transistor.
D characteristics and VG of Nch transistor as reference current source
-ID characteristics. As is clear from FIG.
Both the slope and the threshold potential are different. In the present embodiment, as a method for matching the gradients, in this embodiment, when the potential obtained by dividing the word line potential to a certain fixed ratio is set as VG and added to the gate of the Nch transistor, the gradient of the Nch transistor becomes small. Can be matched.

Next, a method of setting the threshold to an arbitrary value will be described. In FIG. 1, circuits in a portion surrounded by a broken line are a group of circuits for keeping the word line potential VW1 at a constant potential. Pch transistors P1-1 and P1-2
, The potential at the point C can be substantially fixed to the threshold potential of the Pch transistor P1-1. The outputs A, B, and C obtained by dividing the resistances are as shown in FIG.
It is possible to always create a state in which a constant potential drop occurs with respect to the potential change of the word line potential VW1.

The transistors N1-5, N1-4, and N1-3 to which the outputs A, B, and C are input, respectively, clamp the word line potential at a fixed potential.
The resistance is divided by the ratio for matching the slope of G-ID,
When input to each reference current source transistor, as shown in FIG. 4, each reference current source transistor N1-6, N1
−7 and N1-8 have their own thresholds, the slopes of the word potential-ID characteristics match, and an ideal reference current source can be obtained.

FIG. 5 schematically shows a read circuit using the reference current source. Referring to FIG. 5, a circuit added to the configuration shown in FIG. 1 is as follows. The circuit including the Pch transistor P1-3, the Nch transistor N1-9, and the inverter INV1-1 is a current-voltage conversion circuit that converts a current flowing through the Nch transistor N1-6 serving as a reference current source into a voltage.

Similarly, a circuit composed of Pch transistors P1-4, Nch transistor N1-10 and inverter INV1-1, and a circuit composed of Pch transistors P1-5, Nch transistor N1-11 and inverter INV1-3 also have a reference current source. Is a current-voltage conversion circuit for converting the amount of current flowing through the Nch transistor N1-7 into the amount of voltage.

MC1-1 is a memory cell transistor to be read and is a Pch transistor P1-6.
Nch transistor N1-12, inverter INV1-
4 comprises a memory cell transistor MC1-1
Is a current-to-voltage conversion circuit that converts the amount of current flowing through to a voltage amount.

DEF1-1, DEF1-2, DEF1-
Reference numeral 3 denotes a differential amplifier circuit for performing voltage conversion on the current value of the reference current source and the current value flowing through the memory cell transistor MC1-1 and then performing comparison amplification. 1 to OUT1-3.

The operation of the read circuit of this embodiment shown in FIG. 5 will be briefly described. As already described with reference to FIG. 1, the Nch transistors N1-6 to N1-8, which are reference current sources, individually supply currents of stable values. On the other hand, the memory cell transistor MC1-
A current having a value corresponding to the data held also flows. By the current-voltage conversion circuit, a potential corresponding to the reference current source and the amount of current flowing through the memory cell transistor is input to the differential amplifier circuit, and each of the differential amplifier circuits DEF1-1 to DEF
By logically synthesizing data of the outputs OUT1-1 to OUT1-3 of 1-3, the data is output as multi-valued read data.

Next, another embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a diagram showing the configuration of another embodiment of the present invention. In this embodiment, the word line pair ID shown in FIG.
The portion corresponding to the resistance division for matching the slope of (drain current) is a transistor division method, and the operation of the reference current source is stabilized at high speed at the start of operation. .

Here, parts different from the embodiment shown in FIG. 1 will be described. As in the case of FIG. 1, three transistors N1-6 to N1-8 are used as reference current sources, and their operating principles are the same. Hereinafter, a portion surrounded by a broken line in the drawing will be described.

The inclination of the word line pair ID (drain current) is set by the Nch transistors N6-1 and N6-2. These two transistors are configured with high resistance to reduce current consumption. Also N
The resistance ratio between the channel transistors N6-7 and N6-8 is N6
-1: The same as that of N6-2, but the resistance itself is set small.

Terminals V1 and V2 are High when active.
(H) Fixed. Immediately after the start of the operation, the terminal CHN becomes H, the Nch transistors N6-3 and N6-5 having the gate input of the signal of the terminal CHN are turned on, and the signal obtained by inverting the signal of the terminal CHN by the inverter INV6-1 is used as the gate input. Nch transistors NN6-4 and N6-6
FF. As a result, the Nch transistors N6-7, N6
Since 6-8 is also turned on, the gate potential of the transistor N1-6 serving as the reference current source is set to the operating potential at high speed.
Thereafter, the terminal CHN is set to L and the Nch transistor N
6-7 and N6-8 are turned off, and Nc with low power consumption is used.
The gate potentials of the Nch transistors N1-6 are supplied by the h transistors N6-1 and N6-2.

As a result, at the start of the operation, the operation is determined at a high speed by the low-resistance element, and after the stable operation, a stable reference current source with low power consumption can be provided by the high-resistance element.

The transistor N1 serving as a reference current source
-7, N1 transistors N6-9 to N6-17 and N1-
7, Nch transistors N6-17 to N6
The circuit consisting of −24 and N1-8 operates in a similar manner.

[0037]

As described above, according to the present invention,
Even if the power supply potential fluctuates, the relationship between the value of the current flowing through the reference current source and the value of the current flowing through the cell transistor is always fixed, and there is an effect that malfunction does not occur.

The reason is that, in the present invention, information obtained by comparing and amplifying a current flowing in a selected cell transistor and a current flowing in a reference current source is used as storage information of the selected cell transistor. Means for approximating the slope of the drain current of the cell transistor in the semiconductor memory device with respect to the power supply potential for the word line and the slope of the drain current of the transistor in the reference current source relative to the power supply potential for the word line; and a threshold potential of the reference current source. And a means for arbitrarily setting the value.

According to the present invention, even when noise is present, the operation of the reference current source follows the fluctuation of the power supply potential and becomes equivalent to the operation of the cell transistor. In a sensitive read operation, there is an effect that a stable operation can be performed even when an intentional potential change occurs and also when an unintended potential change occurs.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of a potential of each node of a circuit surrounded by a broken line in FIG. 1;

FIG. 3 is a diagram illustrating VG-ID characteristics of a cell transistor and a single transistor for a reference current source.

FIG. 4 is a diagram showing word potential versus ID characteristics of a reference current source transistor and a cell transistor in one embodiment of the present invention.

FIG. 5 is a diagram showing an example of a read circuit in one embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a circuit configuration of a conventional reference current source.

8 is a diagram showing VG-ID characteristics of the cell transistor and the reference current source transistor of FIG.

FIG. 9 shows VG-ID of a cell transistor and a transistor for a reference current source for realizing a multilevel semiconductor memory device.
It is a figure showing the ideal characteristic of a characteristic.

[Explanation of symbols]

VW1 Word line power supply R1-1 to R1-9 Resistance N1-1 to N1-11 N-channel MOS transistors N6-1 to N6-24, N7-1 to N7-6 N-channel MOS transistors P1-1 to P1-6 P-channel MOS transistor MC1-1 Memory cell transistor W1-1 Word line DFF1-1 to DFF1-3 Differential amplifier circuits INV1-1 to INV1-4, INV6-1 Inverters A to F, OUT1-1 to OUT1-3 CHN, V1,
V2 terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 11/4099 G11C 11/56 WPI (DIALOG)

Claims (7)

(57) [Claims] 1. A semiconductor memory device in which information obtained by comparing and amplifying a current flowing through a selected cell transistor and a current flowing through a reference current source is stored information of the selected cell transistor. Means for configuring the reference current source by a transistor, means for approximating a slope of a drain current with respect to a word line power supply potential of the cell transistor and a slope of a drain current with respect to a word line power supply potential of the transistor of the reference current source; Means for arbitrarily setting a threshold potential of the reference current source. Means for approximating a slope of a drain current of the cell transistor with respect to a power supply potential for a word line and a slope of a drain current of a transistor of the reference current source relative to a power supply potential for a word line, and optionally setting the threshold potential. 2. A method as set forth in claim 1, wherein a potential obtained by dividing a potential clamped by a potential obtained by lowering a certain potential from a word line potential is set as a gate potential of the transistor serving as the reference current source. 13. The semiconductor memory device according to claim 1. And means for arbitrarily setting a threshold potential of the reference current source, wherein a potential obtained by lowering a certain potential from a word line potential is set as a gate potential of a transistor of the reference current source. 2. The semiconductor memory device according to claim 1, wherein: And means for approximating a slope of a drain current of the cell transistor with respect to a word line power supply potential and a slope of a drain current of the reference current source transistor with respect to a word line power supply potential. The potential clamped by the reduced potential is set as the gate potential of the transistor serving as the reference current source, and the means for arbitrarily setting the threshold potential of the reference current source includes a gate length of the transistor serving as the reference current source, 4. The semiconductor memory device according to claim 1, wherein the gate width is adjusted. 5. The apparatus according to claim 1, wherein a plurality of said reference current sources are provided.
Obtain three or more values of stored information from the cell transistors;
The semiconductor memory device according to claim 1, wherein: 6. A read circuit which uses information obtained by comparing and amplifying a current flowing in a selected cell transistor and a current flowing in a reference current source as storage information of the selected cell transistor. In the semiconductor memory device, a potential obtained by lowering the potential of the word line power supply by a predetermined potential is input to the gates of a plurality of transistors to generate a clamp potential, and the clamp potential is further divided by a voltage dividing means to generate a reference current source. By inputting to the gate of the transistor, the threshold value of the reference current source transistor can be set individually, and the slope of the drain current with respect to the power supply potential for the word line of the cell transistor and the transistor of the reference current source can be apparently set. By approximating the slope of the drain current with respect to the power supply potential for the word line, correct operation is possible even if the power supply potential fluctuates. The semiconductor memory device being characterized in that the. 7. The voltage dividing means includes first and second transistors connected in series having relatively high resistance, and third and fourth transistors connected in series having relatively low resistance. Wherein the first and second transistors and the third and fourth transistors have the same resistance ratio. At the start of operation, the third and fourth transistors are turned on and the third transistor and the fourth transistor are turned on. Third, the operation of the reference current source transistor is determined by the fourth transistor, and after the stable operation, the first and second transistors are turned on, and the resistance of the first and second transistors is determined by the resistance ratio of the first and second transistors. 7. The semiconductor memory device according to claim 6, wherein a divided voltage is supplied to the reference current source transistor.