JP3098372B2 - Communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device, and more particularly to a satellite communication device having a frame generation circuit for generating a desired frame in order to generate an arbitrary different frame.

[0002]

2. Description of the Related Art Burst and continuous wave frames are constructed,
A satellite communication device that multiplexes and communicates data includes a frame generation circuit that generates a desired frame in order to generate an arbitrary different frame. For example, when performing communication by taking a frame configuration by multiplexing overhead with data such as conventional voice, a mask pattern of a timing ROM (read only memory) or a FIFO (first-in-first- Out) A frame configuration is realized by a generation circuit that controls read and write signals of the memory.

When the transmission frame is fixed or the number of types is small, the timing ROM is effective. However, when there are several types of transmission frames, a mask pattern matching the frame must be generated. Conventionally, the contents of the timing ROM are rewritten to generate different frame configurations and different frame lengths.

When a burst or continuous wave frame is formed, signals necessary for multiplexing, such as a preamble, a data multiplexing pattern, and a burst termination pattern, are written in a timing ROM, and these signals may be generated in combination. it can.

On the other hand, a frame structure can be generated by replacing the timing ROM with a rewritable RAM (random access memory). For example, by using a RAM as a rewritable address control memory and rewriting the contents of the address control memory to freely multiplex data of various timeslot numbers of many different units, the total number is fixed. It has been known that a time slot is used effectively (Japanese Patent Laid-Open No.
No. 208041).

[0006]

However, the above RA
The conventional method of generating a frame configuration using M is RAM
Only controls the timing of the frame when multiplexing.Considering some control such as storing the data from the unit actually required in the buffer and outputting it to the insertion position in the time slot is considered. Not.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide a communication device capable of generating a desired frame with the same circuit by rewriting timing data from a central processing unit using a RAM without using a timing ROM.

[0008]

Since the present invention SUMMARY OF THE INVENTION The To achieve the above object, in a communication apparatus for generating an arbitrary burst frame length, a transmission frame pulse generating circuit for generating a transmission frame pulse, said transmission frame A transmission address counter that outputs an address that gradually changes from an initial value on the basis of a pulse; a storage circuit in which software and data for controlling and monitoring a communication device and timing data of a logic circuit are written; A central processing unit that sets parameters including an initial value of the transmission address counter and a mode of a transmission frame based on storage software and timing data of a circuit, and logic data respectively corresponding to a plurality of transmission modes are stored in a known address in advance. And the output of the transmission address counter is And, and receives the output of the central processing unit as an upper address specifying the transmission mode,
A transmission memory rewritable to generate a burst frame by outputting a logic data corresponding to the transmission mode of the transmission mode are sequentially rewritten specified at a timing corresponding to the input address, logic output from the transmission memory <br / > a multiplexing means for multiplexing the frame configuration of transmission data in the transmission mode based on Kudeta, and a sending circuit for transmitting the multi <br/> heavy signal outputted from said multiplexing means.

Further, the present invention provides a receiver circuit for outputting a multiplexed signal by demodulating the received signal, a reception frame pulse generating circuit for generating a frame pulse from the multi <br/> heavy signal outputted from the reception circuit, A reception address counter that outputs an address that gradually changes from an initial value set by the central processing unit based on a frame pulse from the reception frame pulse generation circuit, and that reception timing data is written by the central processing unit. A rewritable reception memory for reading timing data corresponding to an output address of the reception address counter;
And a means for separating and error-correcting and decoding the multiplexed signal output from the multiplexed signal based on the timing data from the reception memory and outputting the multiplexed signal.

[0010]

According to the present invention, the central processing unit accesses the address where the timing data is written from the storage circuit where the software is written, and transfers the data to the transmission memory. The transmission memory outputs a corresponding signal by accessing an address according to the output of the transmission address counter.

The output signal of the transmission memory is a mode switching signal for forming a frame. This mode switching signal multiplexes transmission data into a frame configuration by data multiplexing means. The multiplex signal of the transmission data is transmitted to the satellite via the transmission circuit. Therefore, in the present invention, any different frame configuration can be generated by the same circuit simply by arbitrarily rewriting the mode and the timing data to be written to the transmission memory under the control of the central processing unit.

Also, the reception memory is written with reception timing data by the central processing unit, and the timing data corresponding to the output address of the reception address counter is read out. Therefore, it is possible to separate data of various reception frames by the same circuit. it can.

[0013]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of one embodiment of the present invention. In FIG. 1, a satellite communication device 10 is a ground station that communicates with a satellite, generates and transmits a desired frame, and receives a frame having an arbitrary configuration. The satellite communication device 10 includes a transmission unit including a transmission frame pulse generation circuit 11, a transmission address counter 12, a central processing unit (CPU) 13, a ROM 14, a transmission RAM 15, a data multiplexing circuit and a logic circuit 16, and a transmission circuit 17. , A reception circuit 21, a reception frame pulse generation circuit 22, a reception address counter 23, a reception R
AM 24, data separation circuit and logic circuit 25, and CPU
13 and the ROM 14 constitute a receiving unit. That is, the CPU 13 and the ROM 14 are shared by the transmitting unit and the receiving unit.

The transmission frame pulse generation circuit 11 generates a transmission frame pulse. The transmission address counter 12 counts addresses based on transmission frame pulses. The ROM 14 has multiplexed software and data for controlling and monitoring the satellite communication device 10, and has written therein timing data of logic circuits. CPU 13 is ROM1
4, the address counters 12 and 2
3 and parameters such as the mode of the transmission frame.

The transmission RAM 15 outputs the timing signal corresponding to the count value using the transmission timing data and the output of the transmission address counter 12 as addresses from the contents of the ROM 14. The data multiplexing circuit and the logic circuit 16 perform processing such as data multiplexing for multiplexing transmission data in a frame configuration using the timing signal from the transmission RAM 15 and data error correction. The transmission circuit 17 outputs the multiplexed frame-structured data to the satellite as a transmission signal in a predetermined frequency band.

The receiving circuit 21 demodulates data from a signal received from a satellite. The reception frame pulse generation circuit 22 detects a synchronization word from the reception data and generates a reception frame pulse. The reception address counter 23 counts the address from the initial value set by the CPU 13 based on the reception frame pulse. The reception RAM 24 uses the output of the reception address counter 23 as an address and outputs a timing signal corresponding to the count value. The data separation circuit and the logic circuit 25 perform data separation for separating data using a timing signal, error correction, and decoding.

Next, the operation of this embodiment will be described.
The transmission frame pulse generation circuit 11 generates the frame pulse shown in FIG. 2A and supplies it to the transmission address counter 12 as a load signal. Transmission address counter 12
The CPU 13 sets an initial value from the CPU 13, counts up from the initial value at the time of input of the frame pulse, and outputs an address signal whose value gradually changes as shown in FIG. 2B. In FIG. 2B, the initial value is “0”, and
The lower 8 bits of the address signal when the upper address is "0" are shown in hexadecimal notation.

The CPU 13 accesses the address where the timing data is written from the ROM 14 in which the software is written, and transfers the data to the transmission RAM 15. When the address according to the output of the transmission address counter 12 is accessed, the transmission RAM 15 outputs a corresponding signal. FIGS. 2C and 2D show two bits of the output of the transmission RAM 15, respectively.

The output signal of the transmission RAM 15 is a clock for a scrambler or FEC (forward error correction) encoder, or a mode switching signal for forming a mask signal, a gate signal, or a frame thereof. The mode switching signal is supplied to the data multiplexing circuit and the logic circuit 16, where the transmission data is generated in a frame configuration. FIGS. 2E and 2F show multiplexed signals generated by the output signals of the transmission RAM 15 shown in FIGS. 2C and 2D, respectively, in which transmission data is multiplexed in a frame configuration. These multiplexed signals are further time-division multiplexed by a data multiplexing circuit and a logic circuit 16 as shown in FIG.

The receiving circuit 21 receives the signal shown in FIG.
The received multiplexed signal shown in (G) is demodulated and supplied to the received frame pulse generation circuit 22, the data separation circuit and the logic circuit 25. The reception frame pulse generation circuit 22 generates a frame pulse from the demodulated multiplex signal,
It is input to the reception address counter 23 as a load signal. The reception address counter 23 has an initial value set by the CPU 13 and counts up from the initial value at the time of input of the frame pulse to output an address signal.

The reception RAM 24 outputs a corresponding signal by accessing an address according to the output of the reception address counter 23. The output signal is a clock of a descrambler, an FEC decoder, or the like, or a mask signal thereof. The data separation circuit and the logic circuit 25 separate the data from the demodulated multiplex signal based on the output signal of the reception RAM 24. This receiving unit can be realized with the same configuration as the transmitting unit, and only the output signal of the RAM needs to be changed and used.

By the way, if the frame length is fixed, various signals may be written in the timing ROM.
To change the frame length, for example, to increase the number of bits in one frame, it is necessary to prepare a timing ROM whose contents are rewritten. However, according to the present embodiment, the frame length can be changed or corrected only by rewriting the contents of the transmission RAM 15.

The method for rewriting the contents of the transmission RAM 15 may be to control only the timing of the frame at the time of multiplexing, as described in the data multiplexing method described in the above-mentioned publication. Based on the output of the counter 12, the transmission RAM 15 generates the timing of the entire frame configuration. Although the timing data is stored in the ROM 14 in which software is written, it is easy to rewrite the contents because it is a RAM.

Specifically, the ROM 14 and the transmission RAM 15
Depending on the capacity of the transmission RAM 15, some different timing data is written in the upper address of the transmission RAM 15 and the upper address is used as a transmission mode, so that the transmission of data at different timings is performed regardless of the output of the address counter 12. By switching the mode, the output can be switched.

Although the frame length is usually fixed, even if the end of the preamble or burst is different from the frame length, only the initial value of the start address of the address counter 12 and the setting of the transmission mode are changed. And can be easily realized. 2H and 2I show two bits of the output of the transmission RAM 15 when the upper address of the output of the address counter 12 is changed from, for example, "0" to "1". Thereby, the output signal of the data multiplexing circuit and the logic circuit 16 can be in a format in which the transmission data 3 is inserted between the transmission data 1 and 2 as shown in FIG.

It should be noted that the synchronization word can be multiplexed in the data multiplexing circuit and the logic circuit 16. 3A shows the transmission frame pulse, and FIGS. 3C and 3D show the two bits of the output signal of the transmission RAM 15, respectively, whereby the data multiplexing circuit and the logic circuit 16 are arranged as shown in FIG. 3B. The synchronization word is multiplexed with the transmission data, and the output of the logic circuit is further multiplexed as shown in FIG. In this case, the reception frame pulse generation circuit 22 detects the synchronization word in the received and demodulated signal and generates a frame pulse.

Next, switching of the transmission mode will be described. As shown in the memory map of FIG. 5, the transmission RAM 15 stores the preamble logic data of the transmission mode 1 in the storage area I of the addresses “000” to “0FF”, and the addresses “100” to “1FF”. In the storage area II of "", logic data for frame data of transmission mode 2 is stored, and further, addresses "200" to "200" are stored.
It is assumed that the storage area III of 2FF "stores the logic data for the end data of the burst of the transmission mode 3.

In this case, the transmission frame pulse generation circuit 1
When a frame pulse as shown in FIG. 4 (A) is output from 1, an address as shown in FIG. 4 (C) is output from the transmission address counter 12 and supplied to the transmission RAM 15, while the address is transmitted from the CPU 13 to the transmission RAM 15. Are supplied to the upper 4 bits of.

As a result, first, the transmission RA
One frame period during which "0" is output to M15 is shown in FIG.
As shown in (B), the transmission mode 1 is set and the transmission RAM 15
, The preamble logic data is read from the storage area I, thereby causing the data multiplexing and logic circuit 16 to output the preamble data d1 as shown in FIG.

Subsequently, when "1" is output from the CPU 13 to the transmission RAM 15 for the next three frame periods,
As shown in (B), the transmission mode becomes the transmission mode 2 and the transmission RAM 15
Logic data for frame data is read from the storage area II of the
The frame data is read as shown in FIG. This frame data is indicated by d2, d3 and d4 in FIG. 4 (D), and each has, for example, a synchronization word.

When "2" is output from the CPU 13 to the transmission RAM 15 for the next one frame period,
As shown in (B), the transmission mode becomes the transmission mode 3 and the transmission RAM 15
Logic data for burst end data is read from the storage area III, and the data multiplexing and logic circuit 16 multiplexes and outputs burst end data as indicated by d5 in FIG. 4D. As described above, the transmission mode can be sequentially switched to 1, 2, and 3 using the upper address of the transmission RAM 15 as the mode switching signal.

Note that the memory capacity of the transmission RAM 15 is 16
When it is from (00) _H to (FF) _{H in} hexadecimal notation,
The mode can be switched by sequentially rewriting the data in the transmission mode 1, the transmission mode 2, and the transmission mode 3 when the contents are not used.

Similarly, when it is desired to generate a different frame when the capacity of the transmission RAM 15 is small, the transmission RA
It is necessary to rewrite the contents of M15, but this is effective when a slight change is desired. The same applies to the reception RAM 24.

[0034]

As described above, according to the present invention,
In a device that forms and communicates a frame using a burst or a continuous wave, a burst frame can be generated by combining arbitrary different frames in the same circuit simply by rewriting the mode or the timing data to be written to the storage circuit.

Further, a central processing unit and a storage circuit in which a program is stored are indispensable, and rewritable storage is provided by storing data for generating timing data using an extra area of the storage circuit. A general-purpose configuration can be obtained by rewriting desired timing data in a circuit. The circuit configuration is not complicated by using a rewritable storage circuit, and all circuits can be realized by a logic circuit. Therefore, the size of the entire apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a timing chart of FIG. 1 for explaining transmission mode switching.

FIG. 5 is a diagram illustrating an example of a memory map of a transmission RAM.

[Explanation of symbols]

 Reference Signs List 10 satellite communication device 11 transmission frame pulse generation circuit 12 transmission address counter 13 central processing unit (CPU) 14 read only memory (ROM) 15 transmission random access memory (RAM) 16 data multiplexing circuit and logic circuit 17 transmission circuit Reference Signs List 21 reception circuit 22 reception frame pulse generation circuit 23 reception address counter 24 reception random access memory (RAM) 25 data separation circuit and logic circuit

Claims (2)

(57) [Claims] 1. A communication apparatus for generating a burst frame of an arbitrary length, comprising: a transmission frame pulse generation circuit for generating a transmission frame pulse; and outputting an address gradually changing from an initial value based on the transmission frame pulse. A transmission address counter, a storage circuit in which software and data for controlling and monitoring a communication device and timing data of a logic circuit are written, and an initial value of the transmission address counter based on storage software and timing data of the storage circuit. A central processing unit for setting a parameter including a value and a mode of a transmission frame; logic data respectively corresponding to a plurality of transmission modes are stored in a known address in advance; an output of the transmission address counter is set as a lower address; and The output of the central processing unit to the transmission mode. Receiving as an upper address designating a de, and rewritable transmission memory to generate a burst frame by outputting a logic data corresponding to the transmission mode of the transmission mode are sequentially rewritten specified at a timing corresponding to the input address, the transmission communication device, characterized in that it comprises a multiplexing means for multiplexing the frame configuration of transmission data in the transmission mode based on the logic data output from the memory, and a transmission circuit for transmitting the multiplexed signal outputted from said multiplexing means. 2. A receiving circuit for demodulating a received signal to output a multiplexed signal, a receiving frame pulse generating circuit for generating a frame pulse from the multiplexed signal output from the receiving circuit, A reception address counter that outputs an address that gradually changes from an initial value set by the central processing unit with reference to a frame pulse, and reception timing data written by the central processing unit, and an output of the reception address counter A rewritable receiving memory from which timing data corresponding to the address is read out; and a means for separating and error-correcting and decoding the multiplexed signal output from the receiving circuit based on the timing data from the receiving memory and outputting the multiplexed signal. The communication device according to claim 1, wherein: